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arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
Add basic chip support for Mediatek 8183, include uart node with correct uart clocks, pwrap device Add clock controller nodes, include topckgen, infracfg, apmixedsys and subsystem. Signed-off-by: Ben Ho <Ben.Ho@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Ben Ho
Matthias Brugger
parent
2a368ed7b5
commit
e526c9bc11
@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
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31
arch/arm64/boot/dts/mediatek/mt8183-evb.dts
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31
arch/arm64/boot/dts/mediatek/mt8183-evb.dts
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@ -0,0 +1,31 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Ben Ho <ben.ho@mediatek.com>
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* Erin Lo <erin.lo@mediatek.com>
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*/
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/dts-v1/;
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#include "mt8183.dtsi"
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/ {
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model = "MediaTek MT8183 evaluation board";
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compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
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aliases {
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serial0 = &uart0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x80000000>;
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};
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chosen {
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stdout-path = "serial0:921600n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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311
arch/arm64/boot/dts/mediatek/mt8183.dtsi
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311
arch/arm64/boot/dts/mediatek/mt8183.dtsi
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@ -0,0 +1,311 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Ben Ho <ben.ho@mediatek.com>
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* Erin Lo <erin.lo@mediatek.com>
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*/
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "mediatek,mt8183";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x000>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x001>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x002>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x003>;
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enable-method = "psci";
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x100>;
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enable-method = "psci";
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x101>;
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enable-method = "psci";
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x102>;
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enable-method = "psci";
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x103>;
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enable-method = "psci";
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};
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};
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pmu-a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
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};
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pmu-a73 {
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compatible = "arm,cortex-a73-pmu";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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clk26m: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <4>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x40000>, /* GICD */
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<0 0x0c100000 0 0x200000>, /* GICR */
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<0 0x0c400000 0 0x2000>, /* GICC */
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<0 0x0c410000 0 0x1000>, /* GICH */
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<0 0x0c420000 0 0x2000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
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ppi-partitions {
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ppi_cluster0: interrupt-partition-0 {
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affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
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};
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ppi_cluster1: interrupt-partition-1 {
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affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
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};
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};
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};
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mcucfg: syscon@c530000 {
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compatible = "mediatek,mt8183-mcucfg", "syscon";
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reg = <0 0x0c530000 0 0x1000>;
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#clock-cells = <1>;
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};
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sysirq: interrupt-controller@c530a80 {
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compatible = "mediatek,mt8183-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x0c530a80 0 0x50>;
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};
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt8183-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt8183-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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};
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apmixedsys: syscon@1000c000 {
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compatible = "mediatek,mt8183-apmixedsys", "syscon";
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reg = <0 0x1000c000 0 0x1000>;
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#clock-cells = <1>;
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};
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pwrap: pwrap@1000d000 {
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compatible = "mediatek,mt8183-pwrap";
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reg = <0 0x1000d000 0 0x1000>;
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reg-names = "pwrap";
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interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
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<&infracfg CLK_INFRA_PMIC_AP>;
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clock-names = "spi", "wrap";
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt8183-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x1000>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt8183-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x1000>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt8183-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x1000>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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audiosys: syscon@11220000 {
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compatible = "mediatek,mt8183-audiosys", "syscon";
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reg = <0 0x11220000 0 0x1000>;
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#clock-cells = <1>;
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};
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mfgcfg: syscon@13000000 {
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compatible = "mediatek,mt8183-mfgcfg", "syscon";
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reg = <0 0x13000000 0 0x1000>;
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#clock-cells = <1>;
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};
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt8183-mmsys", "syscon";
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reg = <0 0x14000000 0 0x1000>;
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#clock-cells = <1>;
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};
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imgsys: syscon@15020000 {
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compatible = "mediatek,mt8183-imgsys", "syscon";
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reg = <0 0x15020000 0 0x1000>;
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#clock-cells = <1>;
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};
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vdecsys: syscon@16000000 {
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compatible = "mediatek,mt8183-vdecsys", "syscon";
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reg = <0 0x16000000 0 0x1000>;
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#clock-cells = <1>;
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};
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vencsys: syscon@17000000 {
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compatible = "mediatek,mt8183-vencsys", "syscon";
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reg = <0 0x17000000 0 0x1000>;
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#clock-cells = <1>;
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};
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ipu_conn: syscon@19000000 {
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compatible = "mediatek,mt8183-ipu_conn", "syscon";
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reg = <0 0x19000000 0 0x1000>;
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#clock-cells = <1>;
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};
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ipu_adl: syscon@19010000 {
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compatible = "mediatek,mt8183-ipu_adl", "syscon";
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reg = <0 0x19010000 0 0x1000>;
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#clock-cells = <1>;
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};
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ipu_core0: syscon@19180000 {
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compatible = "mediatek,mt8183-ipu_core0", "syscon";
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reg = <0 0x19180000 0 0x1000>;
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#clock-cells = <1>;
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};
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ipu_core1: syscon@19280000 {
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compatible = "mediatek,mt8183-ipu_core1", "syscon";
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reg = <0 0x19280000 0 0x1000>;
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#clock-cells = <1>;
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};
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camsys: syscon@1a000000 {
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compatible = "mediatek,mt8183-camsys", "syscon";
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reg = <0 0x1a000000 0 0x1000>;
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#clock-cells = <1>;
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};
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};
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};
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