From e50bf385bfadeaacfb8af07b9b78dcfdef339981 Mon Sep 17 00:00:00 2001 From: Maurus Cuelenaere Date: Mon, 19 Jul 2010 09:40:50 +0100 Subject: [PATCH] USB: s3c-hsotg: Add support for external USB clock The PLL that drives the USB clock supports 3 input clocks: 12, 24 and 48Mhz. This patch adds support to the USB driver for setting the correct register bit according to the given clock. This depends on the following patch: [PATCH] ARM: S3C64XX: Add USB external clock definition Signed-off-by: Maurus Cuelenaere Signed-off-by: Ben Dooks Signed-off-by: Greg Kroah-Hartman --- drivers/usb/gadget/s3c-hsotg.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c index 825b6ca62941..a4e0b0fa0191 100644 --- a/drivers/usb/gadget/s3c-hsotg.c +++ b/drivers/usb/gadget/s3c-hsotg.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -2798,6 +2799,7 @@ static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg, */ static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg) { + struct clk *xusbxti; u32 osc; writel(0, S3C_PHYPWR); @@ -2805,6 +2807,23 @@ static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg) osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0; + xusbxti = clk_get(hsotg->dev, "xusbxti"); + if (xusbxti && !IS_ERR(xusbxti)) { + switch (clk_get_rate(xusbxti)) { + case 12*MHZ: + osc |= S3C_PHYCLK_CLKSEL_12M; + break; + case 24*MHZ: + osc |= S3C_PHYCLK_CLKSEL_24M; + break; + default: + case 48*MHZ: + /* default reference clock */ + break; + } + clk_put(xusbxti); + } + writel(osc | 0x10, S3C_PHYCLK); /* issue a full set of resets to the otg and core */