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drm/i915/hsw: Flush RING_IMR changes before changing the global GT IMR (vecs)

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Haswell also requires the RING_IMR flush for its unique vebox setup to
avoid losing interrupts, as per 476af9c260 ("drm/i915/gen6: Flush
RING_IMR changes before changing the global GT IMR"):

On Baytail, notably, we can still detect missed interrupt syndrome
(where we never spot a completed request). In this case, it can be
alleviated by always keeping the interrupt unmasked, implying that the
interrupt is being lost in the window after modifying the IMR. (This is
the reason we still have the posting reads on enable_irq, if we remove
them we miss interrupts!) Having narrowed the issue down to the IMR,
rather than keeping it always enabled, applying the usual posting
read/flush of the RING_IMR before unmasking the GT IMR also seems to
prevent the missed interrupt. So be it.

References: 476af9c260 ("drm/i915/gen6: Flush RING_IMR changes before changing the global GT IMR")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190105115647.4970-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson 2019-01-05 11:56:47 +00:00
parent 963cc126d3
commit e4fc69f24b
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/i915/intel_ringbuffer.c
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@ -996,6 +996,10 @@ hsw_vebox_irq_enable(struct intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
/* Flush/delay to ensure the RING_IMR is active before the GT IMR */
POSTING_READ_FW(RING_IMR(engine->mmio_base));
gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask);
}