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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 15:40:53 +07:00
[libata sata_mv] add 6042 support, fix 60xx/50xx EDMA configuration
This commit is contained in:
Jeff Garzik
parent
d6fb89bf6b
commit
e4e7b89280
@ -37,7 +37,7 @@
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#include <asm/io.h>
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#define DRV_NAME "sata_mv"
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#define DRV_VERSION "0.5"
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#define DRV_VERSION "0.6"
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enum {
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/* BAR's are enumerated in terms of pci_resource_start() terms */
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@ -228,7 +228,9 @@ enum {
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MV_HP_ERRATA_50XXB2 = (1 << 2),
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MV_HP_ERRATA_60X1B2 = (1 << 3),
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MV_HP_ERRATA_60X1C0 = (1 << 4),
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MV_HP_50XX = (1 << 5),
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MV_HP_ERRATA_XX42A0 = (1 << 5),
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MV_HP_50XX = (1 << 6),
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MV_HP_GEN_IIE = (1 << 7),
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/* Port private flags (pp_flags) */
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MV_PP_FLAG_EDMA_EN = (1 << 0),
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@ -237,6 +239,9 @@ enum {
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#define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
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#define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
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#define IS_GEN_I(hpriv) IS_50XX(hpriv)
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#define IS_GEN_II(hpriv) IS_60XX(hpriv)
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#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
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enum {
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/* Our DMA boundary is determined by an ePRD being unable to handle
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@ -255,6 +260,8 @@ enum chip_type {
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chip_5080,
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chip_604x,
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chip_608x,
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chip_6042,
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chip_7042,
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};
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/* Command ReQuest Block: 32B */
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@ -265,6 +272,14 @@ struct mv_crqb {
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u16 ata_cmd[11];
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};
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struct mv_crqb_iie {
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u32 addr;
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u32 addr_hi;
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u32 flags;
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u32 len;
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u32 ata_cmd[4];
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};
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/* Command ResPonse Block: 8B */
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struct mv_crpb {
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u16 id;
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@ -328,6 +343,7 @@ static void mv_host_stop(struct ata_host_set *host_set);
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static int mv_port_start(struct ata_port *ap);
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static void mv_port_stop(struct ata_port *ap);
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static void mv_qc_prep(struct ata_queued_cmd *qc);
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static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
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static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
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static irqreturn_t mv_interrupt(int irq, void *dev_instance,
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struct pt_regs *regs);
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@ -430,6 +446,33 @@ static const struct ata_port_operations mv6_ops = {
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.host_stop = mv_host_stop,
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};
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static const struct ata_port_operations mv_iie_ops = {
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.port_disable = ata_port_disable,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.phy_reset = mv_phy_reset,
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.qc_prep = mv_qc_prep_iie,
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.qc_issue = mv_qc_issue,
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.eng_timeout = mv_eng_timeout,
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.irq_handler = mv_interrupt,
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.irq_clear = mv_irq_clear,
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.scr_read = mv_scr_read,
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.scr_write = mv_scr_write,
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.port_start = mv_port_start,
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.port_stop = mv_port_stop,
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.host_stop = mv_host_stop,
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};
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static const struct ata_port_info mv_port_info[] = {
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{ /* chip_504x */
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.sht = &mv_sht,
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@ -467,6 +510,21 @@ static const struct ata_port_info mv_port_info[] = {
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.udma_mask = 0x7f, /* udma0-6 */
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.port_ops = &mv6_ops,
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},
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{ /* chip_6042 */
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.sht = &mv_sht,
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.host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
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.pio_mask = 0x1f, /* pio0-4 */
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.udma_mask = 0x7f, /* udma0-6 */
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.port_ops = &mv_iie_ops,
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},
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{ /* chip_7042 */
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.sht = &mv_sht,
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.host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
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MV_FLAG_DUAL_HC),
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.pio_mask = 0x1f, /* pio0-4 */
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.udma_mask = 0x7f, /* udma0-6 */
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.port_ops = &mv_iie_ops,
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},
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};
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static const struct pci_device_id mv_pci_tbl[] = {
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@ -477,6 +535,7 @@ static const struct pci_device_id mv_pci_tbl[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
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{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
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{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6042), 0, 0, chip_6042},
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{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
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{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
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@ -767,6 +826,33 @@ static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
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dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
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}
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static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
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{
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u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
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/* set up non-NCQ EDMA configuration */
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cfg &= ~0x1f; /* clear queue depth */
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cfg &= ~EDMA_CFG_NCQ; /* clear NCQ mode */
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cfg &= ~(1 << 9); /* disable equeue */
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if (IS_GEN_I(hpriv))
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cfg |= (1 << 8); /* enab config burst size mask */
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else if (IS_GEN_II(hpriv))
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cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
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else if (IS_GEN_IIE(hpriv)) {
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cfg |= (1 << 23); /* dis RX PM port mask */
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cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
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cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
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cfg |= (1 << 18); /* enab early completion */
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cfg |= (1 << 17); /* enab host q cache */
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cfg |= (1 << 22); /* enab cutthrough */
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}
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writelfl(cfg, port_mmio + EDMA_CFG_OFS);
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}
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/**
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* mv_port_start - Port specific init/start routine.
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* @ap: ATA channel to manipulate
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@ -780,6 +866,7 @@ static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
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static int mv_port_start(struct ata_port *ap)
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{
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struct device *dev = ap->host_set->dev;
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struct mv_host_priv *hpriv = ap->host_set->private_data;
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struct mv_port_priv *pp;
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void __iomem *port_mmio = mv_ap_base(ap);
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void *mem;
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@ -823,17 +910,26 @@ static int mv_port_start(struct ata_port *ap)
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pp->sg_tbl = mem;
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pp->sg_tbl_dma = mem_dma;
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writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
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EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
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mv_edma_cfg(hpriv, port_mmio);
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writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
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writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
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port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
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writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
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writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
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if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
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writelfl(pp->crqb_dma & 0xffffffff,
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port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
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else
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writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
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writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
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if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
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writelfl(pp->crpb_dma & 0xffffffff,
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port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
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else
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writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
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writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
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port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
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@ -954,9 +1050,8 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
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struct ata_taskfile *tf;
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u16 flags = 0;
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if (ATA_PROT_DMA != qc->tf.protocol) {
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if (ATA_PROT_DMA != qc->tf.protocol)
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return;
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}
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/* the req producer index should be the same as we remember it */
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assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
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@ -965,9 +1060,8 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
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/* Fill in command request block
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*/
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if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
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if (!(qc->tf.flags & ATA_TFLAG_WRITE))
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flags |= CRQB_FLAG_READ;
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}
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assert(MV_MAX_Q_DEPTH > qc->tag);
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flags |= qc->tag << CRQB_TAG_SHIFT;
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@ -1022,9 +1116,76 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
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mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
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mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
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if (!(qc->flags & ATA_QCFLAG_DMAMAP)) {
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if (!(qc->flags & ATA_QCFLAG_DMAMAP))
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return;
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mv_fill_sg(qc);
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}
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/**
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* mv_qc_prep_iie - Host specific command preparation.
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* @qc: queued command to prepare
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*
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* This routine simply redirects to the general purpose routine
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* if command is not DMA. Else, it handles prep of the CRQB
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* (command request block), does some sanity checking, and calls
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* the SG load routine.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct mv_port_priv *pp = ap->private_data;
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struct mv_crqb_iie *crqb;
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struct ata_taskfile *tf;
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u32 flags = 0;
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if (ATA_PROT_DMA != qc->tf.protocol)
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return;
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/* the req producer index should be the same as we remember it */
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assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
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EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
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pp->req_producer);
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/* Fill in Gen IIE command request block
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*/
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if (!(qc->tf.flags & ATA_TFLAG_WRITE))
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flags |= CRQB_FLAG_READ;
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assert(MV_MAX_Q_DEPTH > qc->tag);
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flags |= qc->tag << CRQB_TAG_SHIFT;
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crqb = (struct mv_crqb_iie *) &pp->crqb[pp->req_producer];
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crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
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crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
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crqb->flags = cpu_to_le32(flags);
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tf = &qc->tf;
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crqb->ata_cmd[0] = cpu_to_le32(
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(tf->command << 16) |
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(tf->feature << 24)
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);
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crqb->ata_cmd[1] = cpu_to_le32(
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(tf->lbal << 0) |
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(tf->lbam << 8) |
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(tf->lbah << 16) |
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(tf->device << 24)
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);
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crqb->ata_cmd[2] = cpu_to_le32(
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(tf->hob_lbal << 0) |
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(tf->hob_lbam << 8) |
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(tf->hob_lbah << 16) |
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(tf->hob_feature << 24)
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);
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crqb->ata_cmd[3] = cpu_to_le32(
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(tf->nsect << 0) |
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(tf->hob_nsect << 8)
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);
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if (!(qc->flags & ATA_QCFLAG_DMAMAP))
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return;
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}
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mv_fill_sg(qc);
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}
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@ -1674,6 +1835,12 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
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m2 |= hpriv->signal[port].pre;
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m2 &= ~(1 << 16);
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/* according to mvSata 3.6.1, some IIE values are fixed */
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if (IS_GEN_IIE(hpriv)) {
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m2 &= ~0xC30FF01F;
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m2 |= 0x0000900F;
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}
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writel(m2, port_mmio + PHY_MODE2);
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}
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@ -1978,6 +2145,27 @@ static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
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}
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break;
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case chip_7042:
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case chip_6042:
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hpriv->ops = &mv6xxx_ops;
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hp_flags |= MV_HP_GEN_IIE;
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switch (rev_id) {
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case 0x0:
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hp_flags |= MV_HP_ERRATA_XX42A0;
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break;
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case 0x1:
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hp_flags |= MV_HP_ERRATA_60X1C0;
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break;
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default:
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dev_printk(KERN_WARNING, &pdev->dev,
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"Applying 60X1C0 workarounds to unknown rev\n");
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hp_flags |= MV_HP_ERRATA_60X1C0;
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break;
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}
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break;
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default:
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printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
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return 1;
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