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drm/i915: Make a single set-to-cpu-domain path and use it wherever needed.
This fixes several domain management bugs, including potential lack of cache invalidation for pread, potential failure to wait for set_domain(CPU, 0), and more, along with producing more intelligible code. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Eric Anholt
Dave Airlie
parent
2ef7eeaa55
commit
e47c68e9c5
@ -379,8 +379,8 @@ struct drm_i915_gem_object {
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uint32_t agp_type;
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/**
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* Flagging of which individual pages are valid in GEM_DOMAIN_CPU when
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* GEM_DOMAIN_CPU is not in the object's read domain.
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* If present, while GEM_DOMAIN_CPU is in the read domain this array
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* flags which individual pages are valid.
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*/
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uint8_t *page_cpu_valid;
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};
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@ -37,19 +37,17 @@ static int
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i915_gem_object_set_domain(struct drm_gem_object *obj,
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uint32_t read_domains,
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uint32_t write_domain);
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static int
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i915_gem_object_set_domain_range(struct drm_gem_object *obj,
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uint64_t offset,
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uint64_t size,
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uint32_t read_domains,
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uint32_t write_domain);
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static int
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i915_gem_set_domain(struct drm_gem_object *obj,
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struct drm_file *file_priv,
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uint32_t read_domains,
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uint32_t write_domain);
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static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
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static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
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static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
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static int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
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int write);
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static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
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int write);
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static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
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uint64_t offset,
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uint64_t size);
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static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
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static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
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static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
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static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
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@ -164,8 +162,8 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
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mutex_lock(&dev->struct_mutex);
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ret = i915_gem_object_set_domain_range(obj, args->offset, args->size,
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I915_GEM_DOMAIN_CPU, 0);
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ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
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args->size);
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if (ret != 0) {
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drm_gem_object_unreference(obj);
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mutex_unlock(&dev->struct_mutex);
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@ -321,8 +319,7 @@ i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
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mutex_lock(&dev->struct_mutex);
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ret = i915_gem_set_domain(obj, file_priv,
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I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
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ret = i915_gem_object_set_to_cpu_domain(obj, 1);
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if (ret) {
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mutex_unlock(&dev->struct_mutex);
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return ret;
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@ -439,8 +436,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
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if (read_domains & I915_GEM_DOMAIN_GTT) {
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ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
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} else {
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ret = i915_gem_set_domain(obj, file_priv,
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read_domains, write_domain);
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ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
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}
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drm_gem_object_unreference(obj);
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@ -477,10 +473,9 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
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obj_priv = obj->driver_private;
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/* Pinned buffers may be scanout, so flush the cache */
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if ((obj->write_domain & I915_GEM_DOMAIN_CPU) && obj_priv->pin_count) {
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i915_gem_clflush_object(obj);
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drm_agp_chipset_flush(dev);
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}
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if (obj_priv->pin_count)
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i915_gem_object_flush_cpu_write_domain(obj);
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drm_gem_object_unreference(obj);
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mutex_unlock(&dev->struct_mutex);
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return ret;
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@ -925,23 +920,10 @@ i915_gem_object_wait_rendering(struct drm_gem_object *obj)
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struct drm_i915_gem_object *obj_priv = obj->driver_private;
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int ret;
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/* If there are writes queued to the buffer, flush and
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* create a new seqno to wait for.
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/* This function only exists to support waiting for existing rendering,
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* not for emitting required flushes.
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*/
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if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) {
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uint32_t seqno, write_domain = obj->write_domain;
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#if WATCH_BUF
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DRM_INFO("%s: flushing object %p from write domain %08x\n",
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__func__, obj, write_domain);
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#endif
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i915_gem_flush(dev, 0, write_domain);
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seqno = i915_add_request(dev, write_domain);
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i915_gem_object_move_to_active(obj, seqno);
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#if WATCH_LRU
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DRM_INFO("%s: flush moves to exec list %p\n", __func__, obj);
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#endif
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}
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BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
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/* If there is rendering queued on the buffer being evicted, wait for
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* it.
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@ -981,24 +963,16 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
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return -EINVAL;
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}
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/* Wait for any rendering to complete
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*/
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ret = i915_gem_object_wait_rendering(obj);
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if (ret) {
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DRM_ERROR("wait_rendering failed: %d\n", ret);
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return ret;
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}
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/* Move the object to the CPU domain to ensure that
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* any possible CPU writes while it's not in the GTT
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* are flushed when we go to remap it. This will
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* also ensure that all pending GPU writes are finished
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* before we unbind.
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*/
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ret = i915_gem_object_set_domain(obj, I915_GEM_DOMAIN_CPU,
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I915_GEM_DOMAIN_CPU);
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ret = i915_gem_object_set_to_cpu_domain(obj, 1);
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if (ret) {
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DRM_ERROR("set_domain failed: %d\n", ret);
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if (ret != -ERESTARTSYS)
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DRM_ERROR("set_domain failed: %d\n", ret);
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return ret;
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}
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@ -1259,6 +1233,51 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
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drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
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}
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/** Flushes any GPU write domain for the object if it's dirty. */
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static void
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i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
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{
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struct drm_device *dev = obj->dev;
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uint32_t seqno;
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if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
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return;
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/* Queue the GPU write cache flushing we need. */
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i915_gem_flush(dev, 0, obj->write_domain);
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seqno = i915_add_request(dev, obj->write_domain);
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obj->write_domain = 0;
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i915_gem_object_move_to_active(obj, seqno);
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}
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/** Flushes the GTT write domain for the object if it's dirty. */
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static void
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i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
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{
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if (obj->write_domain != I915_GEM_DOMAIN_GTT)
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return;
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/* No actual flushing is required for the GTT write domain. Writes
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* to it immediately go to main memory as far as we know, so there's
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* no chipset flush. It also doesn't land in render cache.
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*/
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obj->write_domain = 0;
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}
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/** Flushes the CPU write domain for the object if it's dirty. */
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static void
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i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
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{
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struct drm_device *dev = obj->dev;
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if (obj->write_domain != I915_GEM_DOMAIN_CPU)
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return;
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i915_gem_clflush_object(obj);
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drm_agp_chipset_flush(dev);
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obj->write_domain = 0;
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}
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/**
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* Moves a single object to the GTT read, and possibly write domain.
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*
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@ -1268,56 +1287,81 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
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static int
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i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
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{
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struct drm_device *dev = obj->dev;
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struct drm_i915_gem_object *obj_priv = obj->driver_private;
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uint32_t flush_domains;
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/* Figure out what GPU domains we need to flush or invalidate for
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* moving to GTT.
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*/
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flush_domains = obj->write_domain & I915_GEM_GPU_DOMAINS;
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/* Queue the GPU write cache flushing we need. */
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if (flush_domains != 0) {
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uint32_t seqno;
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obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
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i915_gem_flush(dev, 0, flush_domains);
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seqno = i915_add_request(dev, flush_domains);
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i915_gem_object_move_to_active(obj, seqno);
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}
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int ret;
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i915_gem_object_flush_gpu_write_domain(obj);
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/* Wait on any GPU rendering and flushing to occur. */
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if (obj_priv->active) {
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int ret;
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ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
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if (ret != 0)
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return ret;
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}
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ret = i915_gem_object_wait_rendering(obj);
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if (ret != 0)
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return ret;
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/* If we're writing through the GTT domain, then CPU and GPU caches
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* will need to be invalidated at next use.
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*/
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if (write)
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obj->read_domains &= ~(I915_GEM_GPU_DOMAINS |
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I915_GEM_DOMAIN_CPU);
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obj->read_domains &= I915_GEM_DOMAIN_GTT;
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/* Flush the CPU domain if it's dirty. */
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if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
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i915_gem_clflush_object(obj);
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drm_agp_chipset_flush(dev);
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obj->write_domain &= ~I915_GEM_DOMAIN_CPU;
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}
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i915_gem_object_flush_cpu_write_domain(obj);
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/* It should now be out of any other write domains, and we can update
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* the domain values for our changes.
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*/
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BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
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obj->read_domains |= I915_GEM_DOMAIN_GTT;
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if (write)
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if (write) {
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obj->write_domain = I915_GEM_DOMAIN_GTT;
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obj_priv->dirty = 1;
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}
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return 0;
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}
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/**
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* Moves a single object to the CPU read, and possibly write domain.
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*
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* This function returns when the move is complete, including waiting on
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* flushes to occur.
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*/
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static int
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i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
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{
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struct drm_device *dev = obj->dev;
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int ret;
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i915_gem_object_flush_gpu_write_domain(obj);
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/* Wait on any GPU rendering and flushing to occur. */
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ret = i915_gem_object_wait_rendering(obj);
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if (ret != 0)
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return ret;
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i915_gem_object_flush_gtt_write_domain(obj);
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/* If we have a partially-valid cache of the object in the CPU,
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* finish invalidating it and free the per-page flags.
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*/
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i915_gem_object_set_to_full_cpu_read_domain(obj);
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/* Flush the CPU cache if it's still invalid. */
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if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
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i915_gem_clflush_object(obj);
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drm_agp_chipset_flush(dev);
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obj->read_domains |= I915_GEM_DOMAIN_CPU;
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}
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/* It should now be out of any other write domains, and we can update
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* the domain values for our changes.
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*/
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BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
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/* If we're writing through the CPU, then the GPU read domains will
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* need to be invalidated at next use.
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*/
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if (write) {
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obj->read_domains &= I915_GEM_DOMAIN_CPU;
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obj->write_domain = I915_GEM_DOMAIN_CPU;
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}
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return 0;
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}
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@ -1442,7 +1486,9 @@ i915_gem_object_set_domain(struct drm_gem_object *obj,
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struct drm_i915_gem_object *obj_priv = obj->driver_private;
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uint32_t invalidate_domains = 0;
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uint32_t flush_domains = 0;
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int ret;
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BUG_ON(read_domains & I915_GEM_DOMAIN_CPU);
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BUG_ON(write_domain == I915_GEM_DOMAIN_CPU);
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#if WATCH_BUF
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DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
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@ -1479,34 +1525,11 @@ i915_gem_object_set_domain(struct drm_gem_object *obj,
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DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
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__func__, flush_domains, invalidate_domains);
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#endif
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/*
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* If we're invaliding the CPU cache and flushing a GPU cache,
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* then pause for rendering so that the GPU caches will be
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* flushed before the cpu cache is invalidated
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*/
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if ((invalidate_domains & I915_GEM_DOMAIN_CPU) &&
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(flush_domains & ~(I915_GEM_DOMAIN_CPU |
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I915_GEM_DOMAIN_GTT))) {
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ret = i915_gem_object_wait_rendering(obj);
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if (ret)
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return ret;
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}
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i915_gem_clflush_object(obj);
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}
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if ((write_domain | flush_domains) != 0)
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obj->write_domain = write_domain;
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/* If we're invalidating the CPU domain, clear the per-page CPU
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* domain list as well.
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*/
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if (obj_priv->page_cpu_valid != NULL &&
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(write_domain != 0 ||
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read_domains & I915_GEM_DOMAIN_CPU)) {
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drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
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DRM_MEM_DRIVER);
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obj_priv->page_cpu_valid = NULL;
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}
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obj->read_domains = read_domains;
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dev->invalidate_domains |= invalidate_domains;
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@ -1521,43 +1544,91 @@ i915_gem_object_set_domain(struct drm_gem_object *obj,
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}
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/**
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* Set the read/write domain on a range of the object.
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* Moves the object from a partially CPU read to a full one.
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*
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* Currently only implemented for CPU reads, otherwise drops to normal
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* i915_gem_object_set_domain().
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* Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
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* and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
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*/
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static void
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i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
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{
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struct drm_device *dev = obj->dev;
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struct drm_i915_gem_object *obj_priv = obj->driver_private;
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if (!obj_priv->page_cpu_valid)
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return;
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/* If we're partially in the CPU read domain, finish moving it in.
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*/
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if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
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int i;
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for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
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if (obj_priv->page_cpu_valid[i])
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continue;
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drm_clflush_pages(obj_priv->page_list + i, 1);
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}
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drm_agp_chipset_flush(dev);
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}
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/* Free the page_cpu_valid mappings which are now stale, whether
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* or not we've got I915_GEM_DOMAIN_CPU.
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*/
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drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
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DRM_MEM_DRIVER);
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obj_priv->page_cpu_valid = NULL;
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}
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/**
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* Set the CPU read domain on a range of the object.
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*
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* The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
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* not entirely valid. The page_cpu_valid member of the object flags which
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* pages have been flushed, and will be respected by
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* i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
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* of the whole object.
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*
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* This function returns when the move is complete, including waiting on
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* flushes to occur.
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*/
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static int
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i915_gem_object_set_domain_range(struct drm_gem_object *obj,
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uint64_t offset,
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uint64_t size,
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uint32_t read_domains,
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uint32_t write_domain)
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i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
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uint64_t offset, uint64_t size)
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{
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struct drm_i915_gem_object *obj_priv = obj->driver_private;
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int ret, i;
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int i, ret;
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|
||||
if (obj->read_domains & I915_GEM_DOMAIN_CPU)
|
||||
if (offset == 0 && size == obj->size)
|
||||
return i915_gem_object_set_to_cpu_domain(obj, 0);
|
||||
|
||||
i915_gem_object_flush_gpu_write_domain(obj);
|
||||
/* Wait on any GPU rendering and flushing to occur. */
|
||||
ret = i915_gem_object_wait_rendering(obj);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
i915_gem_object_flush_gtt_write_domain(obj);
|
||||
|
||||
/* If we're already fully in the CPU read domain, we're done. */
|
||||
if (obj_priv->page_cpu_valid == NULL &&
|
||||
(obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
|
||||
return 0;
|
||||
|
||||
if (read_domains != I915_GEM_DOMAIN_CPU ||
|
||||
write_domain != 0)
|
||||
return i915_gem_object_set_domain(obj,
|
||||
read_domains, write_domain);
|
||||
|
||||
/* Wait on any GPU rendering to the object to be flushed. */
|
||||
ret = i915_gem_object_wait_rendering(obj);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Otherwise, create/clear the per-page CPU read domain flag if we're
|
||||
* newly adding I915_GEM_DOMAIN_CPU
|
||||
*/
|
||||
if (obj_priv->page_cpu_valid == NULL) {
|
||||
obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
|
||||
DRM_MEM_DRIVER);
|
||||
}
|
||||
if (obj_priv->page_cpu_valid == NULL)
|
||||
return -ENOMEM;
|
||||
} else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
|
||||
memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
|
||||
|
||||
/* Flush the cache on any pages that are still invalid from the CPU's
|
||||
* perspective.
|
||||
*/
|
||||
for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; i++) {
|
||||
for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
|
||||
i++) {
|
||||
if (obj_priv->page_cpu_valid[i])
|
||||
continue;
|
||||
|
||||
@ -1566,6 +1637,13 @@ i915_gem_object_set_domain_range(struct drm_gem_object *obj,
|
||||
obj_priv->page_cpu_valid[i] = 1;
|
||||
}
|
||||
|
||||
/* It should now be out of any other write domains, and we can update
|
||||
* the domain values for our changes.
|
||||
*/
|
||||
BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
|
||||
|
||||
obj->read_domains |= I915_GEM_DOMAIN_CPU;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1679,6 +1757,18 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
|
||||
reloc.read_domains & I915_GEM_DOMAIN_CPU) {
|
||||
DRM_ERROR("reloc with read/write CPU domains: "
|
||||
"obj %p target %d offset %d "
|
||||
"read %08x write %08x",
|
||||
obj, reloc.target_handle,
|
||||
(int) reloc.offset,
|
||||
reloc.read_domains,
|
||||
reloc.write_domain);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (reloc.write_domain && target_obj->pending_write_domain &&
|
||||
reloc.write_domain != target_obj->pending_write_domain) {
|
||||
DRM_ERROR("Write domain conflict: "
|
||||
@ -2157,11 +2247,7 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data,
|
||||
/* XXX - flush the CPU caches for pinned objects
|
||||
* as the X server doesn't manage domains yet
|
||||
*/
|
||||
if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
|
||||
i915_gem_clflush_object(obj);
|
||||
drm_agp_chipset_flush(dev);
|
||||
obj->write_domain = 0;
|
||||
}
|
||||
i915_gem_object_flush_cpu_write_domain(obj);
|
||||
args->offset = obj_priv->gtt_offset;
|
||||
drm_gem_object_unreference(obj);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
@ -2263,29 +2349,6 @@ void i915_gem_free_object(struct drm_gem_object *obj)
|
||||
drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
|
||||
}
|
||||
|
||||
static int
|
||||
i915_gem_set_domain(struct drm_gem_object *obj,
|
||||
struct drm_file *file_priv,
|
||||
uint32_t read_domains,
|
||||
uint32_t write_domain)
|
||||
{
|
||||
struct drm_device *dev = obj->dev;
|
||||
int ret;
|
||||
uint32_t flush_domains;
|
||||
|
||||
BUG_ON(!mutex_is_locked(&dev->struct_mutex));
|
||||
|
||||
ret = i915_gem_object_set_domain(obj, read_domains, write_domain);
|
||||
if (ret)
|
||||
return ret;
|
||||
flush_domains = i915_gem_dev_set_domain(obj->dev);
|
||||
|
||||
if (flush_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))
|
||||
(void) i915_add_request(dev, flush_domains);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/** Unbinds all objects that are on the given buffer list. */
|
||||
static int
|
||||
i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user