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SoC updates for ti81xx for v5.1 merge window
Two changes to add legacy hwmod data for gpio and spi peripherals on ti81xx. We have not yet updated ti81xx to probe devices with ti-sysc interconnect target module driver, so these changes are still needed to make devices usable for the related device tree changes. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxTGfwRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXMTDxAAsGXhQz6TfSUZGcYVow/1v3l/1Mr3S/Yb gBMeHVQqoGFTU4eCGHEL3X2qNFE+0Kfq1Sbqbfq6sbyzqiExjbYFF58hMJVHVxRX WzO/GNEZFugdFf70K2sb/d5xZEq1YIlxna8Brg32zIp6YROLREtNPUO3Lehn21rj KKWAb00fnyt04XM1JI/Q/tOQeRsz+Ec3KytSkYzGt8jaaEgzU8tH05uVfQB7Qshv z5mr737CHnUXH/AaEFzboUlTzETPM03oHObBpylPYCvBgzGPKCHsBHdPfIYqiEyn pgoBGJT6ZqsxfhcLi9umoUxHMJAVhGh8pB01sewct8sbhWdT5fOuOwlFl9Rhvpue kkj8bqWMKHz9TFACiXtqj6qGQt9Fm61w2i8cAvlpjMPRLo+a+qDZeqcum9X5PnwA pKKoc0gMEZmg7LWSFiPuXdxeL3QG4NtB/KI0CiDg2xHU/+wTKiIGq29V9tBag70h 1UAyhDMkqsG/pIM01kOnKSkNIIRLgqjTMyuwEJnKdB7m7QF5aSw1UQethEIjXXzb 24vDHdTBlg9tb7pKn6/QL92PWtT6ceRsz9Ck7zR1UpijK+KlFfsPz1VYk+L9Op8G 7Lfux80AEuuz69PH3V23bsvysFIqgGXpzExEiVsVcJQz0GZ5DutyY5JNo/8uptNd bjoJMWKfPbo= =f3Ol -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.1/soc-ti-81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt SoC updates for ti81xx for v5.1 merge window Two changes to add legacy hwmod data for gpio and spi peripherals on ti81xx. We have not yet updated ti81xx to probe devices with ti-sysc interconnect target module driver, so these changes are still needed to make devices usable for the related device tree changes. * tag 'omap-for-v5.1/soc-ti-81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: ti81xx: Add hwmod boilerplate for all GPIO and SPI peripherals ARM: ti81xx: Move I2C entries in omap_hwmod_81xx to maintain grouping Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
e4354c1aaf
@ -432,6 +432,13 @@ static struct omap_hwmod dm81xx_i2c2_hwmod = {
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.class = &i2c_class,
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_i2c2_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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@ -443,13 +450,6 @@ static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_i2c2_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
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.name = "elm",
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.sysc = &dm81xx_elm_sysc,
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@ -539,6 +539,58 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
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{ .role = "dbclk", .clk = "sysclk18_ck" },
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};
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static struct omap_hwmod dm81xx_gpio3_hwmod = {
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.name = "gpio3",
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.clkdm_name = "alwon_l3s_clkdm",
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.class = &dm81xx_gpio_hwmod_class,
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.main_clk = "sysclk6_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = gpio3_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio3 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_gpio3_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
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{ .role = "dbclk", .clk = "sysclk18_ck" },
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};
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static struct omap_hwmod dm81xx_gpio4_hwmod = {
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.name = "gpio4",
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.clkdm_name = "alwon_l3s_clkdm",
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.class = &dm81xx_gpio_hwmod_class,
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.main_clk = "sysclk6_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = gpio4_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio4 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_gpio4_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x10,
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@ -1133,6 +1185,45 @@ static struct omap_hwmod dm81xx_mcspi1_hwmod = {
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.class = &dm816x_mcspi_class,
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};
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static struct omap_hwmod dm81xx_mcspi2_hwmod = {
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.name = "mcspi2",
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.clkdm_name = "alwon_l3s_clkdm",
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.main_clk = "sysclk10_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.class = &dm816x_mcspi_class,
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};
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static struct omap_hwmod dm81xx_mcspi3_hwmod = {
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.name = "mcspi3",
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.clkdm_name = "alwon_l3s_clkdm",
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.main_clk = "sysclk10_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.class = &dm816x_mcspi_class,
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};
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static struct omap_hwmod dm81xx_mcspi4_hwmod = {
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.name = "mcspi4",
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.clkdm_name = "alwon_l3s_clkdm",
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.main_clk = "sysclk10_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.class = &dm816x_mcspi_class,
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_mcspi1_hwmod,
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@ -1140,6 +1231,27 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi2 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_mcspi2_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi3 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_mcspi3_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi4 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_mcspi4_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
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.rev_offs = 0x000,
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.sysc_offs = 0x010,
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@ -1378,8 +1490,13 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
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&dm81xx_l4_ls__i2c2,
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&dm81xx_l4_ls__gpio1,
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&dm81xx_l4_ls__gpio2,
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&dm81xx_l4_ls__gpio3,
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&dm81xx_l4_ls__gpio4,
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&dm81xx_l4_ls__elm,
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&dm81xx_l4_ls__mcspi1,
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&dm81xx_l4_ls__mcspi2,
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&dm81xx_l4_ls__mcspi3,
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&dm81xx_l4_ls__mcspi4,
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&dm814x_l4_ls__mmc1,
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&dm814x_l4_ls__mmc2,
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&ti81xx_l4_ls__rtc,
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