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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 11:55:49 +07:00
xhci: Don't pass struct xhci_hcd pointer to xhci_link_seg()
It's only used to dig out if we need to set a chain flag for specific hosts. Pass the flag directly as a parameter instead. No functional changes. xhci_link_seg() is also used by DbC code, this change helps decoupling xhci and DbC. Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Link: https://lore.kernel.org/r/20200723144530.9992-4-mathias.nyman@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -96,8 +96,9 @@ static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
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* DMA address of the next segment. The caller needs to set any Link TRB
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* DMA address of the next segment. The caller needs to set any Link TRB
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* related flags, such as End TRB, Toggle Cycle, and no snoop.
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* related flags, such as End TRB, Toggle Cycle, and no snoop.
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*/
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*/
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static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
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static void xhci_link_segments(struct xhci_segment *prev,
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struct xhci_segment *next, enum xhci_ring_type type)
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struct xhci_segment *next,
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enum xhci_ring_type type, bool chain_links)
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{
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{
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u32 val;
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u32 val;
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@ -112,11 +113,7 @@ static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
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val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
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val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
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val &= ~TRB_TYPE_BITMASK;
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val &= ~TRB_TYPE_BITMASK;
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val |= TRB_TYPE(TRB_LINK);
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val |= TRB_TYPE(TRB_LINK);
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/* Always set the chain bit with 0.95 hardware */
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if (chain_links)
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/* Set chain bit for isoc rings on AMD 0.96 host */
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if (xhci_link_trb_quirk(xhci) ||
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(type == TYPE_ISOC &&
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(xhci->quirks & XHCI_AMD_0x96_HOST)))
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val |= TRB_CHAIN;
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val |= TRB_CHAIN;
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prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
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prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
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}
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}
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@ -131,13 +128,19 @@ static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
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unsigned int num_segs)
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unsigned int num_segs)
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{
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{
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struct xhci_segment *next;
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struct xhci_segment *next;
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bool chain_links;
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if (!ring || !first || !last)
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if (!ring || !first || !last)
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return;
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return;
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/* Set chain bit for 0.95 hosts, and for isoc rings on AMD 0.96 host */
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chain_links = !!(xhci_link_trb_quirk(xhci) ||
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(ring->type == TYPE_ISOC &&
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(xhci->quirks & XHCI_AMD_0x96_HOST)));
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next = ring->enq_seg->next;
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next = ring->enq_seg->next;
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xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
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xhci_link_segments(ring->enq_seg, first, ring->type, chain_links);
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xhci_link_segments(xhci, last, next, ring->type);
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xhci_link_segments(last, next, ring->type, chain_links);
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ring->num_segs += num_segs;
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ring->num_segs += num_segs;
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ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
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ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
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@ -321,6 +324,12 @@ static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
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enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
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enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
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{
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{
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struct xhci_segment *prev;
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struct xhci_segment *prev;
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bool chain_links;
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/* Set chain bit for 0.95 hosts, and for isoc rings on AMD 0.96 host */
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chain_links = !!(xhci_link_trb_quirk(xhci) ||
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(type == TYPE_ISOC &&
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(xhci->quirks & XHCI_AMD_0x96_HOST)));
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prev = xhci_segment_alloc(xhci, cycle_state, max_packet, flags);
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prev = xhci_segment_alloc(xhci, cycle_state, max_packet, flags);
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if (!prev)
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if (!prev)
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@ -341,12 +350,12 @@ static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
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}
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}
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return -ENOMEM;
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return -ENOMEM;
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}
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}
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xhci_link_segments(xhci, prev, next, type);
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xhci_link_segments(prev, next, type, chain_links);
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prev = next;
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prev = next;
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num_segs--;
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num_segs--;
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}
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}
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xhci_link_segments(xhci, prev, *first, type);
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xhci_link_segments(prev, *first, type, chain_links);
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*last = prev;
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*last = prev;
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return 0;
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return 0;
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