mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 14:21:55 +07:00
drm/i915/tv: Generate better pipe timings for TV encoder
To make vblank timestamps work better with the TV encoder let's
scale the pipe timings such that the relationship between the
TV active and TV blanking periods is mirrored in the
corresponding pipe timings.
Note that in reality the pipe runs at a faster speed during the
TV vblank, and correspondigly there are periods when the pipe
is enitrely stopped. We pretend that this isn't the case and
as such we incur some error in the vblank timestamps during
the TV vblank. Further explanation of the issues in a big
comment in the code.
This makes the vblank timestamps good enough to make
i965gm (which doesn't have a working frame counter with
the TV encoder) report correct frame numbers. Previously
you could get all kinds of nonsense which resulted in
eg. glxgears reporting that it's running at twice the
actual framerate in most cases.
v2: s/IS_GEN4(dev_priv)/IS_GEN(dev_priv, 4)/ in the comment
for consistency
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181112170000.27531-15-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
This commit is contained in:
Ville Syrjälä
parent
a0ff6779c7
commit
e3bb355c7d
@ -4895,6 +4895,7 @@ enum {
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# define TV_OVERSAMPLE_NONE (2 << 18)
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/* Selects 8x oversampling */
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# define TV_OVERSAMPLE_8X (3 << 18)
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# define TV_OVERSAMPLE_MASK (3 << 18)
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/* Selects progressive mode rather than interlaced */
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# define TV_PROGRESSIVE (1 << 17)
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/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
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@ -339,7 +339,6 @@ struct tv_mode {
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const struct video_levels *composite_levels, *svideo_levels;
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const struct color_conversion *composite_color, *svideo_color;
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const u32 *filter_table;
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u16 max_srcw;
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};
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@ -728,7 +727,6 @@ static const struct tv_mode tv_modes[] = {
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.burst_ena = false,
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.filter_table = filter_table,
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.max_srcw = 800
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},
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{
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.name = "1080i@50Hz",
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@ -946,13 +944,183 @@ intel_tv_mode_vdisplay(const struct tv_mode *tv_mode)
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return 2 * (tv_mode->nbr_end + 1);
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}
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static void
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intel_tv_mode_to_mode(struct drm_display_mode *mode,
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const struct tv_mode *tv_mode)
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{
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mode->clock = tv_mode->clock /
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(tv_mode->oversample >> !tv_mode->progressive);
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/*
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* tv_mode horizontal timings:
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*
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* hsync_end
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* | hblank_end
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* | | hblank_start
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* | | | htotal
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* | _______ |
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* ____/ \___
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* \__/ \
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*/
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mode->hdisplay =
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tv_mode->hblank_start - tv_mode->hblank_end;
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mode->hsync_start = mode->hdisplay +
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tv_mode->htotal - tv_mode->hblank_start;
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mode->hsync_end = mode->hsync_start +
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tv_mode->hsync_end;
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mode->htotal = tv_mode->htotal + 1;
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/*
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* tv_mode vertical timings:
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*
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* vsync_start
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* | vsync_end
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* | | vi_end nbr_end
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* | | | |
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* | | _______
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* \__ ____/ \
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* \__/
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*/
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mode->vdisplay = intel_tv_mode_vdisplay(tv_mode);
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if (tv_mode->progressive) {
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mode->vsync_start = mode->vdisplay +
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tv_mode->vsync_start_f1 + 1;
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mode->vsync_end = mode->vsync_start +
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tv_mode->vsync_len;
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mode->vtotal = mode->vdisplay +
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tv_mode->vi_end_f1 + 1;
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} else {
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mode->vsync_start = mode->vdisplay +
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tv_mode->vsync_start_f1 + 1 +
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tv_mode->vsync_start_f2 + 1;
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mode->vsync_end = mode->vsync_start +
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2 * tv_mode->vsync_len;
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mode->vtotal = mode->vdisplay +
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tv_mode->vi_end_f1 + 1 +
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tv_mode->vi_end_f2 + 1;
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}
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/* TV has it's own notion of sync and other mode flags, so clear them. */
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mode->flags = 0;
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mode->vrefresh = 0;
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mode->vrefresh = drm_mode_vrefresh(mode);
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snprintf(mode->name, sizeof(mode->name),
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"%dx%d%c (%s)",
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mode->hdisplay, mode->vdisplay,
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tv_mode->progressive ? 'p' : 'i',
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tv_mode->name);
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}
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static void intel_tv_scale_mode_horiz(struct drm_display_mode *mode,
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int hdisplay, int left_margin,
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int right_margin)
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{
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int hsync_start = mode->hsync_start - mode->hdisplay + right_margin;
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int hsync_end = mode->hsync_end - mode->hdisplay + right_margin;
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int new_htotal = mode->htotal * hdisplay /
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(mode->hdisplay - left_margin - right_margin);
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mode->clock = mode->clock * new_htotal / mode->htotal;
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mode->hdisplay = hdisplay;
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mode->hsync_start = hdisplay + hsync_start * new_htotal / mode->htotal;
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mode->hsync_end = hdisplay + hsync_end * new_htotal / mode->htotal;
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mode->htotal = new_htotal;
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}
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static void intel_tv_scale_mode_vert(struct drm_display_mode *mode,
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int vdisplay, int top_margin,
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int bottom_margin)
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{
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int vsync_start = mode->vsync_start - mode->vdisplay + bottom_margin;
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int vsync_end = mode->vsync_end - mode->vdisplay + bottom_margin;
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int new_vtotal = mode->vtotal * vdisplay /
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(mode->vdisplay - top_margin - bottom_margin);
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mode->clock = mode->clock * new_vtotal / mode->vtotal;
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mode->vdisplay = vdisplay;
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mode->vsync_start = vdisplay + vsync_start * new_vtotal / mode->vtotal;
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mode->vsync_end = vdisplay + vsync_end * new_vtotal / mode->vtotal;
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mode->vtotal = new_vtotal;
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}
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static void
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intel_tv_get_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct drm_display_mode *adjusted_mode =
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&pipe_config->base.adjusted_mode;
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struct drm_display_mode mode = {};
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u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
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struct tv_mode tv_mode = {};
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int hdisplay = adjusted_mode->crtc_hdisplay;
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int vdisplay = adjusted_mode->crtc_vdisplay;
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int xsize, ysize, xpos, ypos;
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pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
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pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
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tv_ctl = I915_READ(TV_CTL);
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hctl1 = I915_READ(TV_H_CTL_1);
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hctl3 = I915_READ(TV_H_CTL_3);
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vctl1 = I915_READ(TV_V_CTL_1);
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vctl2 = I915_READ(TV_V_CTL_2);
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tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT;
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tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT;
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tv_mode.hblank_start = (hctl3 & TV_HBLANK_START_MASK) >> TV_HBLANK_START_SHIFT;
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tv_mode.hblank_end = (hctl3 & TV_HSYNC_END_MASK) >> TV_HBLANK_END_SHIFT;
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tv_mode.nbr_end = (vctl1 & TV_NBR_END_MASK) >> TV_NBR_END_SHIFT;
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tv_mode.vi_end_f1 = (vctl1 & TV_VI_END_F1_MASK) >> TV_VI_END_F1_SHIFT;
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tv_mode.vi_end_f2 = (vctl1 & TV_VI_END_F2_MASK) >> TV_VI_END_F2_SHIFT;
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tv_mode.vsync_len = (vctl2 & TV_VSYNC_LEN_MASK) >> TV_VSYNC_LEN_SHIFT;
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tv_mode.vsync_start_f1 = (vctl2 & TV_VSYNC_START_F1_MASK) >> TV_VSYNC_START_F1_SHIFT;
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tv_mode.vsync_start_f2 = (vctl2 & TV_VSYNC_START_F2_MASK) >> TV_VSYNC_START_F2_SHIFT;
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tv_mode.clock = pipe_config->port_clock;
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tv_mode.progressive = tv_ctl & TV_PROGRESSIVE;
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switch (tv_ctl & TV_OVERSAMPLE_MASK) {
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case TV_OVERSAMPLE_8X:
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tv_mode.oversample = 8;
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break;
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case TV_OVERSAMPLE_4X:
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tv_mode.oversample = 4;
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break;
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case TV_OVERSAMPLE_2X:
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tv_mode.oversample = 2;
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break;
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default:
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tv_mode.oversample = 1;
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break;
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}
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tmp = I915_READ(TV_WIN_POS);
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xpos = tmp >> 16;
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ypos = tmp & 0xffff;
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tmp = I915_READ(TV_WIN_SIZE);
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xsize = tmp >> 16;
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ysize = tmp & 0xffff;
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intel_tv_mode_to_mode(&mode, &tv_mode);
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DRM_DEBUG_KMS("TV mode:\n");
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drm_mode_debug_printmodeline(&mode);
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intel_tv_scale_mode_horiz(&mode, hdisplay,
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xpos, mode.hdisplay - xsize - xpos);
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intel_tv_scale_mode_vert(&mode, vdisplay,
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ypos, mode.vdisplay - ysize - ypos);
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adjusted_mode->crtc_clock = mode.clock;
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}
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static int
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@ -963,6 +1131,8 @@ intel_tv_compute_config(struct intel_encoder *encoder,
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const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
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struct drm_display_mode *adjusted_mode =
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&pipe_config->base.adjusted_mode;
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int hdisplay = adjusted_mode->crtc_hdisplay;
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int vdisplay = adjusted_mode->crtc_vdisplay;
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if (!tv_mode)
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return -EINVAL;
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@ -971,17 +1141,90 @@ intel_tv_compute_config(struct intel_encoder *encoder,
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return -EINVAL;
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pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
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adjusted_mode->crtc_clock = tv_mode->clock;
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DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
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pipe_config->pipe_bpp = 8*3;
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/* TV has it's own notion of sync and other mode flags, so clear them. */
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adjusted_mode->flags = 0;
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pipe_config->port_clock = tv_mode->clock;
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intel_tv_mode_to_mode(adjusted_mode, tv_mode);
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DRM_DEBUG_KMS("TV mode:\n");
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drm_mode_debug_printmodeline(adjusted_mode);
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/*
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* FIXME: We don't check whether the input mode is actually what we want
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* or whether userspace is doing something stupid.
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* The pipe scanline counter behaviour looks as follows when
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* using the TV encoder:
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*
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* time ->
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*
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* dsl=vtotal-1 | |
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* || ||
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* ___| | ___| |
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* / | / |
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* / | / |
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* dsl=0 ___/ |_____/ |
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* | | | | | |
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* ^ ^ ^ ^ ^
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* | | | | pipe vblank/first part of tv vblank
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* | | | bottom margin
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* | | active
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* | top margin
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* remainder of tv vblank
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*
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* When the TV encoder is used the pipe wants to run faster
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* than expected rate. During the active portion the TV
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* encoder stalls the pipe every few lines to keep it in
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* check. When the TV encoder reaches the bottom margin the
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* pipe simply stops. Once we reach the TV vblank the pipe is
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* no longer stalled and it runs at the max rate (apparently
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* oversample clock on gen3, cdclk on gen4). Once the pipe
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* reaches the pipe vtotal the pipe stops for the remainder
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* of the TV vblank/top margin. The pipe starts up again when
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* the TV encoder exits the top margin.
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*
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* To avoid huge hassles for vblank timestamping we scale
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* the pipe timings as if the pipe always runs at the average
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* rate it maintains during the active period. This also
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* gives us a reasonable guesstimate as to the pixel rate.
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* Due to the variation in the actual pipe speed the scanline
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* counter will give us slightly erroneous results during the
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* TV vblank/margins. But since vtotal was selected such that
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* it matches the average rate of the pipe during the active
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* portion the error shouldn't cause any serious grief to
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* vblank timestamps.
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*
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* For posterity here is the empirically derived formula
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* that gives us the maximum length of the pipe vblank
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* we can use without causing display corruption. Following
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* this would allow us to have a ticking scanline counter
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* everywhere except during the bottom margin (there the
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* pipe always stops). Ie. this would eliminate the second
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* flat portion of the above graph. However this would also
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* complicate vblank timestamping as the pipe vtotal would
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* no longer match the average rate the pipe runs at during
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* the active portion. Hence following this formula seems
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* more trouble that it's worth.
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*
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* if (IS_GEN(dev_priv, 4)) {
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* num = cdclk * (tv_mode->oversample >> !tv_mode->progressive);
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* den = tv_mode->clock;
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* } else {
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* num = tv_mode->oversample >> !tv_mode->progressive;
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* den = 1;
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* }
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* max_pipe_vblank_len ~=
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* (num * tv_htotal * (tv_vblank_len + top_margin)) /
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* (den * pipe_htotal);
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*/
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intel_tv_scale_mode_horiz(adjusted_mode, hdisplay,
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conn_state->tv.margins.left,
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conn_state->tv.margins.right);
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intel_tv_scale_mode_vert(adjusted_mode, vdisplay,
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conn_state->tv.margins.top,
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conn_state->tv.margins.bottom);
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drm_mode_set_crtcinfo(adjusted_mode, 0);
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adjusted_mode->name[0] = '\0';
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return 0;
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}
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@ -1410,52 +1653,41 @@ intel_tv_set_mode_type(struct drm_display_mode *mode,
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static int
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intel_tv_get_modes(struct drm_connector *connector)
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{
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struct drm_display_mode *mode_ptr;
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const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
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int j, count = 0;
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u64 tmp;
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int i, count = 0;
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for (j = 0; j < ARRAY_SIZE(input_res_table);
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j++) {
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const struct input_res *input = &input_res_table[j];
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unsigned int hactive_s = input->w;
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unsigned int vactive_s = input->h;
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for (i = 0; i < ARRAY_SIZE(input_res_table); i++) {
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const struct input_res *input = &input_res_table[i];
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struct drm_display_mode *mode;
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if (tv_mode->max_srcw && input->w > tv_mode->max_srcw)
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if (input->w > 1024 &&
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!tv_mode->progressive &&
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!tv_mode->component_only)
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continue;
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if (input->w > 1024 && (!tv_mode->progressive
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&& !tv_mode->component_only))
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mode = drm_mode_create(connector->dev);
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if (!mode)
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continue;
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mode_ptr = drm_mode_create(connector->dev);
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if (!mode_ptr)
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continue;
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/*
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* We take the TV mode and scale it to look
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* like it had the expected h/vdisplay. This
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* provides the most information to userspace
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* about the actual timings of the mode. We
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* do ignore the margins though.
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*/
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intel_tv_mode_to_mode(mode, tv_mode);
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if (count == 0) {
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DRM_DEBUG_KMS("TV mode:\n");
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drm_mode_debug_printmodeline(mode);
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}
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intel_tv_scale_mode_horiz(mode, input->w, 0, 0);
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intel_tv_scale_mode_vert(mode, input->h, 0, 0);
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intel_tv_set_mode_type(mode, tv_mode);
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mode_ptr->hdisplay = hactive_s;
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mode_ptr->hsync_start = hactive_s + 1;
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mode_ptr->hsync_end = hactive_s + 64;
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if (mode_ptr->hsync_end <= mode_ptr->hsync_start)
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mode_ptr->hsync_end = mode_ptr->hsync_start + 1;
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mode_ptr->htotal = hactive_s + 96;
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drm_mode_set_name(mode);
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mode_ptr->vdisplay = vactive_s;
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mode_ptr->vsync_start = vactive_s + 1;
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mode_ptr->vsync_end = vactive_s + 32;
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if (mode_ptr->vsync_end <= mode_ptr->vsync_start)
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mode_ptr->vsync_end = mode_ptr->vsync_start + 1;
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mode_ptr->vtotal = vactive_s + 33;
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tmp = mul_u32_u32(tv_mode->refresh, mode_ptr->vtotal);
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tmp *= mode_ptr->htotal;
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tmp = div_u64(tmp, 1000000);
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mode_ptr->clock = (int) tmp;
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intel_tv_set_mode_type(mode_ptr, tv_mode);
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drm_mode_set_name(mode_ptr);
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drm_mode_probed_add(connector, mode_ptr);
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drm_mode_probed_add(connector, mode);
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count++;
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}
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