AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-24 21:36:57 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

drm/i915: Use 200MHz cdclk on vlv when all pipes are off

Browse Source 
Drop the cdclk frequency to 200MHz on vlv when all pipes are off. In
theory we should be able to use 200MHz also when the pixel clock is at
most 90% of 200MHz. However in practice all we seem to get is a solid
color picture or an otherwise corrupted display.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2014-06-13 13:37:51 +03:00 committed by Daniel Vetter
parent 29dc7ef3bb
commit e37c67a1c5
1 changed files with 7 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/drm/i915/intel_display.c
View File

@ -4556,14 +4556,19 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
* 400MHz
* So we check to see whether we're above 90% of the lower bin and
* adjust if needed.
*
* We seem to get an unstable or solid color picture at 200MHz.
* Not sure what's wrong. For now use 200MHz only when all pipes
* are off.
*/
if (max_pixclk > freq_320*9/10)
return 400000;
else if (max_pixclk > 266667*9/10)
return freq_320;
else
else if (max_pixclk > 0)
return 266667;
/* Looks like the 200MHz CDclk freq doesn't work on some configs */
else
return 200000;
}
/* compute the max pixel clock for new configuration */