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dmaengine: dw: select DW_DMAC_BIG_ENDIAN_IO automagically

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Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Vinod Koul 2013-06-12 13:39:57 +05:30
parent fed42c198b
commit e368b510c0
2 changed files with 8 additions and 9 deletions
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11
drivers/dma/dw/Kconfig
View File

@ -10,6 +10,7 @@ config DW_DMAC_CORE
config DW_DMAC config DW_DMAC
tristate "Synopsys DesignWare AHB DMA platform driver" tristate "Synopsys DesignWare AHB DMA platform driver"
select DW_DMAC_CORE select DW_DMAC_CORE
select DW_DMAC_BIG_ENDIAN_IO if AVR32
default y if CPU_AT32AP7000 default y if CPU_AT32AP7000
help help
Support the Synopsys DesignWare AHB DMA controller. This Support the Synopsys DesignWare AHB DMA controller. This
@ -25,12 +26,4 @@ config DW_DMAC_PCI
Intel Medfield has integrated this GPDMA controller. Intel Medfield has integrated this GPDMA controller.
config DW_DMAC_BIG_ENDIAN_IO config DW_DMAC_BIG_ENDIAN_IO
bool "Use big endian I/O register access" bool
default y if AVR32
depends on DW_DMAC_CORE
help
Say yes here to use big endian I/O access when reading and writing
to the DMA controller registers. This is needed on some platforms,
like the Atmel AVR32 architecture.
If unsure, use the default setting.

6
drivers/dma/dw/regs.h
View File

@ -101,6 +101,12 @@ struct dw_dma_regs {
u32 DW_PARAMS; u32 DW_PARAMS;
}; };
/*
* Big endian I/O access when reading and writing to the DMA controller
* registers. This is needed on some platforms, like the Atmel AVR32
* architecture.
*/
#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
#define dma_readl_native ioread32be #define dma_readl_native ioread32be
#define dma_writel_native iowrite32be #define dma_writel_native iowrite32be