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drm/i915/gen8: Tidy display interrupt processing
One bugfix and a few tidy-ups: * Pipe fault logging was broken on Gen9+. * Removed some unnecessary local variables. * Removed unnecessary initializers. * Decreased pipe iir block indentation level. * Grouped variable initialization close to use sites. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@cris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1452614647-13973-1-git-send-email-tvrtko.ursulin@linux.intel.com
This commit is contained in:
Tvrtko Ursulin
parent
1892faa9ec
commit
e32192e1ae
@ -2268,11 +2268,9 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 master_ctl;
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u32 master_ctl, iir;
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irqreturn_t ret = IRQ_NONE;
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uint32_t tmp = 0;
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enum pipe pipe;
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u32 aux_mask = GEN8_AUX_CHANNEL_A;
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if (!intel_irqs_enabled(dev_priv))
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return IRQ_NONE;
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@ -2280,10 +2278,6 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
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/* IRQs are synced during runtime_suspend, we don't require a wakeref */
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disable_rpm_wakeref_asserts(dev_priv);
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if (INTEL_INFO(dev_priv)->gen >= 9)
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aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
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GEN9_AUX_CHANNEL_D;
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master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
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master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
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if (!master_ctl)
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@ -2296,11 +2290,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
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ret = gen8_gt_irq_handler(dev_priv, master_ctl);
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if (master_ctl & GEN8_DE_MISC_IRQ) {
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tmp = I915_READ(GEN8_DE_MISC_IIR);
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if (tmp) {
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I915_WRITE(GEN8_DE_MISC_IIR, tmp);
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iir = I915_READ(GEN8_DE_MISC_IIR);
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if (iir) {
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I915_WRITE(GEN8_DE_MISC_IIR, iir);
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ret = IRQ_HANDLED;
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if (tmp & GEN8_DE_MISC_GSE)
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if (iir & GEN8_DE_MISC_GSE)
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intel_opregion_asle_intr(dev);
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else
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DRM_ERROR("Unexpected DE Misc interrupt\n");
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@ -2310,33 +2304,40 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
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}
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if (master_ctl & GEN8_DE_PORT_IRQ) {
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tmp = I915_READ(GEN8_DE_PORT_IIR);
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if (tmp) {
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iir = I915_READ(GEN8_DE_PORT_IIR);
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if (iir) {
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u32 tmp_mask;
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bool found = false;
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u32 hotplug_trigger = 0;
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if (IS_BROXTON(dev_priv))
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hotplug_trigger = tmp & BXT_DE_PORT_HOTPLUG_MASK;
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else if (IS_BROADWELL(dev_priv))
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hotplug_trigger = tmp & GEN8_PORT_DP_A_HOTPLUG;
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I915_WRITE(GEN8_DE_PORT_IIR, tmp);
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I915_WRITE(GEN8_DE_PORT_IIR, iir);
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ret = IRQ_HANDLED;
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if (tmp & aux_mask) {
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tmp_mask = GEN8_AUX_CHANNEL_A;
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if (INTEL_INFO(dev_priv)->gen >= 9)
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tmp_mask |= GEN9_AUX_CHANNEL_B |
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GEN9_AUX_CHANNEL_C |
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GEN9_AUX_CHANNEL_D;
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if (iir & tmp_mask) {
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dp_aux_irq_handler(dev);
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found = true;
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}
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if (hotplug_trigger) {
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if (IS_BROXTON(dev))
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bxt_hpd_irq_handler(dev, hotplug_trigger, hpd_bxt);
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else
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ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_bdw);
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found = true;
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if (IS_BROXTON(dev_priv)) {
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tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
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if (tmp_mask) {
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bxt_hpd_irq_handler(dev, tmp_mask, hpd_bxt);
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found = true;
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}
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} else if (IS_BROADWELL(dev_priv)) {
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tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
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if (tmp_mask) {
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ilk_hpd_irq_handler(dev, tmp_mask, hpd_bdw);
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found = true;
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}
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}
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if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
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if (IS_BROXTON(dev) && (iir & BXT_DE_PORT_GMBUS)) {
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gmbus_irq_handler(dev);
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found = true;
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}
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@ -2349,49 +2350,51 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
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}
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for_each_pipe(dev_priv, pipe) {
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uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
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u32 flip_done, fault_errors;
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if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
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continue;
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pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
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if (pipe_iir) {
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ret = IRQ_HANDLED;
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I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
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if (pipe_iir & GEN8_PIPE_VBLANK &&
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intel_pipe_handle_vblank(dev, pipe))
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intel_check_page_flip(dev, pipe);
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if (INTEL_INFO(dev_priv)->gen >= 9)
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flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
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else
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flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
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if (flip_done) {
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intel_prepare_page_flip(dev, pipe);
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intel_finish_page_flip_plane(dev, pipe);
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}
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if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
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hsw_pipe_crc_irq_handler(dev, pipe);
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if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
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intel_cpu_fifo_underrun_irq_handler(dev_priv,
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pipe);
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if (INTEL_INFO(dev_priv)->gen >= 9)
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fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
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else
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fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
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if (fault_errors)
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DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
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pipe_name(pipe),
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pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
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} else
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iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
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if (!iir) {
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DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
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continue;
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}
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ret = IRQ_HANDLED;
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I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
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if (iir & GEN8_PIPE_VBLANK &&
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intel_pipe_handle_vblank(dev, pipe))
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intel_check_page_flip(dev, pipe);
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flip_done = iir;
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if (INTEL_INFO(dev_priv)->gen >= 9)
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flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
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else
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flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
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if (flip_done) {
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intel_prepare_page_flip(dev, pipe);
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intel_finish_page_flip_plane(dev, pipe);
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}
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if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
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hsw_pipe_crc_irq_handler(dev, pipe);
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if (iir & GEN8_PIPE_FIFO_UNDERRUN)
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intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
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fault_errors = iir;
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if (INTEL_INFO(dev_priv)->gen >= 9)
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fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
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else
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fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
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if (fault_errors)
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DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
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pipe_name(pipe),
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fault_errors);
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}
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if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
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@ -2401,15 +2404,15 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
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* scheme also closed the SDE interrupt handling race we've seen
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* on older pch-split platforms. But this needs testing.
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*/
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u32 pch_iir = I915_READ(SDEIIR);
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if (pch_iir) {
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I915_WRITE(SDEIIR, pch_iir);
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iir = I915_READ(SDEIIR);
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if (iir) {
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I915_WRITE(SDEIIR, iir);
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ret = IRQ_HANDLED;
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if (HAS_PCH_SPT(dev_priv))
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spt_irq_handler(dev, pch_iir);
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spt_irq_handler(dev, iir);
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else
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cpt_irq_handler(dev, pch_iir);
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cpt_irq_handler(dev, iir);
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} else {
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/*
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* Like on previous PCH there seems to be something
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