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mvebu dt64 for 5.5 (part 1)

Browse Source 
- Add new Marvell CN9130 SoC support (CN9130 is made of one AP807 and
    one internal CP115, similar to the Armada 7K/8K using AP806 and
    CP110).
  - Reorganize EspressoBin device tree to add new variant of the boards
    (Armada 3270 based)
  - Add firmware node for turris Mox (Armada 3720 based)
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Merge tag 'mvebu-dt64-5.5-1' of git://git.infradead.org/linux-mvebu into arm/dt

mvebu dt64 for 5.5 (part 1)

 - Add new Marvell CN9130 SoC support (CN9130 is made of one AP807 and
   one internal CP115, similar to the Armada 7K/8K using AP806 and
   CP110).
 - Reorganize EspressoBin device tree to add new variant of the boards
   (Armada 3270 based)
 - Add firmware node for turris Mox (Armada 3720 based)

* tag 'mvebu-dt64-5.5-1' of git://git.infradead.org/linux-mvebu: (23 commits)
  arm64: dts: armada-3720-turris-mox: add firmware node
  arm64: dts: marvell: add ESPRESSObin variants
  arm64: dts: marvell: Add support for Marvell CN9132-DB
  arm64: dts: marvell: Add support for Marvell CN9131-DB
  arm64: dts: marvell: Add support for Marvell CN9130-DB
  arm64: dts: marvell: Add support for Marvell CN9130 SoC support
  arm64: dts: marvell: Add support for CP115
  arm64: dts: marvell: Externalize PCIe macros from CP11x file
  arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file
  arm64: dts: marvell: Prepare the introduction of CP115
  arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment
  arm64: dts: marvell: Add AP807-quad cache description
  arm64: dts: marvell: Add AP806-quad cache description
  arm64: dts: marvell: Add AP806-dual cache description
  arm64: dts: marvell: Add support for AP807/AP807-quad
  dt-bindings: marvell: Declare the CN913x SoC compatibles
  dt-bindings: marvell: Convert the SoC compatibles description to YAML
  arm64: dts: marvell: Move clocks to AP806 specific file
  arm64: dts: marvell: Prepare the introduction of AP807 based SoCs
  MAINTAINERS: Add new Marvell CN9130-based files to track
  ...

Link: https://lore.kernel.org/r/87zhhc3bo6.fsf@FE-laptop
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-11-03 17:32:25 -08:00
commit e315c7b3da
28 changed files with 2535 additions and 1276 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt → Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
View File

@ -1,15 +1,15 @@
Marvell Armada AP806 System Controller
Marvell Armada AP80x System Controller
======================================
The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
SoCs. It contains system controllers, which provide several registers
giving access to numerous features: clocks, pin-muxing and many other
SoC configuration items. This DT binding allows to describe these
system controllers.
The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
7K/8K/931x SoCs. It contains system controllers, which provide several
registers giving access to numerous features: clocks, pin-muxing and
many other SoC configuration items. This DT binding allows to describe
these system controllers.
For the top level node:
- compatible: must be: "syscon", "simple-mfd";
- reg: register area of the AP806 system controller
- reg: register area of the AP80x system controller
SYSTEM CONTROLLER 0
===================

24
Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt
View File

@ -1,24 +0,0 @@
Marvell Armada 7K/8K Platforms Device Tree Bindings
---------------------------------------------------
Boards using a SoC of the Marvell Armada 7K or 8K families must carry
the following root node property:
- compatible, with one of the following values:
- "marvell,armada7020", "marvell,armada-ap806-dual", "marvell,armada-ap806"
when the SoC being used is the Armada 7020
- "marvell,armada7040", "marvell,armada-ap806-quad", "marvell,armada-ap806"
when the SoC being used is the Armada 7040
- "marvell,armada8020", "marvell,armada-ap806-dual", "marvell,armada-ap806"
when the SoC being used is the Armada 8020
- "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"
when the SoC being used is the Armada 8040
Example:
compatible = "marvell,armada7040-db", "marvell,armada7040",
"marvell,armada-ap806-quad", "marvell,armada-ap806";

61
Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml Normal file
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@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0+ OR X11)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/marvell/armada-7k-8k.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 7K/8K Platforms Device Tree Bindings
maintainers:
- Gregory CLEMENT <gregory.clement@bootlin.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Armada 7020 SoC
items:
- const: marvell,armada7020
- const: marvell,armada-ap806-dual
- const: marvell,armada-ap806
- description: Armada 7040 SoC
items:
- const: marvell,armada7040
- const: marvell,armada-ap806-quad
- const: marvell,armada-ap806
- description: Armada 8020 SoC
items:
- const: marvell,armada8020
- const: marvell,armada-ap806-dual
- const: marvell,armada-ap806
- description: Armada 8040 SoC
items:
- const: marvell,armada8040
- const: marvell,armada-ap806-quad
- const: marvell,armada-ap806
- description: Armada CN9130 SoC with no external CP
items:
- const: marvell,cn9130
- const: marvell,armada-ap807-quad
- const: marvell,armada-ap807
- description: Armada CN9131 SoC with one external CP
items:
- const: marvell,cn9131
- const: marvell,cn9130
- const: marvell,armada-ap807-quad
- const: marvell,armada-ap807
- description: Armada CN9132 SoC with two external CPs
items:
- const: marvell,cn9132
- const: marvell,cn9131
- const: marvell,cn9130
- const: marvell,armada-ap807-quad
- const: marvell,armada-ap807

3
MAINTAINERS
View File

@ -1897,7 +1897,7 @@ F: arch/arm/boot/dts/dove*
F: arch/arm/boot/dts/orion5x*
T: git git://git.infradead.org/linux-mvebu.git
ARM/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K SOC support
ARM/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SOC support
M: Jason Cooper <jason@lakedaemon.net>
M: Andrew Lunn <andrew@lunn.ch>
M: Gregory Clement <gregory.clement@bootlin.com>
@ -1909,6 +1909,7 @@ F: arch/arm/boot/dts/kirkwood*
F: arch/arm/configs/mvebu_*_defconfig
F: arch/arm/mach-mvebu/
F: arch/arm64/boot/dts/marvell/armada*
F: arch/arm64/boot/dts/marvell/cn913*
F: drivers/cpufreq/armada-37xx-cpufreq.c
F: drivers/cpufreq/armada-8k-cpufreq.c
F: drivers/cpufreq/mvebu-cpufreq.c

3
arch/arm64/boot/dts/marvell/Makefile
View File

@ -10,3 +10,6 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb

42
arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts Normal file
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@ -0,0 +1,42 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC
* Copyright (C) 2018 Marvell
*
* Romain Perier <romain.perier@free-electrons.com>
* Konstantin Porotchkin <kostap@marvell.com>
*
*/
/*
* Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
*/
#include "armada-3720-espressobin.dtsi"
/ {
model = "Globalscale Marvell ESPRESSOBin Board (eMMC)";
compatible = "globalscale,espressobin-emmc", "globalscale,espressobin",
"marvell,armada3720", "marvell,armada3710";
};
/* U11 */
&sdhci0 {
non-removable;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,xenon-emmc;
marvell,xenon-tun-count = <9>;
marvell,pad-type = "fixed-1-8v";
pinctrl-names = "default";
pinctrl-0 = <&mmc_pins>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
mmccard: mmccard@0 {
compatible = "mmc-card";
reg = <0>;
};
};

59
arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts Normal file
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@ -0,0 +1,59 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 with eMMC
* Copyright (C) 2018 Marvell
*
* Romain Perier <romain.perier@free-electrons.com>
* Konstantin Porotchkin <kostap@marvell.com>
*
*/
/*
* Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200
*/
#include "armada-3720-espressobin.dtsi"
/ {
model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)";
compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7",
"globalscale,espressobin", "marvell,armada3720",
"marvell,armada3710";
};
&switch0 {
ports {
port@1 {
reg = <1>;
label = "lan1";
phy-handle = <&switch0phy0>;
};
port@3 {
reg = <3>;
label = "wan";
phy-handle = <&switch0phy2>;
};
};
};
/* U11 */
&sdhci0 {
non-removable;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,xenon-emmc;
marvell,xenon-tun-count = <9>;
marvell,pad-type = "fixed-1-8v";
pinctrl-names = "default";
pinctrl-0 = <&mmc_pins>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
mmccard: mmccard@0 {
compatible = "mmc-card";
reg = <0>;
};
};

36
arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts Normal file
View File

@ -0,0 +1,36 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Globalscale Marvell ESPRESSOBin Board V7
* Copyright (C) 2018 Marvell
*
* Romain Perier <romain.perier@free-electrons.com>
* Konstantin Porotchkin <kostap@marvell.com>
*
*/
/*
* Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200
*/
#include "armada-3720-espressobin.dtsi"
/ {
model = "Globalscale Marvell ESPRESSOBin Board V7";
compatible = "globalscale,espressobin-v7", "globalscale,espressobin",
"marvell,armada3720", "marvell,armada3710";
};
&switch0 {
ports {
port@1 {
reg = <1>;
label = "lan1";
phy-handle = <&switch0phy0>;
};
port@3 {
reg = <3>;
label = "wan";
phy-handle = <&switch0phy2>;
};
};
};

184
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
View File

@ -12,191 +12,9 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
#include "armada-3720-espressobin.dtsi"
/ {
model = "Globalscale Marvell ESPRESSOBin Board";
compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
vcc_sd_reg1: regulator {
compatible = "regulator-gpio";
regulator-name = "vcc_sd1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <1800000 0x1
3300000 0x0>;
enable-active-high;
};
};
/* J9 */
&pcie0 {
status = "okay";
phys = <&comphy1 0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
};
/* J6 */
&sata {
status = "okay";
phys = <&comphy2 0>;
phy-names = "sata-phy";
};
/* J1 */
&sdhci1 {
wp-inverted;
bus-width = <4>;
cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
marvell,pad-type = "sd";
vqmmc-supply = <&vcc_sd_reg1>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_pins>;
status = "okay";
};
/* U11 */
&sdhci0 {
non-removable;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,xenon-emmc;
marvell,xenon-tun-count = <9>;
marvell,pad-type = "fixed-1-8v";
pinctrl-names = "default";
pinctrl-0 = <&mmc_pins>;
/*
* This eMMC is not populated on all boards, so disable it by
* default and let the bootloader enable it, if it is present
*/
status = "disabled";
};
&spi0 {
status = "okay";
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <104000000>;
m25p,fast-read;
};
};
/* Exported on the micro USB connector J5 through an FTDI */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
/*
* Connector J17 and J18 expose a number of different features. Some pins are
* multiplexed. This is the case for instance for the following features:
* - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
* how to enable it. Beware that the signals are 1.8V TTL.
* - I2C
* - SPI
* - MMC
*/
/* J7 */
&usb3 {
status = "okay";
};
/* J8 */
&usb2 {
status = "okay";
};
&mdio {
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
};
port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
};
};
};
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
phy-mode = "rgmii-id";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};

177
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi Normal file
View File

@ -0,0 +1,177 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Globalscale Marvell ESPRESSOBin Board
* Copyright (C) 2016 Marvell
*
* Romain Perier <romain.perier@free-electrons.com>
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
/ {
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
vcc_sd_reg1: regulator {
compatible = "regulator-gpio";
regulator-name = "vcc_sd1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <1800000 0x1
3300000 0x0>;
enable-active-high;
};
};
/* J9 */
&pcie0 {
status = "okay";
phys = <&comphy1 0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
};
/* J6 */
&sata {
status = "okay";
phys = <&comphy2 0>;
phy-names = "sata-phy";
};
/* J1 */
&sdhci1 {
wp-inverted;
bus-width = <4>;
cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
marvell,pad-type = "sd";
vqmmc-supply = <&vcc_sd_reg1>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_pins>;
status = "okay";
};
&spi0 {
status = "okay";
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <104000000>;
m25p,fast-read;
};
};
/* Exported on the micro USB connector J5 through an FTDI */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
/*
* Connector J17 and J18 expose a number of different features. Some pins are
* multiplexed. This is the case for instance for the following features:
* - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
* how to enable it. Beware that the signals are 1.8V TTL.
* - I2C
* - SPI
* - MMC
*/
/* J7 */
&usb3 {
status = "okay";
};
/* J8 */
&usb2 {
status = "okay";
};
&mdio {
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
};
port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
};
};
};
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
phy-mode = "rgmii-id";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};

8
arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
View File

@ -111,6 +111,14 @@ sfp: sfp {
/* enabled by U-Boot if SFP module is present */
status = "disabled";
};
firmware {
turris-mox-rwtm {
compatible = "cznic,turris-mox-rwtm";
mboxes = <&rwtm 0>;
status = "okay";
};
};
};
&i2c0 {

28
arch/arm64/boot/dts/marvell/armada-70x0.dtsi
View File

@ -17,23 +17,23 @@ aliases {
/*
* Instantiate the CP110
*/
#define CP110_NAME cp0
#define CP110_BASE f2000000
#define CP110_PCIE_IO_BASE 0xf9000000
#define CP110_PCIE_MEM_BASE 0xf6000000
#define CP110_PCIE0_BASE f2600000
#define CP110_PCIE1_BASE f2620000
#define CP110_PCIE2_BASE f2640000
#define CP11X_NAME cp0
#define CP11X_BASE f2000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f2600000
#define CP11X_PCIE1_BASE f2620000
#define CP11X_PCIE2_BASE f2640000
#include "armada-cp110.dtsi"
#undef CP110_NAME
#undef CP110_BASE
#undef CP110_PCIE_IO_BASE
#undef CP110_PCIE_MEM_BASE
#undef CP110_PCIE0_BASE
#undef CP110_PCIE1_BASE
#undef CP110_PCIE2_BASE
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
&cp0_gpio1 {
status = "okay";

3
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
View File

@ -179,8 +179,7 @@ &cp0_pcie0 {
num-lanes = <4>;
num-viewport = <8>;
reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000
0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
<&cp0_comphy2 0>, <&cp0_comphy3 0>;
phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",

56
arch/arm64/boot/dts/marvell/armada-80x0.dtsi
View File

@ -19,44 +19,44 @@ aliases {
/*
* Instantiate the master CP110
*/
#define CP110_NAME cp0
#define CP110_BASE f2000000
#define CP110_PCIE_IO_BASE 0xf9000000
#define CP110_PCIE_MEM_BASE 0xf6000000
#define CP110_PCIE0_BASE f2600000
#define CP110_PCIE1_BASE f2620000
#define CP110_PCIE2_BASE f2640000
#define CP11X_NAME cp0
#define CP11X_BASE f2000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f2600000
#define CP11X_PCIE1_BASE f2620000
#define CP11X_PCIE2_BASE f2640000
#include "armada-cp110.dtsi"
#undef CP110_NAME
#undef CP110_BASE
#undef CP110_PCIE_IO_BASE
#undef CP110_PCIE_MEM_BASE
#undef CP110_PCIE0_BASE
#undef CP110_PCIE1_BASE
#undef CP110_PCIE2_BASE
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
/*
* Instantiate the slave CP110
*/
#define CP110_NAME cp1
#define CP110_BASE f4000000
#define CP110_PCIE_IO_BASE 0xfd000000
#define CP110_PCIE_MEM_BASE 0xfa000000
#define CP110_PCIE0_BASE f4600000
#define CP110_PCIE1_BASE f4620000
#define CP110_PCIE2_BASE f4640000
#define CP11X_NAME cp1
#define CP11X_BASE f4000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f4600000
#define CP11X_PCIE1_BASE f4620000
#define CP11X_PCIE2_BASE f4640000
#include "armada-cp110.dtsi"
#undef CP110_NAME
#undef CP110_BASE
#undef CP110_PCIE_IO_BASE
#undef CP110_PCIE_MEM_BASE
#undef CP110_PCIE0_BASE
#undef CP110_PCIE1_BASE
#undef CP110_PCIE2_BASE
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
/* The 80x0 has two CP blocks, but uses only one block from each. */
&cp1_gpio1 {

23
arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
View File

@ -21,6 +21,14 @@ cpu0: cpu@0 {
reg = <0x000>;
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
@ -28,6 +36,21 @@ cpu1: cpu@1 {
reg = <0x001>;
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
};
};

42
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
View File

@ -22,6 +22,13 @@ cpu0: cpu@0 {
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_0>;
};
cpu1: cpu@1 {
device_type = "cpu";
@ -30,6 +37,13 @@ cpu1: cpu@1 {
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_0>;
};
cpu2: cpu@100 {
device_type = "cpu";
@ -38,6 +52,13 @@ cpu2: cpu@100 {
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 1>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
};
cpu3: cpu@101 {
device_type = "cpu";
@ -46,6 +67,27 @@ cpu3: cpu@101 {
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 1>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
};
l2_0: l2-cache0 {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
};
};

460
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View File

@ -5,454 +5,26 @@
* Device Tree file for Marvell Armada AP806.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/dts-v1/;
#define AP_NAME ap806
#include "armada-ap80x.dtsi"
/ {
model = "Marvell Armada AP806";
compatible = "marvell,armada-ap806";
#address-cells = <2>;
#size-cells = <2>;
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
gpio0 = &ap_gpio;
spi0 = &spi0;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* This area matches the mapping done with a
* mainline U-Boot, and should be updated by the
* bootloader.
*/
psci-area@4000000 {
reg = <0x0 0x4000000 0x0 0x200000>;
no-map;
};
};
ap806 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
config-space@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x0 0x0 0xf0000000 0x1000000>;
gic: interrupt-controller@210000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x210000 0x10000>,
<0x220000 0x20000>,
<0x240000 0x20000>,
<0x260000 0x20000>;
gic_v2m0: v2m@280000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x280000 0x1000>;
arm,msi-base-spi = <160>;
arm,msi-num-spis = <32>;
};
gic_v2m1: v2m@290000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x290000 0x1000>;
arm,msi-base-spi = <192>;
arm,msi-num-spis = <32>;
};
gic_v2m2: v2m@2a0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x2a0000 0x1000>;
arm,msi-base-spi = <224>;
arm,msi-num-spis = <32>;
};
gic_v2m3: v2m@2b0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x2b0000 0x1000>;
arm,msi-base-spi = <256>;
arm,msi-num-spis = <32>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,cortex-a72-pmu";
interrupt-parent = <&pic>;
interrupts = <17>;
};
odmi: odmi@300000 {
compatible = "marvell,odmi-controller";
interrupt-controller;
msi-controller;
marvell,odmi-frames = <4>;
reg = <0x300000 0x4000>,
<0x304000 0x4000>,
<0x308000 0x4000>,
<0x30C000 0x4000>;
marvell,spi-base = <128>, <136>, <144>, <152>;
};
gicp: gicp@3f0040 {
compatible = "marvell,ap806-gicp";
reg = <0x3f0040 0x10>;
marvell,spi-ranges = <64 64>, <288 64>;
msi-controller;
};
pic: interrupt-controller@3f0100 {
compatible = "marvell,armada-8k-pic";
reg = <0x3f0100 0x10>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
sei: interrupt-controller@3f0200 {
compatible = "marvell,ap806-sei";
reg = <0x3f0200 0x40>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-controller;
msi-controller;
};
xor@400000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x400000 0x1000>,
<0x410000 0x1000>;
msi-parent = <&gic_v2m0>;
clocks = <&ap_clk 3>;
dma-coherent;
};
xor@420000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x420000 0x1000>,
<0x430000 0x1000>;
msi-parent = <&gic_v2m0>;
clocks = <&ap_clk 3>;
dma-coherent;
};
xor@440000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x440000 0x1000>,
<0x450000 0x1000>;
msi-parent = <&gic_v2m0>;
clocks = <&ap_clk 3>;
dma-coherent;
};
xor@460000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x460000 0x1000>,
<0x470000 0x1000>;
msi-parent = <&gic_v2m0>;
clocks = <&ap_clk 3>;
dma-coherent;
};
spi0: spi@510600 {
compatible = "marvell,armada-380-spi";
reg = <0x510600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ap_clk 3>;
status = "disabled";
};
i2c0: i2c@511000 {
compatible = "marvell,mv78230-i2c";
reg = <0x511000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&ap_clk 3>;
status = "disabled";
};
uart0: serial@512000 {
compatible = "snps,dw-apb-uart";
reg = <0x512000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&ap_clk 3>;
status = "disabled";
};
uart1: serial@512100 {
compatible = "snps,dw-apb-uart";
reg = <0x512100 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&ap_clk 3>;
status = "disabled";
};
watchdog: watchdog@610000 {
compatible = "arm,sbsa-gwdt";
reg = <0x610000 0x1000>, <0x600000 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
};
ap_sdhci0: sdhci@6e0000 {
compatible = "marvell,armada-ap806-sdhci";
reg = <0x6e0000 0x300>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
clocks = <&ap_clk 4>;
dma-coherent;
marvell,xenon-phy-slow-mode;
status = "disabled";
};
ap_syscon: system-controller@6f4000 {
compatible = "syscon", "simple-mfd";
reg = <0x6f4000 0x2000>;
ap_clk: clock {
compatible = "marvell,ap806-clock";
#clock-cells = <1>;
};
ap_pinctrl: pinctrl {
compatible = "marvell,ap806-pinctrl";
uart0_pins: uart0-pins {
marvell,pins = "mpp11", "mpp19";
marvell,function = "uart0";
};
};
ap_gpio: gpio@1040 {
compatible = "marvell,armada-8k-gpio";
offset = <0x1040>;
ngpios = <20>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&ap_pinctrl 0 0 20>;
};
};
ap_syscon1: system-controller@6f8000 {
compatible = "syscon", "simple-mfd";
reg = <0x6f8000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
cpu_clk: clock-cpu@278 {
compatible = "marvell,ap806-cpu-clock";
clocks = <&ap_clk 0>, <&ap_clk 1>;
#clock-cells = <1>;
reg = <0x278 0xa30>;
};
ap_thermal: thermal-sensor@80 {
compatible = "marvell,armada-ap806-thermal";
reg = <0x80 0x10>;
interrupt-parent = <&sei>;
interrupts = <18>;
#thermal-sensor-cells = <1>;
};
};
};
};
/*
* The thermal IP features one internal sensor plus, if applicable, one
* remote channel wired to one sensor per CPU.
*
* Only one thermal zone per AP/CP may trigger interrupts at a time, the
* first one that will have a critical trip point will be chosen.
*/
thermal-zones {
ap_thermal_ic: ap-thermal-ic {
polling-delay-passive = <0>; /* Interrupt driven */
polling-delay = <0>; /* Interrupt driven */
thermal-sensors = <&ap_thermal 0>;
trips {
ap_crit: ap-crit {
temperature = <100000>; /* mC degrees */
hysteresis = <2000>; /* mC degrees */
type = "critical";
};
};
cooling-maps { };
};
ap_thermal_cpu0: ap-thermal-cpu0 {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&ap_thermal 1>;
trips {
cpu0_hot: cpu0-hot {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_emerg: cpu0-emerg {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
};
cooling-maps {
map0_hot: map0-hot {
trip = <&cpu0_hot>;
cooling-device = <&cpu0 1 2>,
<&cpu1 1 2>;
};
map0_emerg: map0-ermerg {
trip = <&cpu0_emerg>;
cooling-device = <&cpu0 3 3>,
<&cpu1 3 3>;
};
};
};
ap_thermal_cpu1: ap-thermal-cpu1 {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&ap_thermal 2>;
trips {
cpu1_hot: cpu1-hot {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_emerg: cpu1-emerg {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
};
cooling-maps {
map1_hot: map1-hot {
trip = <&cpu1_hot>;
cooling-device = <&cpu0 1 2>,
<&cpu1 1 2>;
};
map1_emerg: map1-emerg {
trip = <&cpu1_emerg>;
cooling-device = <&cpu0 3 3>,
<&cpu1 3 3>;
};
};
};
ap_thermal_cpu2: ap-thermal-cpu2 {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&ap_thermal 3>;
trips {
cpu2_hot: cpu2-hot {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_emerg: cpu2-emerg {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
};
cooling-maps {
map2_hot: map2-hot {
trip = <&cpu2_hot>;
cooling-device = <&cpu2 1 2>,
<&cpu3 1 2>;
};
map2_emerg: map2-emerg {
trip = <&cpu2_emerg>;
cooling-device = <&cpu2 3 3>,
<&cpu3 3 3>;
};
};
};
ap_thermal_cpu3: ap-thermal-cpu3 {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&ap_thermal 4>;
trips {
cpu3_hot: cpu3-hot {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_emerg: cpu3-emerg {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
};
cooling-maps {
map3_hot: map3-bhot {
trip = <&cpu3_hot>;
cooling-device = <&cpu2 1 2>,
<&cpu3 1 2>;
};
map3_emerg: map3-emerg {
trip = <&cpu3_emerg>;
cooling-device = <&cpu2 3 3>,
<&cpu3 3 3>;
};
};
};
&ap_syscon0 {
ap_clk: clock {
compatible = "marvell,ap806-clock";
#clock-cells = <1>;
};
};
&ap_syscon1 {
cpu_clk: clock-cpu@278 {
compatible = "marvell,ap806-cpu-clock";
clocks = <&ap_clk 0>, <&ap_clk 1>;
#clock-cells = <1>;
reg = <0x278 0xa30>;
};
};

93
arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi Normal file
View File

@ -0,0 +1,93 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada AP807 Quad
*
* Copyright (C) 2019 Marvell Technology Group Ltd.
*/
#include "armada-ap807.dtsi"
/ {
model = "Marvell Armada AP807 Quad";
compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x000>;
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x001>;
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_0>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x100>;
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 1>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x101>;
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 1>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
};
l2_0: l2-cache0 {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
};
};

29
arch/arm64/boot/dts/marvell/armada-ap807.dtsi Normal file
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@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada AP807
*
* Copyright (C) 2019 Marvell Technology Group Ltd.
*/
#define AP_NAME ap807
#include "armada-ap80x.dtsi"
/ {
model = "Marvell Armada AP807";
compatible = "marvell,armada-ap807";
};
&ap_syscon0 {
ap_clk: clock {
compatible = "marvell,ap807-clock";
#clock-cells = <1>;
};
};
&ap_syscon1 {
cpu_clk: clock-cpu {
compatible = "marvell,ap807-cpu-clock";
clocks = <&ap_clk 0>, <&ap_clk 1>;
#clock-cells = <1>;
};
};

444
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi Normal file
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@ -0,0 +1,444 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Marvell Technology Group Ltd.
*
* Device Tree file for Marvell Armada AP80x.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
gpio0 = &ap_gpio;
spi0 = &spi0;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* This area matches the mapping done with a
* mainline U-Boot, and should be updated by the
* bootloader.
*/
psci-area@4000000 {
reg = <0x0 0x4000000 0x0 0x200000>;
no-map;
};
};
AP_NAME {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
config-space@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x0 0x0 0xf0000000 0x1000000>;
gic: interrupt-controller@210000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x210000 0x10000>,
<0x220000 0x20000>,
<0x240000 0x20000>,
<0x260000 0x20000>;
gic_v2m0: v2m@280000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x280000 0x1000>;
arm,msi-base-spi = <160>;
arm,msi-num-spis = <32>;
};
gic_v2m1: v2m@290000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x290000 0x1000>;
arm,msi-base-spi = <192>;
arm,msi-num-spis = <32>;
};
gic_v2m2: v2m@2a0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x2a0000 0x1000>;
arm,msi-base-spi = <224>;
arm,msi-num-spis = <32>;
};
gic_v2m3: v2m@2b0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x2b0000 0x1000>;
arm,msi-base-spi = <256>;
arm,msi-num-spis = <32>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,cortex-a72-pmu";
interrupt-parent = <&pic>;
interrupts = <17>;
};
odmi: odmi@300000 {
compatible = "marvell,odmi-controller";
interrupt-controller;
msi-controller;
marvell,odmi-frames = <4>;
reg = <0x300000 0x4000>,
<0x304000 0x4000>,
<0x308000 0x4000>,
<0x30C000 0x4000>;
marvell,spi-base = <128>, <136>, <144>, <152>;
};
gicp: gicp@3f0040 {
compatible = "marvell,ap806-gicp";
reg = <0x3f0040 0x10>;
marvell,spi-ranges = <64 64>, <288 64>;
msi-controller;
};
pic: interrupt-controller@3f0100 {
compatible = "marvell,armada-8k-pic";
reg = <0x3f0100 0x10>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
sei: interrupt-controller@3f0200 {
compatible = "marvell,ap806-sei";
reg = <0x3f0200 0x40>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-controller;
msi-controller;
};
xor@400000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x400000 0x1000>,
<0x410000 0x1000>;
msi-parent = <&gic_v2m0>;
clocks = <&ap_clk 3>;
dma-coherent;
};
xor@420000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x420000 0x1000>,
<0x430000 0x1000>;
msi-parent = <&gic_v2m0>;
clocks = <&ap_clk 3>;
dma-coherent;
};
xor@440000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x440000 0x1000>,
<0x450000 0x1000>;
msi-parent = <&gic_v2m0>;
clocks = <&ap_clk 3>;
dma-coherent;
};
xor@460000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x460000 0x1000>,
<0x470000 0x1000>;
msi-parent = <&gic_v2m0>;
clocks = <&ap_clk 3>;
dma-coherent;
};
spi0: spi@510600 {
compatible = "marvell,armada-380-spi";
reg = <0x510600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ap_clk 3>;
status = "disabled";
};
i2c0: i2c@511000 {
compatible = "marvell,mv78230-i2c";
reg = <0x511000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&ap_clk 3>;
status = "disabled";
};
uart0: serial@512000 {
compatible = "snps,dw-apb-uart";
reg = <0x512000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&ap_clk 3>;
status = "disabled";
};
uart1: serial@512100 {
compatible = "snps,dw-apb-uart";
reg = <0x512100 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&ap_clk 3>;
status = "disabled";
};
watchdog: watchdog@610000 {
compatible = "arm,sbsa-gwdt";
reg = <0x610000 0x1000>, <0x600000 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
};
ap_sdhci0: sdhci@6e0000 {
compatible = "marvell,armada-ap806-sdhci";
reg = <0x6e0000 0x300>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
clocks = <&ap_clk 4>;
dma-coherent;
marvell,xenon-phy-slow-mode;
status = "disabled";
};
ap_syscon0: system-controller@6f4000 {
compatible = "syscon", "simple-mfd";
reg = <0x6f4000 0x2000>;
ap_pinctrl: pinctrl {
compatible = "marvell,ap806-pinctrl";
uart0_pins: uart0-pins {
marvell,pins = "mpp11", "mpp19";
marvell,function = "uart0";
};
};
ap_gpio: gpio@1040 {
compatible = "marvell,armada-8k-gpio";
offset = <0x1040>;
ngpios = <20>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&ap_pinctrl 0 0 20>;
};
};
ap_syscon1: system-controller@6f8000 {
compatible = "syscon", "simple-mfd";
reg = <0x6f8000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ap_thermal: thermal-sensor@80 {
compatible = "marvell,armada-ap806-thermal";
reg = <0x80 0x10>;
interrupt-parent = <&sei>;
interrupts = <18>;
#thermal-sensor-cells = <1>;
};
};
};
};
/*
* The thermal IP features one internal sensor plus, if applicable, one
* remote channel wired to one sensor per CPU.
*
* Only one thermal zone per AP/CP may trigger interrupts at a time, the
* first one that will have a critical trip point will be chosen.
*/
thermal-zones {
ap_thermal_ic: ap-thermal-ic {
polling-delay-passive = <0>; /* Interrupt driven */
polling-delay = <0>; /* Interrupt driven */
thermal-sensors = <&ap_thermal 0>;
trips {
ap_crit: ap-crit {
temperature = <100000>; /* mC degrees */
hysteresis = <2000>; /* mC degrees */
type = "critical";
};
};
cooling-maps { };
};
ap_thermal_cpu0: ap-thermal-cpu0 {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&ap_thermal 1>;
trips {
cpu0_hot: cpu0-hot {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_emerg: cpu0-emerg {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
};
cooling-maps {
map0_hot: map0-hot {
trip = <&cpu0_hot>;
cooling-device = <&cpu0 1 2>,
<&cpu1 1 2>;
};
map0_emerg: map0-ermerg {
trip = <&cpu0_emerg>;
cooling-device = <&cpu0 3 3>,
<&cpu1 3 3>;
};
};
};
ap_thermal_cpu1: ap-thermal-cpu1 {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&ap_thermal 2>;
trips {
cpu1_hot: cpu1-hot {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_emerg: cpu1-emerg {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
};
cooling-maps {
map1_hot: map1-hot {
trip = <&cpu1_hot>;
cooling-device = <&cpu0 1 2>,
<&cpu1 1 2>;
};
map1_emerg: map1-emerg {
trip = <&cpu1_emerg>;
cooling-device = <&cpu0 3 3>,
<&cpu1 3 3>;
};
};
};
ap_thermal_cpu2: ap-thermal-cpu2 {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&ap_thermal 3>;
trips {
cpu2_hot: cpu2-hot {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_emerg: cpu2-emerg {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
};
cooling-maps {
map2_hot: map2-hot {
trip = <&cpu2_hot>;
cooling-device = <&cpu2 1 2>,
<&cpu3 1 2>;
};
map2_emerg: map2-emerg {
trip = <&cpu2_emerg>;
cooling-device = <&cpu2 3 3>,
<&cpu3 3 3>;
};
};
};
ap_thermal_cpu3: ap-thermal-cpu3 {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&ap_thermal 4>;
trips {
cpu3_hot: cpu3-hot {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_emerg: cpu3-emerg {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
};
cooling-maps {
map3_hot: map3-bhot {
trip = <&cpu3_hot>;
cooling-device = <&cpu2 1 2>,
<&cpu3 1 2>;
};
map3_emerg: map3-emerg {
trip = <&cpu3_emerg>;
cooling-device = <&cpu2 3 3>,
<&cpu3 3 3>;
};
};
};
};
};

4
arch/arm64/boot/dts/marvell/armada-common.dtsi
View File

@ -6,6 +6,6 @@
/* Common definitions used by Armada 7K/8K DTs */
#define PASTER(x, y) x ## y
#define EVALUATOR(x, y) PASTER(x, y)
#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
#define CP110_NODE_NAME(name) EVALUATOR(CP110_NAME, EVALUATOR(-, name))
#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name))
#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name))
#define ADDRESSIFY(addr) EVALUATOR(0x, addr)

575
arch/arm64/boot/dts/marvell/armada-cp110.dtsi
View File

@ -1,579 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
* Copyright (C) 2019 Marvell Technology Group Ltd.
*
* Device Tree file for Marvell Armada CP110.
*/
#include <dt-bindings/interrupt-controller/mvebu-icu.h>
#include <dt-bindings/thermal/thermal.h>
#define CP11X_TYPE cp110
#include "armada-common.dtsi"
#include "armada-cp11x.dtsi"
#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
/ {
/*
* The contents of the node are defined below, in order to
* save one indentation level
*/
CP110_NAME: CP110_NAME { };
/*
* CPs only have one sensor in the thermal IC.
*
* The cooling maps are empty as there are no cooling devices.
*/
thermal-zones {
CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) {
polling-delay-passive = <0>; /* Interrupt driven */
polling-delay = <0>; /* Interrupt driven */
thermal-sensors = <&CP110_LABEL(thermal) 0>;
trips {
CP110_LABEL(crit): crit {
temperature = <100000>; /* mC degrees */
hysteresis = <2000>; /* mC degrees */
type = "critical";
};
};
cooling-maps { };
};
};
};
&CP110_NAME {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&CP110_LABEL(icu_nsr)>;
ranges;
config-space@CP110_BASE {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
CP110_LABEL(ethernet): ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
<&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
<&CP110_LABEL(clk) 1 18>;
clock-names = "pp_clk", "gop_clk",
"mg_clk", "mg_core_clk", "axi_clk";
marvell,system-controller = <&CP110_LABEL(syscon0)>;
status = "disabled";
dma-coherent;
CP110_LABEL(eth0): eth0 {
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
<43 IRQ_TYPE_LEVEL_HIGH>,
<47 IRQ_TYPE_LEVEL_HIGH>,
<51 IRQ_TYPE_LEVEL_HIGH>,
<55 IRQ_TYPE_LEVEL_HIGH>,
<59 IRQ_TYPE_LEVEL_HIGH>,
<63 IRQ_TYPE_LEVEL_HIGH>,
<67 IRQ_TYPE_LEVEL_HIGH>,
<71 IRQ_TYPE_LEVEL_HIGH>,
<129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hif0", "hif1", "hif2",
"hif3", "hif4", "hif5", "hif6", "hif7",
"hif8", "link";
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
CP110_LABEL(eth1): eth1 {
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
<44 IRQ_TYPE_LEVEL_HIGH>,
<48 IRQ_TYPE_LEVEL_HIGH>,
<52 IRQ_TYPE_LEVEL_HIGH>,
<56 IRQ_TYPE_LEVEL_HIGH>,
<60 IRQ_TYPE_LEVEL_HIGH>,
<64 IRQ_TYPE_LEVEL_HIGH>,
<68 IRQ_TYPE_LEVEL_HIGH>,
<72 IRQ_TYPE_LEVEL_HIGH>,
<128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hif0", "hif1", "hif2",
"hif3", "hif4", "hif5", "hif6", "hif7",
"hif8", "link";
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
CP110_LABEL(eth2): eth2 {
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
<45 IRQ_TYPE_LEVEL_HIGH>,
<49 IRQ_TYPE_LEVEL_HIGH>,
<53 IRQ_TYPE_LEVEL_HIGH>,
<57 IRQ_TYPE_LEVEL_HIGH>,
<61 IRQ_TYPE_LEVEL_HIGH>,
<65 IRQ_TYPE_LEVEL_HIGH>,
<69 IRQ_TYPE_LEVEL_HIGH>,
<73 IRQ_TYPE_LEVEL_HIGH>,
<127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hif0", "hif1", "hif2",
"hif3", "hif4", "hif5", "hif6", "hif7",
"hif8", "link";
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
};
};
CP110_LABEL(comphy): phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&CP110_LABEL(syscon0)>;
clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
<&CP110_LABEL(clk) 1 18>;
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
CP110_LABEL(comphy0): phy@0 {
reg = <0>;
#phy-cells = <1>;
};
CP110_LABEL(comphy1): phy@1 {
reg = <1>;
#phy-cells = <1>;
};
CP110_LABEL(comphy2): phy@2 {
reg = <2>;
#phy-cells = <1>;
};
CP110_LABEL(comphy3): phy@3 {
reg = <3>;
#phy-cells = <1>;
};
CP110_LABEL(comphy4): phy@4 {
reg = <4>;
#phy-cells = <1>;
};
CP110_LABEL(comphy5): phy@5 {
reg = <5>;
#phy-cells = <1>;
};
};
CP110_LABEL(mdio): mdio@12a200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
<&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
status = "disabled";
};
CP110_LABEL(xmdio): mdio@12a600 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,xmdio";
reg = <0x12a600 0x10>;
clocks = <&CP110_LABEL(clk) 1 5>,
<&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
status = "disabled";
};
CP110_LABEL(icu): interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x440>;
#address-cells = <1>;
#size-cells = <1>;
CP110_LABEL(icu_nsr): interrupt-controller@10 {
compatible = "marvell,cp110-icu-nsr";
reg = <0x10 0x20>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&gicp>;
};
CP110_LABEL(icu_sei): interrupt-controller@50 {
compatible = "marvell,cp110-icu-sei";
reg = <0x50 0x10>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&sei>;
};
};
CP110_LABEL(rtc): rtc@284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
};
CP110_LABEL(syscon0): system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x2000>;
CP110_LABEL(clk): clock {
compatible = "marvell,cp110-clock";
#clock-cells = <2>;
};
CP110_LABEL(gpio1): gpio@100 {
compatible = "marvell,armada-8k-gpio";
offset = <0x100>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
interrupt-controller;
interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
<85 IRQ_TYPE_LEVEL_HIGH>,
<84 IRQ_TYPE_LEVEL_HIGH>,
<83 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
status = "disabled";
};
CP110_LABEL(gpio2): gpio@140 {
compatible = "marvell,armada-8k-gpio";
offset = <0x140>;
ngpios = <31>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
interrupt-controller;
interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
<81 IRQ_TYPE_LEVEL_HIGH>,
<80 IRQ_TYPE_LEVEL_HIGH>,
<79 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
status = "disabled";
};
};
CP110_LABEL(syscon1): system-controller@400000 {
compatible = "syscon", "simple-mfd";
reg = <0x400000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
CP110_LABEL(thermal): thermal-sensor@70 {
compatible = "marvell,armada-cp110-thermal";
reg = <0x70 0x10>;
interrupts-extended =
<&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <1>;
};
};
CP110_LABEL(usb3_0): usb3@500000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 22>,
<&CP110_LABEL(clk) 1 16>;
status = "disabled";
};
CP110_LABEL(usb3_1): usb3@510000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 23>,
<&CP110_LABEL(clk) 1 16>;
status = "disabled";
};
CP110_LABEL(sata0): sata@540000 {
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
dma-coherent;
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 15>,
<&CP110_LABEL(clk) 1 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata-port@0 {
reg = <0>;
};
sata-port@1 {
reg = <1>;
};
};
CP110_LABEL(xor0): xor@6a0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 8>,
<&CP110_LABEL(clk) 1 14>;
};
CP110_LABEL(xor1): xor@6c0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 7>,
<&CP110_LABEL(clk) 1 14>;
};
CP110_LABEL(spi0): spi@700600 {
compatible = "marvell,armada-380-spi";
reg = <0x700600 0x50>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clock-names = "core", "axi";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
status = "disabled";
};
CP110_LABEL(spi1): spi@700680 {
compatible = "marvell,armada-380-spi";
reg = <0x700680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "core", "axi";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
status = "disabled";
};
CP110_LABEL(i2c0): i2c@701000 {
compatible = "marvell,mv78230-i2c";
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
status = "disabled";
};
CP110_LABEL(i2c1): i2c@701100 {
compatible = "marvell,mv78230-i2c";
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
status = "disabled";
};
CP110_LABEL(uart0): serial@702000 {
compatible = "snps,dw-apb-uart";
reg = <0x702000 0x100>;
reg-shift = <2>;
interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
status = "disabled";
};
CP110_LABEL(uart1): serial@702100 {
compatible = "snps,dw-apb-uart";
reg = <0x702100 0x100>;
reg-shift = <2>;
interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
status = "disabled";
};
CP110_LABEL(uart2): serial@702200 {
compatible = "snps,dw-apb-uart";
reg = <0x702200 0x100>;
reg-shift = <2>;
interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
status = "disabled";
};
CP110_LABEL(uart3): serial@702300 {
compatible = "snps,dw-apb-uart";
reg = <0x702300 0x100>;
reg-shift = <2>;
interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
status = "disabled";
};
CP110_LABEL(nand_controller): nand@720000 {
/*
* Due to the limitation of the pins available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
compatible = "marvell,armada-8k-nand-controller",
"marvell,armada370-nand-controller";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 2>,
<&CP110_LABEL(clk) 1 17>;
marvell,system-controller = <&CP110_LABEL(syscon0)>;
status = "disabled";
};
CP110_LABEL(trng): trng@760000 {
compatible = "marvell,armada-8k-rng",
"inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 25>,
<&CP110_LABEL(clk) 1 17>;
status = "okay";
};
CP110_LABEL(sdhci0): sdhci@780000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0x780000 0x300>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "axi";
clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
dma-coherent;
status = "disabled";
};
CP110_LABEL(crypto): crypto@800000 {
compatible = "inside-secure,safexcel-eip197b";
reg = <0x800000 0x200000>;
interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
<88 IRQ_TYPE_LEVEL_HIGH>,
<89 IRQ_TYPE_LEVEL_HIGH>,
<90 IRQ_TYPE_LEVEL_HIGH>,
<91 IRQ_TYPE_LEVEL_HIGH>,
<92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 26>,
<&CP110_LABEL(clk) 1 17>;
dma-coherent;
};
};
CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
<0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
status = "disabled";
};
CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
<0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
status = "disabled";
};
CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
<0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
status = "disabled";
};
};
#undef CP11X_TYPE

12
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Marvell Technology Group Ltd.
*
* Device Tree file for Marvell Armada CP115.
*/
#define CP11X_TYPE cp115
#include "armada-cp11x.dtsi"
#undef CP11X_TYPE

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
* Device Tree file for Marvell Armada CP11x.
*/
#include <dt-bindings/interrupt-controller/mvebu-icu.h>
#include <dt-bindings/thermal/thermal.h>
#include "armada-common.dtsi"
#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
/ {
/*
* The contents of the node are defined below, in order to
* save one indentation level
*/
CP11X_NAME: CP11X_NAME { };
/*
* CPs only have one sensor in the thermal IC.
*
* The cooling maps are empty as there are no cooling devices.
*/
thermal-zones {
CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
polling-delay-passive = <0>; /* Interrupt driven */
polling-delay = <0>; /* Interrupt driven */
thermal-sensors = <&CP11X_LABEL(thermal) 0>;
trips {
CP11X_LABEL(crit): crit {
temperature = <100000>; /* mC degrees */
hysteresis = <2000>; /* mC degrees */
type = "critical";
};
};
cooling-maps { };
};
};
};
&CP11X_NAME {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
ranges;
config-space@CP11X_BASE {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
CP11X_LABEL(ethernet): ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
<&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
<&CP11X_LABEL(clk) 1 18>;
clock-names = "pp_clk", "gop_clk",
"mg_clk", "mg_core_clk", "axi_clk";
marvell,system-controller = <&CP11X_LABEL(syscon0)>;
status = "disabled";
dma-coherent;
CP11X_LABEL(eth0): eth0 {
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
<43 IRQ_TYPE_LEVEL_HIGH>,
<47 IRQ_TYPE_LEVEL_HIGH>,
<51 IRQ_TYPE_LEVEL_HIGH>,
<55 IRQ_TYPE_LEVEL_HIGH>,
<59 IRQ_TYPE_LEVEL_HIGH>,
<63 IRQ_TYPE_LEVEL_HIGH>,
<67 IRQ_TYPE_LEVEL_HIGH>,
<71 IRQ_TYPE_LEVEL_HIGH>,
<129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hif0", "hif1", "hif2",
"hif3", "hif4", "hif5", "hif6", "hif7",
"hif8", "link";
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
CP11X_LABEL(eth1): eth1 {
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
<44 IRQ_TYPE_LEVEL_HIGH>,
<48 IRQ_TYPE_LEVEL_HIGH>,
<52 IRQ_TYPE_LEVEL_HIGH>,
<56 IRQ_TYPE_LEVEL_HIGH>,
<60 IRQ_TYPE_LEVEL_HIGH>,
<64 IRQ_TYPE_LEVEL_HIGH>,
<68 IRQ_TYPE_LEVEL_HIGH>,
<72 IRQ_TYPE_LEVEL_HIGH>,
<128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hif0", "hif1", "hif2",
"hif3", "hif4", "hif5", "hif6", "hif7",
"hif8", "link";
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
CP11X_LABEL(eth2): eth2 {
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
<45 IRQ_TYPE_LEVEL_HIGH>,
<49 IRQ_TYPE_LEVEL_HIGH>,
<53 IRQ_TYPE_LEVEL_HIGH>,
<57 IRQ_TYPE_LEVEL_HIGH>,
<61 IRQ_TYPE_LEVEL_HIGH>,
<65 IRQ_TYPE_LEVEL_HIGH>,
<69 IRQ_TYPE_LEVEL_HIGH>,
<73 IRQ_TYPE_LEVEL_HIGH>,
<127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hif0", "hif1", "hif2",
"hif3", "hif4", "hif5", "hif6", "hif7",
"hif8", "link";
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
};
};
CP11X_LABEL(comphy): phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&CP11X_LABEL(syscon0)>;
clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
<&CP11X_LABEL(clk) 1 18>;
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
CP11X_LABEL(comphy0): phy@0 {
reg = <0>;
#phy-cells = <1>;
};
CP11X_LABEL(comphy1): phy@1 {
reg = <1>;
#phy-cells = <1>;
};
CP11X_LABEL(comphy2): phy@2 {
reg = <2>;
#phy-cells = <1>;
};
CP11X_LABEL(comphy3): phy@3 {
reg = <3>;
#phy-cells = <1>;
};
CP11X_LABEL(comphy4): phy@4 {
reg = <4>;
#phy-cells = <1>;
};
CP11X_LABEL(comphy5): phy@5 {
reg = <5>;
#phy-cells = <1>;
};
};
CP11X_LABEL(mdio): mdio@12a200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
<&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
status = "disabled";
};
CP11X_LABEL(xmdio): mdio@12a600 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,xmdio";
reg = <0x12a600 0x10>;
clocks = <&CP11X_LABEL(clk) 1 5>,
<&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
status = "disabled";
};
CP11X_LABEL(icu): interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x440>;
#address-cells = <1>;
#size-cells = <1>;
CP11X_LABEL(icu_nsr): interrupt-controller@10 {
compatible = "marvell,cp110-icu-nsr";
reg = <0x10 0x20>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&gicp>;
};
CP11X_LABEL(icu_sei): interrupt-controller@50 {
compatible = "marvell,cp110-icu-sei";
reg = <0x50 0x10>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&sei>;
};
};
CP11X_LABEL(rtc): rtc@284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
};
CP11X_LABEL(syscon0): system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x2000>;
CP11X_LABEL(clk): clock {
compatible = "marvell,cp110-clock";
#clock-cells = <2>;
};
CP11X_LABEL(gpio1): gpio@100 {
compatible = "marvell,armada-8k-gpio";
offset = <0x100>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
interrupt-controller;
interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
<85 IRQ_TYPE_LEVEL_HIGH>,
<84 IRQ_TYPE_LEVEL_HIGH>,
<83 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
status = "disabled";
};
CP11X_LABEL(gpio2): gpio@140 {
compatible = "marvell,armada-8k-gpio";
offset = <0x140>;
ngpios = <31>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
interrupt-controller;
interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
<81 IRQ_TYPE_LEVEL_HIGH>,
<80 IRQ_TYPE_LEVEL_HIGH>,
<79 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
status = "disabled";
};
};
CP11X_LABEL(syscon1): system-controller@400000 {
compatible = "syscon", "simple-mfd";
reg = <0x400000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
CP11X_LABEL(thermal): thermal-sensor@70 {
compatible = "marvell,armada-cp110-thermal";
reg = <0x70 0x10>;
interrupts-extended =
<&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <1>;
};
};
CP11X_LABEL(usb3_0): usb3@500000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 22>,
<&CP11X_LABEL(clk) 1 16>;
status = "disabled";
};
CP11X_LABEL(usb3_1): usb3@510000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 23>,
<&CP11X_LABEL(clk) 1 16>;
status = "disabled";
};
CP11X_LABEL(sata0): sata@540000 {
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
dma-coherent;
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP11X_LABEL(clk) 1 15>,
<&CP11X_LABEL(clk) 1 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata-port@0 {
reg = <0>;
};
sata-port@1 {
reg = <1>;
};
};
CP11X_LABEL(xor0): xor@6a0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 8>,
<&CP11X_LABEL(clk) 1 14>;
};
CP11X_LABEL(xor1): xor@6c0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 7>,
<&CP11X_LABEL(clk) 1 14>;
};
CP11X_LABEL(spi0): spi@700600 {
compatible = "marvell,armada-380-spi";
reg = <0x700600 0x50>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clock-names = "core", "axi";
clocks = <&CP11X_LABEL(clk) 1 21>,
<&CP11X_LABEL(clk) 1 17>;
status = "disabled";
};
CP11X_LABEL(spi1): spi@700680 {
compatible = "marvell,armada-380-spi";
reg = <0x700680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "core", "axi";
clocks = <&CP11X_LABEL(clk) 1 21>,
<&CP11X_LABEL(clk) 1 17>;
status = "disabled";
};
CP11X_LABEL(i2c0): i2c@701000 {
compatible = "marvell,mv78230-i2c";
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 21>,
<&CP11X_LABEL(clk) 1 17>;
status = "disabled";
};
CP11X_LABEL(i2c1): i2c@701100 {
compatible = "marvell,mv78230-i2c";
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 21>,
<&CP11X_LABEL(clk) 1 17>;
status = "disabled";
};
CP11X_LABEL(uart0): serial@702000 {
compatible = "snps,dw-apb-uart";
reg = <0x702000 0x100>;
reg-shift = <2>;
interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP11X_LABEL(clk) 1 21>,
<&CP11X_LABEL(clk) 1 17>;
status = "disabled";
};
CP11X_LABEL(uart1): serial@702100 {
compatible = "snps,dw-apb-uart";
reg = <0x702100 0x100>;
reg-shift = <2>;
interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP11X_LABEL(clk) 1 21>,
<&CP11X_LABEL(clk) 1 17>;
status = "disabled";
};
CP11X_LABEL(uart2): serial@702200 {
compatible = "snps,dw-apb-uart";
reg = <0x702200 0x100>;
reg-shift = <2>;
interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP11X_LABEL(clk) 1 21>,
<&CP11X_LABEL(clk) 1 17>;
status = "disabled";
};
CP11X_LABEL(uart3): serial@702300 {
compatible = "snps,dw-apb-uart";
reg = <0x702300 0x100>;
reg-shift = <2>;
interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP11X_LABEL(clk) 1 21>,
<&CP11X_LABEL(clk) 1 17>;
status = "disabled";
};
CP11X_LABEL(nand_controller): nand@720000 {
/*
* Due to the limitation of the pins available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
compatible = "marvell,armada-8k-nand-controller",
"marvell,armada370-nand-controller";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 2>,
<&CP11X_LABEL(clk) 1 17>;
marvell,system-controller = <&CP11X_LABEL(syscon0)>;
status = "disabled";
};
CP11X_LABEL(trng): trng@760000 {
compatible = "marvell,armada-8k-rng",
"inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 25>,
<&CP11X_LABEL(clk) 1 17>;
status = "okay";
};
CP11X_LABEL(sdhci0): sdhci@780000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0x780000 0x300>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "axi";
clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
dma-coherent;
status = "disabled";
};
CP11X_LABEL(crypto): crypto@800000 {
compatible = "inside-secure,safexcel-eip197b";
reg = <0x800000 0x200000>;
interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
<88 IRQ_TYPE_LEVEL_HIGH>,
<89 IRQ_TYPE_LEVEL_HIGH>,
<90 IRQ_TYPE_LEVEL_HIGH>,
<91 IRQ_TYPE_LEVEL_HIGH>,
<92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 26>,
<&CP11X_LABEL(clk) 1 17>;
dma-coherent;
};
};
CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
<0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
/* non-prefetchable memory */
ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
status = "disabled";
};
CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
<0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
/* non-prefetchable memory */
ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
status = "disabled";
};
CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
<0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
/* non-prefetchable memory */
ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
status = "disabled";
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Marvell International Ltd.
*
* Device tree for the CN9130-DB board.
*/
#include "cn9130.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada CN9130-DB";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
gpio1 = &cp0_gpio1;
gpio2 = &cp0_gpio2;
i2c0 = &cp0_i2c0;
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
spi1 = &cp0_spi0;
spi2 = &cp0_spi1;
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
ap0_reg_sd_vccq: ap0_sd_vccq@0 {
compatible = "regulator-gpio";
regulator-name = "ap0_sd_vccq";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1 3300000 0x0>;
};
cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
compatible = "regulator-fixed";
regulator-name = "cp0-xhci0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
};
cp0_usb3_0_phy0: cp0_usb3_phy@0 {
compatible = "usb-nop-xceiv";
vcc-supply = <&cp0_reg_usb3_vbus0>;
};
cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
compatible = "regulator-fixed";
regulator-name = "cp0-xhci1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
};
cp0_usb3_0_phy1: cp0_usb3_phy@1 {
compatible = "usb-nop-xceiv";
vcc-supply = <&cp0_reg_usb3_vbus1>;
};
cp0_reg_sd_vccq: cp0_sd_vccq@0 {
compatible = "regulator-gpio";
regulator-name = "cp0_sd_vccq";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1
3300000 0x0>;
};
cp0_reg_sd_vcc: cp0_sd_vcc@0 {
compatible = "regulator-fixed";
regulator-name = "cp0_sd_vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
cp0_sfp_eth0: sfp-eth@0 {
compatible = "sff,sfp";
i2c-bus = <&cp0_sfpp0_i2c>;
los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
/*
* SFP cages are unconnected on early PCBs because of an the I2C
* lanes not being connected. Prevent the port for being
* unusable by disabling the SFP node.
*/
status = "disabled";
};
};
&uart0 {
status = "okay";
};
/* on-board eMMC - U9 */
&ap_sdhci0 {
pinctrl-names = "default";
bus-width = <8>;
vqmmc-supply = <&ap0_reg_sd_vccq>;
status = "okay";
};
&cp0_crypto {
status = "disabled";
};
&cp0_ethernet {
status = "okay";
};
/* SLM-1521-V2, CON9 */
&cp0_eth0 {
status = "disabled";
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cp0_comphy4 0>;
managed = "in-band-status";
sfp = <&cp0_sfp_eth0>;
};
/* CON56 */
&cp0_eth1 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
/* CON57 */
&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
&cp0_gpio1 {
status = "okay";
};
&cp0_gpio2 {
status = "okay";
};
&cp0_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
clock-frequency = <100000>;
/* U36 */
expander0: pca953x@21 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
reg = <0x21>;
status = "okay";
};
/* U42 */
eeprom0: eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <0x20>;
};
/* U38 */
eeprom1: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <0x20>;
};
};
&cp0_i2c1 {
status = "okay";
clock-frequency = <100000>;
/* SLM-1521-V2 - U3 */
i2c-mux@72 { /* verify address - depends on dpr */
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x72>;
cp0_sfpp0_i2c: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* U12 */
cp0_module_expander1: pca9555@21 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
reg = <0x21>;
};
};
};
};
&cp0_mdio {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
/* U54 */
&cp0_nand_controller {
pinctrl-names = "default";
pinctrl-0 = <&nand_pins &nand_rb>;
nand@0 {
reg = <0>;
label = "main-storage";
nand-rb = <0>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0 0x200000>;
};
partition@200000 {
label = "Linux";
reg = <0x200000 0xd00000>;
};
partition@1000000 {
label = "Filesystem";
reg = <0x1000000 0x3f000000>;
};
};
};
};
/* SLM-1521-V2, CON6 */
&cp0_pcie0 {
status = "okay";
num-lanes = <4>;
num-viewport = <8>;
/* Generic PHY, providing serdes lanes */
phys = <&cp0_comphy0 0
&cp0_comphy1 0
&cp0_comphy2 0
&cp0_comphy3 0>;
};
&cp0_sata0 {
status = "okay";
/* SLM-1521-V2, CON2 */
sata-port@1 {
status = "okay";
/* Generic PHY, providing serdes lanes */
phys = <&cp0_comphy5 1>;
};
};
/* CON 28 */
&cp0_sdhci0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_sdhci_pins
&cp0_sdhci_cd_pins>;
bus-width = <4>;
cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
no-1-8-v;
vqmmc-supply = <&cp0_reg_sd_vccq>;
vmmc-supply = <&cp0_reg_sd_vcc>;
};
/* U55 */
&cp0_spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
reg = <0x700680 0x50>;
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
/* On-board MUX does not allow higher frequencies */
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot-0";
reg = <0x0 0x200000>;
};
partition@400000 {
label = "Filesystem-0";
reg = <0x200000 0xe00000>;
};
};
};
};
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp0_i2c0_pins: cp0-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp0_i2c1_pins: cp0-i2c-pins-1 {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
marvell,pins = "mpp0", "mpp1", "mpp2",
"mpp3", "mpp4", "mpp5",
"mpp6", "mpp7", "mpp8",
"mpp9", "mpp10", "mpp11";
marvell,function = "ge0";
};
cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
marvell,pins = "mpp44", "mpp45", "mpp46",
"mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52",
"mpp53", "mpp54", "mpp55";
marvell,function = "ge1";
};
cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
marvell,pins = "mpp43";
marvell,function = "gpio";
};
cp0_sdhci_pins: cp0-sdhi-pins-0 {
marvell,pins = "mpp56", "mpp57", "mpp58",
"mpp59", "mpp60", "mpp61";
marvell,function = "sdio";
};
cp0_spi0_pins: cp0-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
nand_pins: nand-pins {
marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
"mpp19", "mpp20", "mpp21", "mpp22",
"mpp23", "mpp24", "mpp25", "mpp26",
"mpp27";
marvell,function = "dev";
};
nand_rb: nand-rb {
marvell,pins = "mpp13";
marvell,function = "nf";
};
};
};
&cp0_usb3_0 {
status = "okay";
usb-phy = <&cp0_usb3_0_phy0>;
phy-names = "usb";
};
&cp0_usb3_1 {
status = "okay";
usb-phy = <&cp0_usb3_0_phy1>;
phy-names = "usb";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Marvell International Ltd.
*
* Device tree for the CN9130 SoC.
*/
#include "armada-ap807-quad.dtsi"
/ {
model = "Marvell Armada CN9130 SoC";
compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
"marvell,armada-ap807";
};
/*
* Instantiate the internal CP115
*/
#define CP11X_NAME cp0
#define CP11X_BASE f2000000
#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
0xe0000000 + ((iface - 1) * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
#define CP11X_PCIE0_BASE f2600000
#define CP11X_PCIE1_BASE f2620000
#define CP11X_PCIE2_BASE f2640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Marvell International Ltd.
*
* Device tree for the CN9131-DB board.
*/
#include "cn9130-db.dts"
/ {
model = "Marvell Armada CN9131-DB";
compatible = "marvell,cn9131", "marvell,cn9130",
"marvell,armada-ap807-quad", "marvell,armada-ap807";
aliases {
gpio3 = &cp1_gpio1;
gpio4 = &cp1_gpio2;
ethernet3 = &cp1_eth0;
ethernet4 = &cp1_eth1;
};
cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&cp1_xhci0_vbus_pins>;
regulator-name = "cp1-xhci0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
};
cp1_usb3_0_phy0: cp1_usb3_phy0 {
compatible = "usb-nop-xceiv";
vcc-supply = <&cp1_reg_usb3_vbus0>;
};
cp1_sfp_eth1: sfp-eth1 {
compatible = "sff,sfp";
i2c-bus = <&cp1_i2c0>;
los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cp1_sfp_pins>;
/*
* SFP cages are unconnected on early PCBs because of an the I2C
* lanes not being connected. Prevent the port for being
* unusable by disabling the SFP node.
*/
status = "disabled";
};
};
/*
* Instantiate the first slave CP115
*/
#define CP11X_NAME cp1
#define CP11X_BASE f4000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f4600000
#define CP11X_PCIE1_BASE f4620000
#define CP11X_PCIE2_BASE f4640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
&cp1_crypto {
status = "disabled";
};
&cp1_ethernet {
status = "okay";
};
/* CON50 */
&cp1_eth0 {
status = "disabled";
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cp1_comphy4 0>;
managed = "in-band-status";
sfp = <&cp1_sfp_eth1>;
};
&cp1_gpio1 {
status = "okay";
};
&cp1_gpio2 {
status = "okay";
};
&cp1_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp1_i2c0_pins>;
clock-frequency = <100000>;
};
/* CON40 */
&cp1_pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&cp1_pcie_reset_pins>;
num-lanes = <2>;
num-viewport = <8>;
marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
status = "okay";
/* Generic PHY, providing serdes lanes */
phys = <&cp1_comphy0 0
&cp1_comphy1 0>;
};
&cp1_sata0 {
status = "okay";
/* CON32 */
sata-port@1 {
/* Generic PHY, providing serdes lanes */
phys = <&cp1_comphy5 1>;
};
};
/* U24 */
&cp1_spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp1_spi0_pins>;
reg = <0x700680 0x50>;
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
/* On-board MUX does not allow higher frequencies */
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot-1";
reg = <0x0 0x200000>;
};
partition@400000 {
label = "Filesystem-1";
reg = <0x200000 0xe00000>;
};
};
};
};
&cp1_syscon0 {
cp1_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp1_i2c0_pins: cp1-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp1_spi0_pins: cp1-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
marvell,pins = "mpp3";
marvell,function = "gpio";
};
cp1_sfp_pins: sfp-pins {
marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
marvell,function = "gpio";
};
cp1_pcie_reset_pins: cp1-pcie-reset-pins {
marvell,pins = "mpp0";
marvell,function = "gpio";
};
};
};
/* CON58 */
&cp1_usb3_1 {
status = "okay";
usb-phy = <&cp1_usb3_0_phy0>;
/* Generic PHY, providing serdes lanes */
phys = <&cp1_comphy3 1>;
phy-names = "usb";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Marvell International Ltd.
*
* Device tree for the CN9132-DB board.
*/
#include "cn9131-db.dts"
/ {
model = "Marvell Armada CN9132-DB";
compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
"marvell,armada-ap807-quad", "marvell,armada-ap807";
aliases {
gpio5 = &cp2_gpio1;
gpio6 = &cp2_gpio2;
ethernet5 = &cp2_eth0;
};
cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
compatible = "regulator-fixed";
regulator-name = "cp2-xhci0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
};
cp2_usb3_0_phy0: cp2_usb3_phy0 {
compatible = "usb-nop-xceiv";
vcc-supply = <&cp2_reg_usb3_vbus0>;
};
cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
compatible = "regulator-fixed";
regulator-name = "cp2-xhci1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
};
cp2_usb3_0_phy1: cp2_usb3_phy1 {
compatible = "usb-nop-xceiv";
vcc-supply = <&cp2_reg_usb3_vbus1>;
};
cp2_reg_sd_vccq: cp2_sd_vccq@0 {
compatible = "regulator-gpio";
regulator-name = "cp2_sd_vcc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1 3300000 0x0>;
};
cp2_sfp_eth0: sfp-eth0 {
compatible = "sff,sfp";
i2c-bus = <&cp2_sfpp0_i2c>;
los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
/*
* SFP cages are unconnected on early PCBs because of an the I2C
* lanes not being connected. Prevent the port for being
* unusable by disabling the SFP node.
*/
status = "disabled";
};
};
/*
* Instantiate the second slave CP115
*/
#define CP11X_NAME cp2
#define CP11X_BASE f6000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f6600000
#define CP11X_PCIE1_BASE f6620000
#define CP11X_PCIE2_BASE f6640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
&cp2_crypto {
status = "disabled";
};
&cp2_ethernet {
status = "okay";
};
/* SLM-1521-V2, CON9 */
&cp2_eth0 {
status = "disabled";
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cp2_comphy4 0>;
managed = "in-band-status";
sfp = <&cp2_sfp_eth0>;
};
&cp2_gpio1 {
status = "okay";
};
&cp2_gpio2 {
status = "okay";
};
&cp2_i2c0 {
clock-frequency = <100000>;
/* SLM-1521-V2 - U3 */
i2c-mux@72 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x72>;
cp2_sfpp0_i2c: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* U12 */
cp2_module_expander1: pca9555@21 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
reg = <0x21>;
};
};
};
};
/* SLM-1521-V2, CON6 */
&cp2_pcie0 {
status = "okay";
num-lanes = <2>;
num-viewport = <8>;
/* Generic PHY, providing serdes lanes */
phys = <&cp2_comphy0 0
&cp2_comphy1 0>;
};
/* SLM-1521-V2, CON8 */
&cp2_pcie2 {
status = "okay";
num-lanes = <1>;
num-viewport = <8>;
/* Generic PHY, providing serdes lanes */
phys = <&cp2_comphy5 2>;
};
&cp2_sata0 {
status = "okay";
/* SLM-1521-V2, CON4 */
sata-port@0 {
/* Generic PHY, providing serdes lanes */
phys = <&cp2_comphy2 0>;
};
};
/* CON 2 on SLM-1683 - microSD */
&cp2_sdhci0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp2_sdhci_pins>;
bus-width = <4>;
cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
vqmmc-supply = <&cp2_reg_sd_vccq>;
};
&cp2_syscon0 {
cp2_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp2_i2c0_pins: cp2-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp2_sdhci_pins: cp2-sdhi-pins-0 {
marvell,pins = "mpp56", "mpp57", "mpp58",
"mpp59", "mpp60", "mpp61";
marvell,function = "sdio";
};
};
};
&cp2_usb3_0 {
status = "okay";
usb-phy = <&cp2_usb3_0_phy0>;
phy-names = "usb";
};
/* SLM-1521-V2, CON11 */
&cp2_usb3_1 {
status = "okay";
usb-phy = <&cp2_usb3_0_phy1>;
phy-names = "usb";
/* Generic PHY, providing serdes lanes */
phys = <&cp2_comphy3 1>;
};