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drm/amd/powerplay: move the function of is_dpm_running to asic file

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the function os is_dpm_running is aisc related function,
so move them to asic file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Kevin Wang 2019-03-05 15:42:16 +08:00 committed by Alex Deucher
parent 6d22f1aa92
commit e17980535b
3 changed files with 24 additions and 24 deletions
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4
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
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@ -474,6 +474,7 @@ struct pptable_funcs {
int (*set_cpu_power_state)(struct smu_context *smu); int (*set_cpu_power_state)(struct smu_context *smu);
int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures); int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
int (*get_ppfeature_status)(struct smu_context *smu, char *buf); int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
bool (*is_dpm_running)(struct smu_context *smu);
}; };
struct smu_funcs struct smu_funcs
@ -505,7 +506,6 @@ struct smu_funcs
int (*init_display)(struct smu_context *smu); int (*init_display)(struct smu_context *smu);
int (*set_allowed_mask)(struct smu_context *smu); int (*set_allowed_mask)(struct smu_context *smu);
int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
bool (*is_dpm_running)(struct smu_context *smu);
int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled); int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
int (*notify_display_change)(struct smu_context *smu); int (*notify_display_change)(struct smu_context *smu);
int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def); int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
@ -623,7 +623,7 @@ struct smu_funcs
#define smu_feature_get_enabled_mask(smu, mask, num) \ #define smu_feature_get_enabled_mask(smu, mask, num) \
((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0) ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
#define smu_is_dpm_running(smu) \ #define smu_is_dpm_running(smu) \
((smu)->funcs->is_dpm_running ? (smu)->funcs->is_dpm_running((smu)) : 0) ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
#define smu_feature_update_enable_state(smu, feature_id, enabled) \ #define smu_feature_update_enable_state(smu, feature_id, enabled) \
((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0) ((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
#define smu_notify_display_change(smu) \ #define smu_notify_display_change(smu) \

22
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
View File

@ -52,16 +52,6 @@ MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
#define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 #define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
#define SMU11_VOLTAGE_SCALE 4 #define SMU11_VOLTAGE_SCALE 4
#define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
FEATURE_DPM_GFXCLK_MASK | \
FEATURE_DPM_UCLK_MASK | \
FEATURE_DPM_SOCCLK_MASK | \
FEATURE_DPM_UVD_MASK | \
FEATURE_DPM_VCE_MASK | \
FEATURE_DPM_MP0CLK_MASK | \
FEATURE_DPM_LINK_MASK | \
FEATURE_DPM_DCEFCLK_MASK)
static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu, static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
uint16_t msg) uint16_t msg)
{ {
@ -848,17 +838,6 @@ static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
return ret; return ret;
} }
static bool smu_v11_0_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint32_t feature_mask[2];
unsigned long feature_enabled;
ret = smu_v11_0_get_enabled_mask(smu, feature_mask, 2);
feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32));
return !!(feature_enabled & SMC_DPM_FEATURE);
}
static int smu_v11_0_system_features_control(struct smu_context *smu, static int smu_v11_0_system_features_control(struct smu_context *smu,
bool en) bool en)
{ {
@ -1876,7 +1855,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
.init_display = smu_v11_0_init_display, .init_display = smu_v11_0_init_display,
.set_allowed_mask = smu_v11_0_set_allowed_mask, .set_allowed_mask = smu_v11_0_set_allowed_mask,
.get_enabled_mask = smu_v11_0_get_enabled_mask, .get_enabled_mask = smu_v11_0_get_enabled_mask,
.is_dpm_running = smu_v11_0_is_dpm_running,
.system_features_control = smu_v11_0_system_features_control, .system_features_control = smu_v11_0_system_features_control,
.update_feature_enable_state = smu_v11_0_update_feature_enable_state, .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
.notify_display_change = smu_v11_0_notify_display_change, .notify_display_change = smu_v11_0_notify_display_change,

22
drivers/gpu/drm/amd/powerplay/vega20_ppt.c
View File

@ -43,6 +43,16 @@
#define MSG_MAP(msg) \ #define MSG_MAP(msg) \
[SMU_MSG_##msg] = PPSMC_MSG_##msg [SMU_MSG_##msg] = PPSMC_MSG_##msg
#define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
FEATURE_DPM_GFXCLK_MASK | \
FEATURE_DPM_UCLK_MASK | \
FEATURE_DPM_SOCCLK_MASK | \
FEATURE_DPM_UVD_MASK | \
FEATURE_DPM_VCE_MASK | \
FEATURE_DPM_MP0CLK_MASK | \
FEATURE_DPM_LINK_MASK | \
FEATURE_DPM_DCEFCLK_MASK)
static int vega20_message_map[SMU_MSG_MAX_COUNT] = { static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage), MSG_MAP(TestMessage),
MSG_MAP(GetSmuVersion), MSG_MAP(GetSmuVersion),
@ -2794,6 +2804,17 @@ static int vega20_read_sensor(struct smu_context *smu,
return ret; return ret;
} }
static bool vega20_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint32_t feature_mask[2];
unsigned long feature_enabled;
ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32));
return !!(feature_enabled & SMC_DPM_FEATURE);
}
static const struct pptable_funcs vega20_ppt_funcs = { static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context, .alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table, .store_powerplay_table = vega20_store_powerplay_table,
@ -2832,6 +2853,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.get_profiling_clk_mask = vega20_get_profiling_clk_mask, .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
.set_ppfeature_status = vega20_set_ppfeature_status, .set_ppfeature_status = vega20_set_ppfeature_status,
.get_ppfeature_status = vega20_get_ppfeature_status, .get_ppfeature_status = vega20_get_ppfeature_status,
.is_dpm_running = vega20_is_dpm_running,
}; };
void vega20_set_ppt_funcs(struct smu_context *smu) void vega20_set_ppt_funcs(struct smu_context *smu)