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drm/amdgpu: enable gfxoff for sienna_cichlid
Enable GFXOFF for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3537,9 +3537,6 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
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if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
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adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
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break;
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case CHIP_SIENNA_CICHLID:
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adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
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break;
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default:
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break;
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}
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@ -7441,6 +7438,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
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case CHIP_NAVI10:
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case CHIP_NAVI14:
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case CHIP_NAVI12:
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case CHIP_SIENNA_CICHLID:
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amdgpu_gfx_off_ctrl(adev, enable);
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break;
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default:
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@ -341,6 +341,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
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if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
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*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
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if (adev->pm.pp_feature & PP_GFXOFF_MASK)
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*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
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if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
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*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
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@ -1353,6 +1353,7 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
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case CHIP_NAVI10:
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case CHIP_NAVI14:
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case CHIP_NAVI12:
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case CHIP_SIENNA_CICHLID:
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if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
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return 0;
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if (enable)
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