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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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mlxsw: reg: Add shared buffer configuration registers definitions
Add definitions of SBPR, SBCM, SBPM, SBMM and PBMC registers that are used to configure shared buffers. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jiri Pirko
David S. Miller
parent
b2e345f9a4
commit
e059436999
@ -1418,6 +1418,82 @@ static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port)
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mlxsw_reg_ppcnt_prio_tc_set(payload, 0);
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}
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/* PBMC - Port Buffer Management Control Register
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* ----------------------------------------------
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* The PBMC register configures and retrieves the port packet buffer
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* allocation for different Prios, and the Pause threshold management.
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*/
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#define MLXSW_REG_PBMC_ID 0x500C
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#define MLXSW_REG_PBMC_LEN 0x68
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static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
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.id = MLXSW_REG_PBMC_ID,
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.len = MLXSW_REG_PBMC_LEN,
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};
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/* reg_pbmc_local_port
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* Local port number.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
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/* reg_pbmc_xoff_timer_value
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* When device generates a pause frame, it uses this value as the pause
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* timer (time for the peer port to pause in quota-512 bit time).
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* Access: RW
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*/
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MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
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/* reg_pbmc_xoff_refresh
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* The time before a new pause frame should be sent to refresh the pause RW
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* state. Using the same units as xoff_timer_value above (in quota-512 bit
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* time).
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* Access: RW
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*/
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MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
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/* reg_pbmc_buf_lossy
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* The field indicates if the buffer is lossy.
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* 0 - Lossless
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* 1 - Lossy
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* Access: RW
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*/
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MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
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/* reg_pbmc_buf_epsb
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* Eligible for Port Shared buffer.
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* If epsb is set, packets assigned to buffer are allowed to insert the port
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* shared buffer.
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* When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
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* Access: RW
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*/
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MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
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/* reg_pbmc_buf_size
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* The part of the packet buffer array is allocated for the specific buffer.
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* Units are represented in cells.
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* Access: RW
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*/
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MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
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static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
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u16 xoff_timer_value, u16 xoff_refresh)
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{
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MLXSW_REG_ZERO(pbmc, payload);
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mlxsw_reg_pbmc_local_port_set(payload, local_port);
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mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
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mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
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}
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static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
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int buf_index,
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u16 size)
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{
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mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
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mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
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mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
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}
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/* PSPA - Port Switch Partition Allocation
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* ---------------------------------------
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* Controls the association of a port with a switch partition and enables
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@ -1697,6 +1773,269 @@ static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
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mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
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}
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/* SBPR - Shared Buffer Pools Register
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* -----------------------------------
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* The SBPR configures and retrieves the shared buffer pools and configuration.
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*/
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#define MLXSW_REG_SBPR_ID 0xB001
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#define MLXSW_REG_SBPR_LEN 0x14
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static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
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.id = MLXSW_REG_SBPR_ID,
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.len = MLXSW_REG_SBPR_LEN,
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};
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enum mlxsw_reg_sbpr_dir {
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MLXSW_REG_SBPR_DIR_INGRESS,
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MLXSW_REG_SBPR_DIR_EGRESS,
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};
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/* reg_sbpr_dir
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* Direction.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
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/* reg_sbpr_pool
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* Pool index.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
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/* reg_sbpr_size
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* Pool size in buffer cells.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
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enum mlxsw_reg_sbpr_mode {
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MLXSW_REG_SBPR_MODE_STATIC,
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MLXSW_REG_SBPR_MODE_DYNAMIC,
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};
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/* reg_sbpr_mode
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* Pool quota calculation mode.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
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static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
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enum mlxsw_reg_sbpr_dir dir,
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enum mlxsw_reg_sbpr_mode mode, u32 size)
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{
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MLXSW_REG_ZERO(sbpr, payload);
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mlxsw_reg_sbpr_pool_set(payload, pool);
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mlxsw_reg_sbpr_dir_set(payload, dir);
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mlxsw_reg_sbpr_mode_set(payload, mode);
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mlxsw_reg_sbpr_size_set(payload, size);
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}
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/* SBCM - Shared Buffer Class Management Register
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* ----------------------------------------------
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* The SBCM register configures and retrieves the shared buffer allocation
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* and configuration according to Port-PG, including the binding to pool
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* and definition of the associated quota.
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*/
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#define MLXSW_REG_SBCM_ID 0xB002
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#define MLXSW_REG_SBCM_LEN 0x28
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static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
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.id = MLXSW_REG_SBCM_ID,
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.len = MLXSW_REG_SBCM_LEN,
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};
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/* reg_sbcm_local_port
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* Local port number.
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* For Ingress: excludes CPU port and Router port
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* For Egress: excludes IP Router
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* Access: Index
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*/
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MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
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/* reg_sbcm_pg_buff
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* PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
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* For PG buffer: range is 0..cap_max_pg_buffers - 1
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* For traffic class: range is 0..cap_max_tclass - 1
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* Note that when traffic class is in MC aware mode then the traffic
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* classes which are MC aware cannot be configured.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
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enum mlxsw_reg_sbcm_dir {
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MLXSW_REG_SBCM_DIR_INGRESS,
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MLXSW_REG_SBCM_DIR_EGRESS,
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};
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/* reg_sbcm_dir
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* Direction.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
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/* reg_sbcm_min_buff
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* Minimum buffer size for the limiter, in cells.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
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/* reg_sbcm_max_buff
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* When the pool associated to the port-pg/tclass is configured to
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* static, Maximum buffer size for the limiter configured in cells.
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* When the pool associated to the port-pg/tclass is configured to
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* dynamic, the max_buff holds the "alpha" parameter, supporting
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* the following values:
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* 0: 0
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* i: (1/128)*2^(i-1), for i=1..14
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* 0xFF: Infinity
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* Access: RW
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*/
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MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
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/* reg_sbcm_pool
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* Association of the port-priority to a pool.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
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static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
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enum mlxsw_reg_sbcm_dir dir,
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u32 min_buff, u32 max_buff, u8 pool)
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{
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MLXSW_REG_ZERO(sbcm, payload);
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mlxsw_reg_sbcm_local_port_set(payload, local_port);
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mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
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mlxsw_reg_sbcm_dir_set(payload, dir);
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mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
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mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
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mlxsw_reg_sbcm_pool_set(payload, pool);
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}
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/* SBPM - Shared Buffer Class Management Register
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* ----------------------------------------------
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* The SBPM register configures and retrieves the shared buffer allocation
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* and configuration according to Port-Pool, including the definition
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* of the associated quota.
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*/
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#define MLXSW_REG_SBPM_ID 0xB003
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#define MLXSW_REG_SBPM_LEN 0x28
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static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
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.id = MLXSW_REG_SBPM_ID,
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.len = MLXSW_REG_SBPM_LEN,
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};
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/* reg_sbpm_local_port
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* Local port number.
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* For Ingress: excludes CPU port and Router port
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* For Egress: excludes IP Router
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* Access: Index
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*/
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MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
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/* reg_sbpm_pool
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* The pool associated to quota counting on the local_port.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
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enum mlxsw_reg_sbpm_dir {
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MLXSW_REG_SBPM_DIR_INGRESS,
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MLXSW_REG_SBPM_DIR_EGRESS,
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};
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/* reg_sbpm_dir
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* Direction.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
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/* reg_sbpm_min_buff
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* Minimum buffer size for the limiter, in cells.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
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/* reg_sbpm_max_buff
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* When the pool associated to the port-pg/tclass is configured to
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* static, Maximum buffer size for the limiter configured in cells.
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* When the pool associated to the port-pg/tclass is configured to
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* dynamic, the max_buff holds the "alpha" parameter, supporting
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* the following values:
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* 0: 0
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* i: (1/128)*2^(i-1), for i=1..14
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* 0xFF: Infinity
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* Access: RW
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*/
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MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
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static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
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enum mlxsw_reg_sbpm_dir dir,
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u32 min_buff, u32 max_buff)
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{
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MLXSW_REG_ZERO(sbpm, payload);
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mlxsw_reg_sbpm_local_port_set(payload, local_port);
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mlxsw_reg_sbpm_pool_set(payload, pool);
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mlxsw_reg_sbpm_dir_set(payload, dir);
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mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
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mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
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}
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/* SBMM - Shared Buffer Multicast Management Register
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* --------------------------------------------------
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* The SBMM register configures and retrieves the shared buffer allocation
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* and configuration for MC packets according to Switch-Priority, including
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* the binding to pool and definition of the associated quota.
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*/
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#define MLXSW_REG_SBMM_ID 0xB004
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#define MLXSW_REG_SBMM_LEN 0x28
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static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
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.id = MLXSW_REG_SBMM_ID,
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.len = MLXSW_REG_SBMM_LEN,
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};
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/* reg_sbmm_prio
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* Switch Priority.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
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/* reg_sbmm_min_buff
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* Minimum buffer size for the limiter, in cells.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
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/* reg_sbmm_max_buff
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* When the pool associated to the port-pg/tclass is configured to
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* static, Maximum buffer size for the limiter configured in cells.
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* When the pool associated to the port-pg/tclass is configured to
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* dynamic, the max_buff holds the "alpha" parameter, supporting
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* the following values:
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* 0: 0
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* i: (1/128)*2^(i-1), for i=1..14
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* 0xFF: Infinity
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* Access: RW
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*/
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MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
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/* reg_sbmm_pool
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* Association of the port-priority to a pool.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
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static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
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u32 max_buff, u8 pool)
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{
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MLXSW_REG_ZERO(sbmm, payload);
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mlxsw_reg_sbmm_prio_set(payload, prio);
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mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
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mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
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mlxsw_reg_sbmm_pool_set(payload, pool);
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}
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static inline const char *mlxsw_reg_id_str(u16 reg_id)
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{
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switch (reg_id) {
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@ -1734,12 +2073,22 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id)
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return "PAOS";
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case MLXSW_REG_PPCNT_ID:
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return "PPCNT";
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case MLXSW_REG_PBMC_ID:
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return "PBMC";
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case MLXSW_REG_PSPA_ID:
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return "PSPA";
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case MLXSW_REG_HTGT_ID:
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return "HTGT";
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case MLXSW_REG_HPKT_ID:
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return "HPKT";
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case MLXSW_REG_SBPR_ID:
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return "SBPR";
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case MLXSW_REG_SBCM_ID:
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return "SBCM";
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case MLXSW_REG_SBPM_ID:
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return "SBPM";
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case MLXSW_REG_SBMM_ID:
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return "SBMM";
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default:
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return "*UNKNOWN*";
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}
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