AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-20 14:39:21 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

dt-bindings: clock: Convert i.MX8QXP LPCG to json-schema

Browse Source 
Convert the i.MX8QXP LPCG binding to DT schema format using json-schema.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
[robh: add additionalProperties]
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Anson Huang 2020-05-29 14:21:39 +08:00 committed by Rob Herring
parent df8cad689e
commit dff49d55e0
2 changed files with 73 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

51
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
View File

@ -1,51 +0,0 @@
* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
The Low-Power Clock Gate (LPCG) modules contain a local programming
model to control the clock gates for the peripherals. An LPCG module
is used to locally gate the clocks for the associated peripheral.
Note:
This level of clock gating is provided after the clocks are generated
by the SCU resources and clock controls. Thus even if the clock is
enabled by these control bits, it might still not be running based
on the base resource.
Required properties:
- compatible: Should be one of:
"fsl,imx8qxp-lpcg-adma",
"fsl,imx8qxp-lpcg-conn",
"fsl,imx8qxp-lpcg-dc",
"fsl,imx8qxp-lpcg-dsp",
"fsl,imx8qxp-lpcg-gpu",
"fsl,imx8qxp-lpcg-hsio",
"fsl,imx8qxp-lpcg-img",
"fsl,imx8qxp-lpcg-lsio",
"fsl,imx8qxp-lpcg-vpu"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell.
See the full list of clock IDs from:
include/dt-bindings/clock/imx8qxp-clock.h
Examples:
#include <dt-bindings/clock/imx8qxp-clock.h>
conn_lpcg: clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg-conn";
reg = <0x5b200000 0xb0000>;
#clock-cells = <1>;
};
usdhc1: mmc@5b010000 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>,
<&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>,
<&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>;
clock-names = "ipg", "per", "ahb";
};

73
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml Normal file
View File

@ -0,0 +1,73 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
maintainers:
- Aisheng Dong <aisheng.dong@nxp.com>
description: |
The Low-Power Clock Gate (LPCG) modules contain a local programming
model to control the clock gates for the peripherals. An LPCG module
is used to locally gate the clocks for the associated peripheral.
This level of clock gating is provided after the clocks are generated
by the SCU resources and clock controls. Thus even if the clock is
enabled by these control bits, it might still not be running based
on the base resource.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See the full list of clock IDs from:
include/dt-bindings/clock/imx8-clock.h
properties:
compatible:
enum:
- fsl,imx8qxp-lpcg-adma
- fsl,imx8qxp-lpcg-conn
- fsl,imx8qxp-lpcg-dc
- fsl,imx8qxp-lpcg-dsp
- fsl,imx8qxp-lpcg-gpu
- fsl,imx8qxp-lpcg-hsio
- fsl,imx8qxp-lpcg-img
- fsl,imx8qxp-lpcg-lsio
- fsl,imx8qxp-lpcg-vpu
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg-conn";
reg = <0x5b200000 0xb0000>;
#clock-cells = <1>;
};
mmc@5b010000 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_0>;
};