mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 20:45:31 +07:00
Merge branch 'dsa-global-cosmetics'
Vivien Didelot says:
====================
net: dsa: mv88e6xxx: Global (1) cosmetics
The Global (1) internal SMI device of Marvell switches is a set of
registers providing support to different units for MAC addresses (ATU),
VLANs (VTU), PHY polling (PPU), etc.
Chips (like 88E6060) may use a different address for it, or have
subtleties in the units (e.g. different number of databases, changing
how registers must be accessed), making it hard to maintain properly.
This patchset is a first step to polish the Global (1) support, with no
functional changes though. Here's basically what it does:
- add helpers to access Global1 registers (same for Global2)
- remove a few family checks (VTU/STU FID registers)
- s/mv88e6xxx_vtu_stu_entry/mv88e6xxx_vtu_entry/
- add a per-chip mv88e6xxx_ops structure of function pointers:
struct mv88e6xxx_ops {
int (*get_eeprom)(struct mv88e6xxx_chip *chip,
struct ethtool_eeprom *eeprom, u8 *data);
int (*set_eeprom)(struct mv88e6xxx_chip *chip,
struct ethtool_eeprom *eeprom, u8 *data);
int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
int (*phy_read)(struct mv88e6xxx_chip *chip, int addr, int reg,
u16 *val);
int (*phy_write)(struct mv88e6xxx_chip *chip, int addr, int reg,
u16 val);
};
Future patchsets will add ATU/VTU ops, software reset, etc.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
df90a49704
@ -1,3 +1,4 @@
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obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx.o
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mv88e6xxx-objs := chip.o
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mv88e6xxx-objs += global1.o
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mv88e6xxx-$(CONFIG_NET_DSA_MV88E6XXX_GLOBAL2) += global2.o
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File diff suppressed because it is too large
Load Diff
34
drivers/net/dsa/mv88e6xxx/global1.c
Normal file
34
drivers/net/dsa/mv88e6xxx/global1.c
Normal file
@ -0,0 +1,34 @@
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/*
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* Marvell 88E6xxx Switch Global (1) Registers support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "mv88e6xxx.h"
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#include "global1.h"
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int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
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{
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int addr = chip->info->global1_addr;
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return mv88e6xxx_read(chip, addr, reg, val);
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}
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int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
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{
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int addr = chip->info->global1_addr;
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return mv88e6xxx_write(chip, addr, reg, val);
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}
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int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
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{
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return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask);
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}
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23
drivers/net/dsa/mv88e6xxx/global1.h
Normal file
23
drivers/net/dsa/mv88e6xxx/global1.h
Normal file
@ -0,0 +1,23 @@
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/*
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* Marvell 88E6xxx Switch Global (1) Registers support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _MV88E6XXX_GLOBAL1_H
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#define _MV88E6XXX_GLOBAL1_H
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#include "mv88e6xxx.h"
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int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
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int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
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int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
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#endif /* _MV88E6XXX_GLOBAL1_H */
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@ -14,6 +14,28 @@
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#include "mv88e6xxx.h"
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#include "global2.h"
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#define ADDR_GLOBAL2 0x1c
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static int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
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{
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return mv88e6xxx_read(chip, ADDR_GLOBAL2, reg, val);
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}
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static int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
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{
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return mv88e6xxx_write(chip, ADDR_GLOBAL2, reg, val);
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}
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static int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
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{
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return mv88e6xxx_update(chip, ADDR_GLOBAL2, reg, update);
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}
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static int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
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{
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return mv88e6xxx_wait(chip, ADDR_GLOBAL2, reg, mask);
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}
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/* Offset 0x06: Device Mapping Table register */
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static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
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@ -21,7 +43,7 @@ static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
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{
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u16 val = (target << 8) | (port & 0xf);
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return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
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return mv88e6xxx_g2_update(chip, GLOBAL2_DEVICE_MAPPING, val);
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}
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static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
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@ -52,13 +74,13 @@ static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
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static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
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bool hask, u16 mask)
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{
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const u16 port_mask = BIT(chip->info->num_ports) - 1;
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const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
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u16 val = (num << 12) | (mask & port_mask);
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if (hask)
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val |= GLOBAL2_TRUNK_MASK_HASK;
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return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
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return mv88e6xxx_g2_update(chip, GLOBAL2_TRUNK_MASK, val);
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}
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/* Offset 0x08: Trunk Mapping Table register */
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@ -66,15 +88,15 @@ static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
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static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
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u16 map)
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{
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const u16 port_mask = BIT(chip->info->num_ports) - 1;
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const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
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u16 val = (id << 11) | (map & port_mask);
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return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
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return mv88e6xxx_g2_update(chip, GLOBAL2_TRUNK_MAPPING, val);
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}
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static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
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{
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const u16 port_mask = BIT(chip->info->num_ports) - 1;
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const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
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int i, err;
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/* Clear all eight possible Trunk Mask vectors */
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@ -103,16 +125,16 @@ static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
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int port, err;
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/* Init all Ingress Rate Limit resources of all ports */
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for (port = 0; port < chip->info->num_ports; ++port) {
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for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
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/* XXX newer chips (like 88E6390) have different 2-bit ops */
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
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err = mv88e6xxx_g2_write(chip, GLOBAL2_IRL_CMD,
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GLOBAL2_IRL_CMD_OP_INIT_ALL |
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(port << 8));
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if (err)
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break;
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/* Wait for the operation to complete */
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err = mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
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err = mv88e6xxx_g2_wait(chip, GLOBAL2_IRL_CMD,
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GLOBAL2_IRL_CMD_BUSY);
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if (err)
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break;
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@ -128,7 +150,7 @@ static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
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{
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u16 val = (pointer << 8) | data;
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return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
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return mv88e6xxx_g2_update(chip, GLOBAL2_SWITCH_MAC, val);
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}
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int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
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@ -151,7 +173,7 @@ static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
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{
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u16 val = (pointer << 8) | (data & 0x7);
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return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
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return mv88e6xxx_g2_update(chip, GLOBAL2_PRIO_OVERRIDE, val);
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}
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static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
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@ -174,7 +196,7 @@ static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
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static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
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return mv88e6xxx_g2_wait(chip, GLOBAL2_EEPROM_CMD,
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GLOBAL2_EEPROM_CMD_BUSY |
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GLOBAL2_EEPROM_CMD_RUNNING);
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}
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@ -183,7 +205,7 @@ static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
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{
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int err;
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
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err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_CMD, cmd);
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if (err)
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return err;
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@ -204,7 +226,7 @@ static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
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if (err)
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return err;
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return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
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return mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_DATA, data);
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}
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static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
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@ -217,7 +239,7 @@ static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
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if (err)
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return err;
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
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err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_DATA, data);
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if (err)
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return err;
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@ -283,7 +305,7 @@ int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
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int err;
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/* Ensure the RO WriteEn bit is set */
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err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
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err = mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_CMD, &val);
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if (err)
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return err;
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@ -346,7 +368,7 @@ int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
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static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD,
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return mv88e6xxx_g2_wait(chip, GLOBAL2_SMI_PHY_CMD,
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GLOBAL2_SMI_PHY_CMD_BUSY);
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}
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@ -354,7 +376,7 @@ static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
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{
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int err;
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD, cmd);
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err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_CMD, cmd);
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if (err)
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return err;
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@ -375,7 +397,7 @@ int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr, int reg,
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if (err)
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return err;
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return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
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return mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val);
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}
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int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr, int reg,
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@ -388,7 +410,7 @@ int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr, int reg,
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if (err)
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return err;
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
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err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, val);
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if (err)
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return err;
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@ -404,8 +426,7 @@ int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
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/* Consider the frames with reserved multicast destination
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* addresses matching 01:80:c2:00:00:2x as MGMT.
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*/
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
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0xffff);
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err = mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_2X, 0xffff);
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if (err)
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return err;
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}
|
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@ -414,8 +435,7 @@ int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
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/* Consider the frames with reserved multicast destination
|
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* addresses matching 01:80:c2:00:00:0x as MGMT.
|
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*/
|
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
|
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0xffff);
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err = mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_0X, 0xffff);
|
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if (err)
|
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return err;
|
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}
|
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@ -429,7 +449,7 @@ int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
|
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
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mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
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reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
|
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
|
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err = mv88e6xxx_g2_write(chip, GLOBAL2_SWITCH_MGMT, reg);
|
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if (err)
|
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return err;
|
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|
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@ -454,7 +474,7 @@ int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
|
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|
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
|
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/* Initialize Cross-chip Port VLAN Table to reset defaults */
|
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err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
|
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err = mv88e6xxx_g2_write(chip, GLOBAL2_PVT_ADDR,
|
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GLOBAL2_PVT_ADDR_OP_INIT_ONES);
|
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if (err)
|
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return err;
|
||||
|
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@ -159,7 +159,6 @@
|
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#define PORT_TAG_REGMAP_0123 0x18
|
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#define PORT_TAG_REGMAP_4567 0x19
|
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|
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#define REG_GLOBAL 0x1b
|
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#define GLOBAL_STATUS 0x00
|
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#define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
|
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/* Two bits for 6165, 6185 etc */
|
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@ -171,8 +170,8 @@
|
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#define GLOBAL_MAC_01 0x01
|
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#define GLOBAL_MAC_23 0x02
|
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#define GLOBAL_MAC_45 0x03
|
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#define GLOBAL_ATU_FID 0x01 /* 6097 6165 6351 6352 */
|
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#define GLOBAL_VTU_FID 0x02 /* 6097 6165 6351 6352 */
|
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#define GLOBAL_ATU_FID 0x01
|
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#define GLOBAL_VTU_FID 0x02
|
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#define GLOBAL_VTU_FID_MASK 0xfff
|
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#define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */
|
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#define GLOBAL_VTU_SID_MASK 0x3f
|
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@ -277,7 +276,6 @@
|
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#define GLOBAL_STATS_COUNTER_32 0x1e
|
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#define GLOBAL_STATS_COUNTER_01 0x1f
|
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|
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#define REG_GLOBAL2 0x1c
|
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#define GLOBAL2_INT_SOURCE 0x00
|
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#define GLOBAL2_INT_MASK 0x01
|
||||
#define GLOBAL2_MGMT_EN_2X 0x02
|
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@ -410,6 +408,11 @@ enum mv88e6xxx_cap {
|
||||
*/
|
||||
MV88E6XXX_CAP_SERDES,
|
||||
|
||||
/* Switch Global (1) Registers.
|
||||
*/
|
||||
MV88E6XXX_CAP_G1_ATU_FID, /* (0x01) ATU FID Register */
|
||||
MV88E6XXX_CAP_G1_VTU_FID, /* (0x02) VTU FID Register */
|
||||
|
||||
/* Switch Global 2 Registers.
|
||||
* The device contains a second set of global 16-bit registers.
|
||||
*/
|
||||
@ -420,12 +423,7 @@ enum mv88e6xxx_cap {
|
||||
MV88E6XXX_CAP_G2_IRL_DATA, /* (0x0a) Ingress Rate Data */
|
||||
MV88E6XXX_CAP_G2_PVT_ADDR, /* (0x0b) Cross Chip Port VLAN Addr */
|
||||
MV88E6XXX_CAP_G2_PVT_DATA, /* (0x0c) Cross Chip Port VLAN Data */
|
||||
MV88E6XXX_CAP_G2_SWITCH_MAC, /* (0x0d) Switch MAC/WoL/WoF */
|
||||
MV88E6XXX_CAP_G2_POT, /* (0x0f) Priority Override Table */
|
||||
MV88E6XXX_CAP_G2_EEPROM_CMD, /* (0x14) EEPROM Command */
|
||||
MV88E6XXX_CAP_G2_EEPROM_DATA, /* (0x15) EEPROM Data */
|
||||
MV88E6XXX_CAP_G2_SMI_PHY_CMD, /* (0x18) SMI PHY Command */
|
||||
MV88E6XXX_CAP_G2_SMI_PHY_DATA, /* (0x19) SMI PHY Data */
|
||||
|
||||
/* PHY Polling Unit.
|
||||
* See GLOBAL_CONTROL_PPU_ENABLE and GLOBAL_STATUS_PPU_POLLING.
|
||||
@ -462,6 +460,9 @@ enum mv88e6xxx_cap {
|
||||
|
||||
#define MV88E6XXX_FLAG_SERDES BIT_ULL(MV88E6XXX_CAP_SERDES)
|
||||
|
||||
#define MV88E6XXX_FLAG_G1_ATU_FID BIT_ULL(MV88E6XXX_CAP_G1_ATU_FID)
|
||||
#define MV88E6XXX_FLAG_G1_VTU_FID BIT_ULL(MV88E6XXX_CAP_G1_VTU_FID)
|
||||
|
||||
#define MV88E6XXX_FLAG_GLOBAL2 BIT_ULL(MV88E6XXX_CAP_GLOBAL2)
|
||||
#define MV88E6XXX_FLAG_G2_MGMT_EN_2X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_2X)
|
||||
#define MV88E6XXX_FLAG_G2_MGMT_EN_0X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_0X)
|
||||
@ -469,12 +470,7 @@ enum mv88e6xxx_cap {
|
||||
#define MV88E6XXX_FLAG_G2_IRL_DATA BIT_ULL(MV88E6XXX_CAP_G2_IRL_DATA)
|
||||
#define MV88E6XXX_FLAG_G2_PVT_ADDR BIT_ULL(MV88E6XXX_CAP_G2_PVT_ADDR)
|
||||
#define MV88E6XXX_FLAG_G2_PVT_DATA BIT_ULL(MV88E6XXX_CAP_G2_PVT_DATA)
|
||||
#define MV88E6XXX_FLAG_G2_SWITCH_MAC BIT_ULL(MV88E6XXX_CAP_G2_SWITCH_MAC)
|
||||
#define MV88E6XXX_FLAG_G2_POT BIT_ULL(MV88E6XXX_CAP_G2_POT)
|
||||
#define MV88E6XXX_FLAG_G2_EEPROM_CMD BIT_ULL(MV88E6XXX_CAP_G2_EEPROM_CMD)
|
||||
#define MV88E6XXX_FLAG_G2_EEPROM_DATA BIT_ULL(MV88E6XXX_CAP_G2_EEPROM_DATA)
|
||||
#define MV88E6XXX_FLAG_G2_SMI_PHY_CMD BIT_ULL(MV88E6XXX_CAP_G2_SMI_PHY_CMD)
|
||||
#define MV88E6XXX_FLAG_G2_SMI_PHY_DATA BIT_ULL(MV88E6XXX_CAP_G2_SMI_PHY_DATA)
|
||||
|
||||
#define MV88E6XXX_FLAG_PPU BIT_ULL(MV88E6XXX_CAP_PPU)
|
||||
#define MV88E6XXX_FLAG_PPU_ACTIVE BIT_ULL(MV88E6XXX_CAP_PPU_ACTIVE)
|
||||
@ -483,11 +479,6 @@ enum mv88e6xxx_cap {
|
||||
#define MV88E6XXX_FLAG_TEMP_LIMIT BIT_ULL(MV88E6XXX_CAP_TEMP_LIMIT)
|
||||
#define MV88E6XXX_FLAG_VTU BIT_ULL(MV88E6XXX_CAP_VTU)
|
||||
|
||||
/* EEPROM Programming via Global2 with 16-bit data */
|
||||
#define MV88E6XXX_FLAGS_EEPROM16 \
|
||||
(MV88E6XXX_FLAG_G2_EEPROM_CMD | \
|
||||
MV88E6XXX_FLAG_G2_EEPROM_DATA)
|
||||
|
||||
/* Ingress Rate Limit unit */
|
||||
#define MV88E6XXX_FLAGS_IRL \
|
||||
(MV88E6XXX_FLAG_G2_IRL_CMD | \
|
||||
@ -508,11 +499,6 @@ enum mv88e6xxx_cap {
|
||||
(MV88E6XXX_FLAG_PHY_PAGE | \
|
||||
MV88E6XXX_FLAG_SERDES)
|
||||
|
||||
/* Indirect PHY access via Global2 SMI PHY registers */
|
||||
#define MV88E6XXX_FLAGS_SMI_PHY \
|
||||
(MV88E6XXX_FLAG_G2_SMI_PHY_CMD |\
|
||||
MV88E6XXX_FLAG_G2_SMI_PHY_DATA)
|
||||
|
||||
#define MV88E6XXX_FLAGS_FAMILY_6095 \
|
||||
(MV88E6XXX_FLAG_GLOBAL2 | \
|
||||
MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
|
||||
@ -521,7 +507,9 @@ enum mv88e6xxx_cap {
|
||||
MV88E6XXX_FLAGS_MULTI_CHIP)
|
||||
|
||||
#define MV88E6XXX_FLAGS_FAMILY_6097 \
|
||||
(MV88E6XXX_FLAG_GLOBAL2 | \
|
||||
(MV88E6XXX_FLAG_G1_ATU_FID | \
|
||||
MV88E6XXX_FLAG_G1_VTU_FID | \
|
||||
MV88E6XXX_FLAG_GLOBAL2 | \
|
||||
MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
|
||||
MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
|
||||
MV88E6XXX_FLAG_G2_POT | \
|
||||
@ -533,10 +521,11 @@ enum mv88e6xxx_cap {
|
||||
MV88E6XXX_FLAGS_PVT)
|
||||
|
||||
#define MV88E6XXX_FLAGS_FAMILY_6165 \
|
||||
(MV88E6XXX_FLAG_GLOBAL2 | \
|
||||
(MV88E6XXX_FLAG_G1_ATU_FID | \
|
||||
MV88E6XXX_FLAG_G1_VTU_FID | \
|
||||
MV88E6XXX_FLAG_GLOBAL2 | \
|
||||
MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
|
||||
MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
|
||||
MV88E6XXX_FLAG_G2_SWITCH_MAC | \
|
||||
MV88E6XXX_FLAG_G2_POT | \
|
||||
MV88E6XXX_FLAG_STU | \
|
||||
MV88E6XXX_FLAG_TEMP | \
|
||||
@ -558,24 +547,22 @@ enum mv88e6xxx_cap {
|
||||
MV88E6XXX_FLAG_GLOBAL2 | \
|
||||
MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
|
||||
MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
|
||||
MV88E6XXX_FLAG_G2_SWITCH_MAC | \
|
||||
MV88E6XXX_FLAG_G2_POT | \
|
||||
MV88E6XXX_FLAG_PPU_ACTIVE | \
|
||||
MV88E6XXX_FLAG_TEMP | \
|
||||
MV88E6XXX_FLAG_TEMP_LIMIT | \
|
||||
MV88E6XXX_FLAG_VTU | \
|
||||
MV88E6XXX_FLAGS_EEPROM16 | \
|
||||
MV88E6XXX_FLAGS_IRL | \
|
||||
MV88E6XXX_FLAGS_MULTI_CHIP | \
|
||||
MV88E6XXX_FLAGS_PVT | \
|
||||
MV88E6XXX_FLAGS_SMI_PHY)
|
||||
MV88E6XXX_FLAGS_PVT)
|
||||
|
||||
#define MV88E6XXX_FLAGS_FAMILY_6351 \
|
||||
(MV88E6XXX_FLAG_EDSA | \
|
||||
MV88E6XXX_FLAG_G1_ATU_FID | \
|
||||
MV88E6XXX_FLAG_G1_VTU_FID | \
|
||||
MV88E6XXX_FLAG_GLOBAL2 | \
|
||||
MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
|
||||
MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
|
||||
MV88E6XXX_FLAG_G2_SWITCH_MAC | \
|
||||
MV88E6XXX_FLAG_G2_POT | \
|
||||
MV88E6XXX_FLAG_PPU_ACTIVE | \
|
||||
MV88E6XXX_FLAG_STU | \
|
||||
@ -583,28 +570,28 @@ enum mv88e6xxx_cap {
|
||||
MV88E6XXX_FLAG_VTU | \
|
||||
MV88E6XXX_FLAGS_IRL | \
|
||||
MV88E6XXX_FLAGS_MULTI_CHIP | \
|
||||
MV88E6XXX_FLAGS_PVT | \
|
||||
MV88E6XXX_FLAGS_SMI_PHY)
|
||||
MV88E6XXX_FLAGS_PVT)
|
||||
|
||||
#define MV88E6XXX_FLAGS_FAMILY_6352 \
|
||||
(MV88E6XXX_FLAG_EDSA | \
|
||||
MV88E6XXX_FLAG_EEE | \
|
||||
MV88E6XXX_FLAG_G1_ATU_FID | \
|
||||
MV88E6XXX_FLAG_G1_VTU_FID | \
|
||||
MV88E6XXX_FLAG_GLOBAL2 | \
|
||||
MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
|
||||
MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
|
||||
MV88E6XXX_FLAG_G2_SWITCH_MAC | \
|
||||
MV88E6XXX_FLAG_G2_POT | \
|
||||
MV88E6XXX_FLAG_PPU_ACTIVE | \
|
||||
MV88E6XXX_FLAG_STU | \
|
||||
MV88E6XXX_FLAG_TEMP | \
|
||||
MV88E6XXX_FLAG_TEMP_LIMIT | \
|
||||
MV88E6XXX_FLAG_VTU | \
|
||||
MV88E6XXX_FLAGS_EEPROM16 | \
|
||||
MV88E6XXX_FLAGS_IRL | \
|
||||
MV88E6XXX_FLAGS_MULTI_CHIP | \
|
||||
MV88E6XXX_FLAGS_PVT | \
|
||||
MV88E6XXX_FLAGS_SERDES | \
|
||||
MV88E6XXX_FLAGS_SMI_PHY)
|
||||
MV88E6XXX_FLAGS_SERDES)
|
||||
|
||||
struct mv88e6xxx_ops;
|
||||
|
||||
struct mv88e6xxx_info {
|
||||
enum mv88e6xxx_family family;
|
||||
@ -613,8 +600,10 @@ struct mv88e6xxx_info {
|
||||
unsigned int num_databases;
|
||||
unsigned int num_ports;
|
||||
unsigned int port_base_addr;
|
||||
unsigned int global1_addr;
|
||||
unsigned int age_time_coeff;
|
||||
unsigned long long flags;
|
||||
const struct mv88e6xxx_ops *ops;
|
||||
};
|
||||
|
||||
struct mv88e6xxx_atu_entry {
|
||||
@ -625,18 +614,15 @@ struct mv88e6xxx_atu_entry {
|
||||
u8 mac[ETH_ALEN];
|
||||
};
|
||||
|
||||
struct mv88e6xxx_vtu_stu_entry {
|
||||
/* VTU only */
|
||||
struct mv88e6xxx_vtu_entry {
|
||||
u16 vid;
|
||||
u16 fid;
|
||||
|
||||
/* VTU and STU */
|
||||
u8 sid;
|
||||
bool valid;
|
||||
u8 data[DSA_MAX_PORTS];
|
||||
};
|
||||
|
||||
struct mv88e6xxx_ops;
|
||||
struct mv88e6xxx_bus_ops;
|
||||
|
||||
struct mv88e6xxx_priv_port {
|
||||
struct net_device *bridge_dev;
|
||||
@ -657,14 +643,14 @@ struct mv88e6xxx_chip {
|
||||
/* The MII bus and the address on the bus that is used to
|
||||
* communication with the switch
|
||||
*/
|
||||
const struct mv88e6xxx_ops *smi_ops;
|
||||
const struct mv88e6xxx_bus_ops *smi_ops;
|
||||
struct mii_bus *bus;
|
||||
int sw_addr;
|
||||
|
||||
/* Handles automatic disabling and re-enabling of the PHY
|
||||
* polling unit.
|
||||
*/
|
||||
const struct mv88e6xxx_ops *phy_ops;
|
||||
const struct mv88e6xxx_bus_ops *phy_ops;
|
||||
struct mutex ppu_mutex;
|
||||
int ppu_disabled;
|
||||
struct work_struct ppu_work;
|
||||
@ -693,11 +679,25 @@ struct mv88e6xxx_chip {
|
||||
struct mii_bus *mdio_bus;
|
||||
};
|
||||
|
||||
struct mv88e6xxx_ops {
|
||||
struct mv88e6xxx_bus_ops {
|
||||
int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
|
||||
int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
|
||||
};
|
||||
|
||||
struct mv88e6xxx_ops {
|
||||
int (*get_eeprom)(struct mv88e6xxx_chip *chip,
|
||||
struct ethtool_eeprom *eeprom, u8 *data);
|
||||
int (*set_eeprom)(struct mv88e6xxx_chip *chip,
|
||||
struct ethtool_eeprom *eeprom, u8 *data);
|
||||
|
||||
int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
|
||||
|
||||
int (*phy_read)(struct mv88e6xxx_chip *chip, int addr, int reg,
|
||||
u16 *val);
|
||||
int (*phy_write)(struct mv88e6xxx_chip *chip, int addr, int reg,
|
||||
u16 val);
|
||||
};
|
||||
|
||||
enum stat_type {
|
||||
BANK0,
|
||||
BANK1,
|
||||
@ -717,6 +717,16 @@ static inline bool mv88e6xxx_has(struct mv88e6xxx_chip *chip,
|
||||
return (chip->info->flags & flags) == flags;
|
||||
}
|
||||
|
||||
static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
|
||||
{
|
||||
return chip->info->num_databases;
|
||||
}
|
||||
|
||||
static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
|
||||
{
|
||||
return chip->info->num_ports;
|
||||
}
|
||||
|
||||
int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
|
||||
int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
|
||||
int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user