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ARM: dts: cm-t3x: add NAND support
CM-T3517, CM-T3530 and CM-T3730 features NAND storage chip connected to GPMC bus. Add GPMC DT entry into the root DT file omap3-cm-t3x.dtsi, common for all three modules. NAND timings are calculated to be safe for CM-T3x devices as it works now in non DT boot (in this case the timings are updated by U-Boot). Update GPMC ranges in boards DT files to include all connected devices. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -259,3 +259,61 @@ &mcbsp2 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcbsp2_pins>;
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};
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&gpmc {
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ranges = <0 0 0x00000000 0x01000000>;
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nand@0,0 {
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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nand-bus-width = <8>;
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gpmc,device-width = <1>;
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ti,nand-ecc-opt = "sw";
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <120>;
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gpmc,cs-wr-off-ns = <120>;
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gpmc,adv-on-ns = <0>;
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gpmc,adv-rd-off-ns = <120>;
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gpmc,adv-wr-off-ns = <120>;
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gpmc,we-on-ns = <6>;
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gpmc,we-off-ns = <90>;
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gpmc,oe-on-ns = <6>;
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gpmc,oe-off-ns = <90>;
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gpmc,page-burst-access-ns = <6>;
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gpmc,access-ns = <72>;
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gpmc,cycle2cycle-delay-ns = <60>;
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gpmc,rd-cycle-ns = <120>;
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gpmc,wr-cycle-ns = <120>;
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gpmc,wr-access-ns = <186>;
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gpmc,wr-data-mux-bus-ns = <90>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "xloader";
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reg = <0 0x80000>;
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};
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partition@0x80000 {
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label = "uboot";
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reg = <0x80000 0x1e0000>;
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};
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partition@0x260000 {
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label = "uboot environment";
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reg = <0x260000 0x40000>;
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};
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partition@0x2a0000 {
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label = "linux";
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reg = <0x2a0000 0x400000>;
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};
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partition@0x6a0000 {
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label = "rootfs";
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reg = <0x6a0000 0x1f880000>;
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};
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};
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};
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@ -50,7 +50,8 @@ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0
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#include "omap-gpmc-smsc911x.dtsi"
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&gpmc {
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ranges = <5 0 0x2c000000 0x01000000>;
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ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
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<0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
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smsc1: ethernet@gpmc {
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compatible = "smsc,lan9221", "smsc,lan9115";
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@ -69,3 +69,7 @@ dpi_out: endpoint {
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};
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};
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&gpmc {
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ranges = <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */
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<0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
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};
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@ -26,14 +26,10 @@ OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35
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};
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};
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/*
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* The following ranges correspond to SMSC9x eth chips on CM-T3530 CoM and
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* SB-T35 baseboard respectively.
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* This setting includes both chips in SBC-T3530 board device tree.
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*/
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&gpmc {
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ranges = <5 0 0x2c000000 0x01000000>,
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<4 0 0x2d000000 0x01000000>;
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ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
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<4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */
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<0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
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};
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&mmc1 {
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@ -27,8 +27,9 @@ OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35
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};
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&gpmc {
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ranges = <5 0 0x2c000000 0x01000000>,
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<4 0 0x2d000000 0x01000000>;
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ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */
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<4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */
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<0 0 0x00000000 0x01000000>; /* CM-T3x NAND */
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};
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&dss {
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