mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 08:36:48 +07:00
Merge branch 'for-3.7' into next
This commit is contained in:
commit
df3d898c9f
@ -1392,26 +1392,17 @@ static int __devinit dw_probe(struct platform_device *pdev)
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size = sizeof(struct dw_dma);
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size += pdata->nr_channels * sizeof(struct dw_dma_chan);
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dw = kzalloc(size, GFP_KERNEL);
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dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
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if (!dw)
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return -ENOMEM;
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if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) {
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err = -EBUSY;
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goto err_kfree;
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}
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dw->regs = devm_request_and_ioremap(&pdev->dev, io);
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if (!dw->regs)
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return -EBUSY;
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dw->regs = ioremap(io->start, DW_REGLEN);
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if (!dw->regs) {
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err = -ENOMEM;
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goto err_release_r;
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}
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dw->clk = clk_get(&pdev->dev, "hclk");
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if (IS_ERR(dw->clk)) {
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err = PTR_ERR(dw->clk);
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goto err_clk;
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}
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dw->clk = devm_clk_get(&pdev->dev, "hclk");
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if (IS_ERR(dw->clk))
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return PTR_ERR(dw->clk);
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clk_prepare_enable(dw->clk);
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/* Calculate all channel mask before DMA setup */
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@ -1423,9 +1414,10 @@ static int __devinit dw_probe(struct platform_device *pdev)
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/* disable BLOCK interrupts as well */
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channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
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err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw);
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err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0,
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"dw_dmac", dw);
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if (err)
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goto err_irq;
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return err;
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platform_set_drvdata(pdev, dw);
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@ -1491,30 +1483,16 @@ static int __devinit dw_probe(struct platform_device *pdev)
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dma_async_device_register(&dw->dma);
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return 0;
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err_irq:
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clk_disable_unprepare(dw->clk);
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clk_put(dw->clk);
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err_clk:
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iounmap(dw->regs);
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dw->regs = NULL;
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err_release_r:
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release_resource(io);
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err_kfree:
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kfree(dw);
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return err;
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}
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static int __devexit dw_remove(struct platform_device *pdev)
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{
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struct dw_dma *dw = platform_get_drvdata(pdev);
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struct dw_dma_chan *dwc, *_dwc;
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struct resource *io;
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dw_dma_off(dw);
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dma_async_device_unregister(&dw->dma);
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free_irq(platform_get_irq(pdev, 0), dw);
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tasklet_kill(&dw->tasklet);
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list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
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@ -1523,17 +1501,6 @@ static int __devexit dw_remove(struct platform_device *pdev)
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channel_clear_bit(dw, CH_EN, dwc->mask);
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}
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clk_disable_unprepare(dw->clk);
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clk_put(dw->clk);
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iounmap(dw->regs);
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dw->regs = NULL;
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io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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release_mem_region(io->start, DW_REGLEN);
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kfree(dw);
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return 0;
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}
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@ -140,8 +140,6 @@ struct dw_dma_regs {
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/* Bitfields in CFG */
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#define DW_CFG_DMA_EN (1 << 0)
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#define DW_REGLEN 0x400
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enum dw_dmac_flags {
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DW_DMA_IS_CYCLIC = 0,
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};
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@ -1119,15 +1119,21 @@ struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
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static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
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{
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struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
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struct tegra_dma *tdma = tdc->tdma;
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int ret;
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dma_cookie_init(&tdc->dma_chan);
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tdc->config_init = false;
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return 0;
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ret = clk_prepare_enable(tdma->dma_clk);
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if (ret < 0)
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dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
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return ret;
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}
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static void tegra_dma_free_chan_resources(struct dma_chan *dc)
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{
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struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
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struct tegra_dma *tdma = tdc->tdma;
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struct tegra_dma_desc *dma_desc;
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struct tegra_dma_sg_req *sg_req;
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@ -1163,6 +1169,7 @@ static void tegra_dma_free_chan_resources(struct dma_chan *dc)
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list_del(&sg_req->node);
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kfree(sg_req);
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}
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clk_disable_unprepare(tdma->dma_clk);
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}
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/* Tegra20 specific DMA controller information */
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@ -1255,6 +1262,13 @@ static int __devinit tegra_dma_probe(struct platform_device *pdev)
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}
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}
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/* Enable clock before accessing registers */
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ret = clk_prepare_enable(tdma->dma_clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
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goto err_pm_disable;
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}
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/* Reset DMA controller */
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tegra_periph_reset_assert(tdma->dma_clk);
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udelay(2);
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@ -1265,6 +1279,8 @@ static int __devinit tegra_dma_probe(struct platform_device *pdev)
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tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
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tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
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clk_disable_unprepare(tdma->dma_clk);
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INIT_LIST_HEAD(&tdma->dma_dev.channels);
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for (i = 0; i < cdata->nr_channels; i++) {
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struct tegra_dma_channel *tdc = &tdma->channels[i];
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