mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 14:08:59 +07:00
dt-bindings: mmc: Correct the type of the clk phase properties
The clock phase properties are having two uint32 values. The minItems and maxItems are set to 2 for the same. So the property type should be 'uint32-array' and not 'uint32'. Modify it to correct the same. Reported-by: Rob Herring <robh@kernel.org> Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
parent
478c60cea1
commit
def7bd940f
@ -334,16 +334,17 @@ patternProperties:
|
||||
- reg
|
||||
|
||||
"^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- minimum: 0
|
||||
maximum: 359
|
||||
description:
|
||||
Set the clock (phase) delays which are to be configured in the
|
||||
controller while switching to particular speed mode. These values
|
||||
are in pair of degrees.
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 359
|
||||
description:
|
||||
Set the clock (phase) delays which are to be configured in the
|
||||
controller while switching to particular speed mode. These values
|
||||
are in pair of degrees.
|
||||
|
||||
dependencies:
|
||||
cd-debounce-delay-ms: [ cd-gpios ]
|
||||
|
Loading…
Reference in New Issue
Block a user