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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 03:46:47 +07:00
xhci: refactor and cleanup endpoint initialization.
xhci_endpoint_init() and helper functions were a bit messy. Adding the higher bandwidth SuperSpeedPlus Isoc support on top of it would make it even harder to read. No functional changes. Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mathias Nyman
Greg Kroah-Hartman
parent
faee822c5a
commit
def4e6f7b4
@ -1326,7 +1326,7 @@ static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
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default:
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BUG();
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}
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return EP_INTERVAL(interval);
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return interval;
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}
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/* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
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@ -1343,33 +1343,36 @@ static u32 xhci_get_endpoint_mult(struct usb_device *udev,
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return ep->ss_ep_comp.bmAttributes;
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}
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static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
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struct usb_host_endpoint *ep)
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{
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/* Super speed and Plus have max burst in ep companion desc */
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if (udev->speed >= USB_SPEED_SUPER)
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return ep->ss_ep_comp.bMaxBurst;
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if (udev->speed == USB_SPEED_HIGH &&
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(usb_endpoint_xfer_isoc(&ep->desc) ||
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usb_endpoint_xfer_int(&ep->desc)))
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return (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
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return 0;
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}
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static u32 xhci_get_endpoint_type(struct usb_host_endpoint *ep)
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{
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int in;
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u32 type;
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in = usb_endpoint_dir_in(&ep->desc);
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if (usb_endpoint_xfer_control(&ep->desc)) {
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type = EP_TYPE(CTRL_EP);
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} else if (usb_endpoint_xfer_bulk(&ep->desc)) {
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if (in)
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type = EP_TYPE(BULK_IN_EP);
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else
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type = EP_TYPE(BULK_OUT_EP);
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} else if (usb_endpoint_xfer_isoc(&ep->desc)) {
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if (in)
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type = EP_TYPE(ISOC_IN_EP);
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else
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type = EP_TYPE(ISOC_OUT_EP);
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} else if (usb_endpoint_xfer_int(&ep->desc)) {
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if (in)
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type = EP_TYPE(INT_IN_EP);
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else
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type = EP_TYPE(INT_OUT_EP);
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} else {
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type = 0;
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}
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return type;
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if (usb_endpoint_xfer_control(&ep->desc))
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return CTRL_EP;
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if (usb_endpoint_xfer_bulk(&ep->desc))
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return in ? BULK_IN_EP : BULK_OUT_EP;
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if (usb_endpoint_xfer_isoc(&ep->desc))
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return in ? ISOC_IN_EP : ISOC_OUT_EP;
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if (usb_endpoint_xfer_int(&ep->desc))
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return in ? INT_IN_EP : INT_OUT_EP;
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return 0;
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}
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/* Return the maximum endpoint service interval time (ESIT) payload.
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@ -1409,10 +1412,14 @@ int xhci_endpoint_init(struct xhci_hcd *xhci,
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struct xhci_ep_ctx *ep_ctx;
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struct xhci_ring *ep_ring;
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unsigned int max_packet;
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unsigned int max_burst;
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enum xhci_ring_type type;
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enum xhci_ring_type ring_type;
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u32 max_esit_payload;
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u32 endpoint_type;
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unsigned int max_burst;
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unsigned int interval;
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unsigned int mult;
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unsigned int avg_trb_len;
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unsigned int err_count = 0;
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ep_index = xhci_get_endpoint_index(&ep->desc);
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ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
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@ -1420,12 +1427,11 @@ int xhci_endpoint_init(struct xhci_hcd *xhci,
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endpoint_type = xhci_get_endpoint_type(ep);
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if (!endpoint_type)
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return -EINVAL;
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ep_ctx->ep_info2 = cpu_to_le32(endpoint_type);
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type = usb_endpoint_type(&ep->desc);
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ring_type = usb_endpoint_type(&ep->desc);
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/* Set up the endpoint ring */
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virt_dev->eps[ep_index].new_ring =
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xhci_ring_alloc(xhci, 2, 1, type, mem_flags);
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xhci_ring_alloc(xhci, 2, 1, ring_type, mem_flags);
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if (!virt_dev->eps[ep_index].new_ring) {
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/* Attempt to use the ring cache */
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if (virt_dev->num_rings_cached == 0)
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@ -1435,81 +1441,48 @@ int xhci_endpoint_init(struct xhci_hcd *xhci,
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virt_dev->ring_cache[virt_dev->num_rings_cached];
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virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
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xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
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1, type);
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1, ring_type);
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}
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virt_dev->eps[ep_index].skip = false;
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ep_ring = virt_dev->eps[ep_index].new_ring;
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ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
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ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
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| EP_MULT(xhci_get_endpoint_mult(udev, ep)));
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/*
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* Get values to fill the endpoint context, mostly from ep descriptor.
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* The average TRB buffer lengt for bulk endpoints is unclear as we
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* have no clue on scatter gather list entry size. For Isoc and Int,
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* set it to max available. See xHCI 1.1 spec 4.14.1.1 for details.
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*/
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max_esit_payload = xhci_get_max_esit_payload(udev, ep);
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interval = xhci_get_endpoint_interval(udev, ep);
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mult = xhci_get_endpoint_mult(udev, ep);
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max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
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max_burst = xhci_get_endpoint_max_burst(udev, ep);
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avg_trb_len = max_esit_payload;
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/* FIXME dig Mult and streams info out of ep companion desc */
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/* Allow 3 retries for everything but isoc;
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* CErr shall be set to 0 for Isoch endpoints.
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*/
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/* Allow 3 retries for everything but isoc, set CErr = 3 */
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if (!usb_endpoint_xfer_isoc(&ep->desc))
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ep_ctx->ep_info2 |= cpu_to_le32(ERROR_COUNT(3));
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else
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ep_ctx->ep_info2 |= cpu_to_le32(ERROR_COUNT(0));
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/* Set the max packet size and max burst */
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max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
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max_burst = 0;
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switch (udev->speed) {
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case USB_SPEED_SUPER_PLUS:
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case USB_SPEED_SUPER:
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/* dig out max burst from ep companion desc */
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max_burst = ep->ss_ep_comp.bMaxBurst;
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break;
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case USB_SPEED_HIGH:
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/* Some devices get this wrong */
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if (usb_endpoint_xfer_bulk(&ep->desc))
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max_packet = 512;
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/* bits 11:12 specify the number of additional transaction
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* opportunities per microframe (USB 2.0, section 9.6.6)
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*/
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if (usb_endpoint_xfer_isoc(&ep->desc) ||
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usb_endpoint_xfer_int(&ep->desc)) {
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max_burst = (usb_endpoint_maxp(&ep->desc)
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& 0x1800) >> 11;
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}
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break;
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case USB_SPEED_FULL:
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case USB_SPEED_LOW:
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break;
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default:
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BUG();
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}
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ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet) |
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MAX_BURST(max_burst));
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max_esit_payload = xhci_get_max_esit_payload(udev, ep);
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ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
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/*
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* XXX no idea how to calculate the average TRB buffer length for bulk
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* endpoints, as the driver gives us no clue how big each scatter gather
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* list entry (or buffer) is going to be.
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*
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* For isochronous and interrupt endpoints, we set it to the max
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* available, until we have new API in the USB core to allow drivers to
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* declare how much bandwidth they actually need.
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*
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* Normally, it would be calculated by taking the total of the buffer
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* lengths in the TD and then dividing by the number of TRBs in a TD,
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* including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
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* use Event Data TRBs, and we don't chain in a link TRB on short
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* transfers, we're basically dividing by 1.
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*
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* xHCI 1.0 and 1.1 specification indicates that the Average TRB Length
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* should be set to 8 for control endpoints.
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*/
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err_count = 3;
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/* Some devices get this wrong */
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if (usb_endpoint_xfer_bulk(&ep->desc) && udev->speed == USB_SPEED_HIGH)
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max_packet = 512;
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/* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */
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if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version >= 0x100)
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ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
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else
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ep_ctx->tx_info |=
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cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
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avg_trb_len = 8;
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/* Fill the endpoint context */
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ep_ctx->ep_info = cpu_to_le32(EP_INTERVAL(interval) |
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EP_MULT(mult));
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ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) |
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MAX_PACKET(max_packet) |
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MAX_BURST(max_burst) |
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ERROR_COUNT(err_count));
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ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma |
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ep_ring->cycle_state);
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ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
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EP_AVG_TRB_LENGTH(avg_trb_len));
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/* FIXME Debug endpoint context */
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return 0;
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@ -749,8 +749,8 @@ struct xhci_ep_ctx {
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#define GET_MAX_PACKET(p) ((p) & 0x7ff)
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/* tx_info bitmasks */
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#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
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#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
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#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
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#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
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#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
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/* deq bitmasks */
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