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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-03-08 02:44:51 +07:00
ath10k: disable interface pause wow config for integrated chipset
wow pause iface config controls the PCI D0/D3-WOW cases for pcie bus state. Firmware does not expects WOW_IFACE_PAUSE_ENABLED config for bus/link that cannot be suspended ex:snoc and does not trigger common subsystem shutdown. Disable interface pause wow config for integrated chipset(WCN3990) for correct WOW configuration in the firmware. Testing: Tested on WCN3990 HW. Tested FW: WLAN.HL.2.0-01192-QCAHLSWMTPLZ-1. Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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185be1c664
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de8781d7e7
@ -2994,8 +2994,9 @@ static void ath10k_core_register_work(struct work_struct *work)
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int ath10k_core_register(struct ath10k *ar,
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const struct ath10k_bus_params *bus_params)
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{
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ar->chip_id = bus_params->chip_id;
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ar->dev_type = bus_params->dev_type;
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ar->bus_param.chip_id = bus_params->chip_id;
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ar->bus_param.dev_type = bus_params->dev_type;
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ar->bus_param.link_can_suspend = bus_params->link_can_suspend;
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queue_work(ar->workqueue, &ar->register_work);
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return 0;
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@ -922,6 +922,7 @@ enum ath10k_dev_type {
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struct ath10k_bus_params {
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u32 chip_id;
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enum ath10k_dev_type dev_type;
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bool link_can_suspend;
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};
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struct ath10k {
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@ -1191,6 +1192,7 @@ struct ath10k {
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enum ath10k_radar_confirmation_state radar_conf_state;
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struct ath10k_radar_found_info last_radar_info;
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struct work_struct radar_confirmation_work;
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struct ath10k_bus_params bus_param;
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/* must be last */
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u8 drv_priv[0] __aligned(sizeof(void *));
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@ -1167,7 +1167,7 @@ static struct ath10k_dump_file_data *ath10k_coredump_build(struct ath10k *ar)
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dump_data->version = cpu_to_le32(ATH10K_FW_CRASH_DUMP_VERSION);
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guid_copy(&dump_data->guid, &crash_data->guid);
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dump_data->chip_id = cpu_to_le32(ar->chip_id);
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dump_data->chip_id = cpu_to_le32(ar->bus_param.chip_id);
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dump_data->bus_type = cpu_to_le32(0);
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dump_data->target_version = cpu_to_le32(ar->target_version);
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dump_data->fw_version_major = cpu_to_le32(ar->fw_version_major);
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@ -58,7 +58,7 @@ void ath10k_debug_print_hwfw_info(struct ath10k *ar)
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ath10k_info(ar, "%s target 0x%08x chip_id 0x%08x sub %04x:%04x",
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ar->hw_params.name,
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ar->target_version,
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ar->chip_id,
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ar->bus_param.chip_id,
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ar->id.subsystem_vendor, ar->id.subsystem_device);
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ath10k_info(ar, "kconfig debug %d debugfs %d tracing %d dfs %d testmode %d\n",
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@ -625,7 +625,7 @@ static ssize_t ath10k_read_chip_id(struct file *file, char __user *user_buf,
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size_t len;
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char buf[50];
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len = scnprintf(buf, sizeof(buf), "0x%08x\n", ar->chip_id);
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len = scnprintf(buf, sizeof(buf), "0x%08x\n", ar->bus_param.chip_id);
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return simple_read_from_buffer(user_buf, count, ppos, buf, len);
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}
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@ -53,7 +53,7 @@ static inline void ath10k_htc_restore_tx_skb(struct ath10k_htc *htc,
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{
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struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(skb);
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if (htc->ar->dev_type != ATH10K_DEV_TYPE_HL)
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if (htc->ar->bus_param.dev_type != ATH10K_DEV_TYPE_HL)
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dma_unmap_single(htc->ar->dev, skb_cb->paddr, skb->len, DMA_TO_DEVICE);
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skb_pull(skb, sizeof(struct ath10k_htc_hdr));
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}
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@ -138,7 +138,7 @@ int ath10k_htc_send(struct ath10k_htc *htc,
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ath10k_htc_prepare_tx_skb(ep, skb);
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skb_cb->eid = eid;
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if (ar->dev_type != ATH10K_DEV_TYPE_HL) {
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if (ar->bus_param.dev_type != ATH10K_DEV_TYPE_HL) {
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skb_cb->paddr = dma_map_single(dev, skb->data, skb->len,
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DMA_TO_DEVICE);
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ret = dma_mapping_error(dev, skb_cb->paddr);
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@ -161,7 +161,7 @@ int ath10k_htc_send(struct ath10k_htc *htc,
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return 0;
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err_unmap:
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if (ar->dev_type != ATH10K_DEV_TYPE_HL)
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if (ar->bus_param.dev_type != ATH10K_DEV_TYPE_HL)
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dma_unmap_single(dev, skb_cb->paddr, skb->len, DMA_TO_DEVICE);
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err_credits:
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if (ep->tx_credit_flow_enabled) {
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@ -265,7 +265,7 @@ int ath10k_htt_rx_ring_refill(struct ath10k *ar)
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struct ath10k_htt *htt = &ar->htt;
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int ret;
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if (ar->dev_type == ATH10K_DEV_TYPE_HL)
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if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL)
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return 0;
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spin_lock_bh(&htt->rx_ring.lock);
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@ -282,7 +282,7 @@ int ath10k_htt_rx_ring_refill(struct ath10k *ar)
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void ath10k_htt_rx_free(struct ath10k_htt *htt)
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{
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if (htt->ar->dev_type == ATH10K_DEV_TYPE_HL)
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if (htt->ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL)
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return;
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del_timer_sync(&htt->rx_ring.refill_retry_timer);
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@ -760,7 +760,7 @@ int ath10k_htt_rx_alloc(struct ath10k_htt *htt)
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size_t size;
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struct timer_list *timer = &htt->rx_ring.refill_retry_timer;
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if (ar->dev_type == ATH10K_DEV_TYPE_HL)
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if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL)
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return 0;
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htt->rx_confused = false;
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@ -3237,7 +3237,7 @@ bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
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break;
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}
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case HTT_T2H_MSG_TYPE_RX_IND:
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if (ar->dev_type == ATH10K_DEV_TYPE_HL)
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if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL)
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return ath10k_htt_rx_proc_rx_ind_hl(htt,
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&resp->rx_ind_hl,
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skb);
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@ -3533,7 +3533,7 @@ void ath10k_htt_set_rx_ops(struct ath10k_htt *htt)
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{
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struct ath10k *ar = htt->ar;
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if (ar->dev_type == ATH10K_DEV_TYPE_HL)
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if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL)
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htt->rx_ops = &htt_rx_ops_hl;
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else if (ar->hw_params.target_64bit)
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htt->rx_ops = &htt_rx_ops_64;
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@ -495,7 +495,7 @@ int ath10k_htt_tx_start(struct ath10k_htt *htt)
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if (htt->tx_mem_allocated)
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return 0;
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if (ar->dev_type == ATH10K_DEV_TYPE_HL)
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if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL)
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return 0;
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ret = ath10k_htt_tx_alloc_buf(htt);
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@ -1224,7 +1224,7 @@ int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
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return 0;
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err_unmap_msdu:
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if (ar->dev_type != ATH10K_DEV_TYPE_HL)
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if (ar->bus_param.dev_type != ATH10K_DEV_TYPE_HL)
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dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
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err_free_txdesc:
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dev_kfree_skb_any(txdesc);
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@ -1763,7 +1763,7 @@ void ath10k_htt_set_tx_ops(struct ath10k_htt *htt)
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{
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struct ath10k *ar = htt->ar;
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if (ar->dev_type == ATH10K_DEV_TYPE_HL)
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if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL)
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htt->tx_ops = &htt_tx_ops_hl;
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else if (ar->hw_params.target_64bit)
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htt->tx_ops = &htt_tx_ops_64;
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@ -2283,7 +2283,7 @@ static int ath10k_pci_get_num_banks(struct ath10k *ar)
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return 1;
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case QCA6164_2_1_DEVICE_ID:
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case QCA6174_2_1_DEVICE_ID:
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switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
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switch (MS(ar->bus_param.chip_id, SOC_CHIP_ID_REV)) {
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case QCA6174_HW_1_0_CHIP_ID_REV:
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case QCA6174_HW_1_1_CHIP_ID_REV:
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case QCA6174_HW_2_1_CHIP_ID_REV:
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@ -3636,6 +3636,7 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
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}
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bus_params.dev_type = ATH10K_DEV_TYPE_LL;
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bus_params.link_can_suspend = true;
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bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
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if (bus_params.chip_id == 0xffffffff) {
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ath10k_err(ar, "failed to get chip id\n");
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@ -95,7 +95,7 @@ int ath10k_txrx_tx_unref(struct ath10k_htt *htt,
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wake_up(&htt->empty_tx_wq);
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spin_unlock_bh(&htt->tx_lock);
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if (ar->dev_type != ATH10K_DEV_TYPE_HL)
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if (ar->bus_param.dev_type != ATH10K_DEV_TYPE_HL)
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dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
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ath10k_report_offchan_tx(htt->ar, msdu);
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@ -3323,6 +3323,8 @@ ath10k_wmi_tlv_op_gen_wow_enable(struct ath10k *ar)
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cmd = (void *)tlv->value;
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cmd->enable = __cpu_to_le32(1);
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if (!ar->bus_param.link_can_suspend)
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cmd->pause_iface_config = __cpu_to_le32(WOW_IFACE_PAUSE_DISABLED);
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ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi tlv wow enable\n");
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return skb;
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@ -2001,8 +2001,15 @@ struct wmi_tlv_set_quiet_cmd {
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__le32 enabled;
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} __packed;
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enum wmi_tlv_wow_interface_cfg {
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WOW_IFACE_PAUSE_ENABLED,
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WOW_IFACE_PAUSE_DISABLED
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};
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struct wmi_tlv_wow_enable_cmd {
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__le32 enable;
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__le32 pause_iface_config;
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__le32 flags;
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} __packed;
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struct wmi_tlv_wow_host_wakeup_ind {
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