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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 22:16:40 +07:00
gpu: host1x: Program the channel stream ID
When processing command streams, make sure the host1x's stream ID is programmed for the channel so that addresses are properly translated through the SMMU. Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -17,6 +17,7 @@
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*/
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#include <linux/host1x.h>
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#include <linux/iommu.h>
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#include <linux/slab.h>
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#include <trace/events/host1x.h>
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@ -89,6 +90,16 @@ static inline void synchronize_syncpt_base(struct host1x_job *job)
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HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(value));
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}
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static void host1x_channel_set_streamid(struct host1x_channel *channel)
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{
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#if HOST1X_HW >= 6
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struct iommu_fwspec *spec = dev_iommu_fwspec_get(channel->dev->parent);
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u32 sid = spec ? spec->ids[0] & 0xffff : 0x7f;
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host1x_ch_writel(channel, sid, HOST1X_CHANNEL_SMMU_STREAMID);
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#endif
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}
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static int channel_submit(struct host1x_job *job)
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{
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struct host1x_channel *ch = job->channel;
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@ -120,6 +131,8 @@ static int channel_submit(struct host1x_job *job)
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goto error;
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}
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host1x_channel_set_streamid(ch);
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/* begin a CDMA submit */
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err = host1x_cdma_begin(&ch->cdma, job);
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if (err) {
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@ -22,6 +22,7 @@
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include "hw_host1x06_channel.h"
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#include "hw_host1x06_uclass.h"
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#include "hw_host1x06_vm.h"
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#include "hw_host1x06_hypervisor.h"
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@ -22,6 +22,7 @@
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include "hw_host1x07_channel.h"
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#include "hw_host1x07_uclass.h"
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#include "hw_host1x07_vm.h"
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#include "hw_host1x07_hypervisor.h"
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11
drivers/gpu/host1x/hw/hw_host1x06_channel.h
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11
drivers/gpu/host1x/hw/hw_host1x06_channel.h
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@ -0,0 +1,11 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 NVIDIA Corporation.
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*/
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#ifndef HOST1X_HW_HOST1X06_CHANNEL_H
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#define HOST1X_HW_HOST1X06_CHANNEL_H
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#define HOST1X_CHANNEL_SMMU_STREAMID 0x084
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#endif
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drivers/gpu/host1x/hw/hw_host1x07_channel.h
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11
drivers/gpu/host1x/hw/hw_host1x07_channel.h
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@ -0,0 +1,11 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 NVIDIA Corporation.
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*/
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#ifndef HOST1X_HW_HOST1X07_CHANNEL_H
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#define HOST1X_HW_HOST1X07_CHANNEL_H
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#define HOST1X_CHANNEL_SMMU_STREAMID 0x084
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#endif
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