AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2025-03-05 14:35:20 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

gpu: host1x: Program the channel stream ID

Browse Source 
When processing command streams, make sure the host1x's stream ID is
programmed for the channel so that addresses are properly translated
through the SMMU.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2019-02-01 14:28:23 +01:00
parent 6841482b82
commit de5469c21f
5 changed files with 37 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/host1x/hw/channel_hw.c
View File

@ -17,6 +17,7 @@
*/ */
#include <linux/host1x.h> #include <linux/host1x.h>
#include <linux/iommu.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <trace/events/host1x.h> #include <trace/events/host1x.h>
@ -89,6 +90,16 @@ static inline void synchronize_syncpt_base(struct host1x_job *job)
HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(value)); HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(value));
} }
static void host1x_channel_set_streamid(struct host1x_channel *channel)
{
#if HOST1X_HW >= 6
struct iommu_fwspec *spec = dev_iommu_fwspec_get(channel->dev->parent);
u32 sid = spec ? spec->ids[0] & 0xffff : 0x7f;
host1x_ch_writel(channel, sid, HOST1X_CHANNEL_SMMU_STREAMID);
#endif
}
static int channel_submit(struct host1x_job *job) static int channel_submit(struct host1x_job *job)
{ {
struct host1x_channel *ch = job->channel; struct host1x_channel *ch = job->channel;
@ -120,6 +131,8 @@ static int channel_submit(struct host1x_job *job)
goto error; goto error;
} }
host1x_channel_set_streamid(ch);
/* begin a CDMA submit */ /* begin a CDMA submit */
err = host1x_cdma_begin(&ch->cdma, job); err = host1x_cdma_begin(&ch->cdma, job);
if (err) { if (err) {

1
drivers/gpu/host1x/hw/host1x06_hardware.h
View File

@ -22,6 +22,7 @@
#include <linux/types.h> #include <linux/types.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include "hw_host1x06_channel.h"
#include "hw_host1x06_uclass.h" #include "hw_host1x06_uclass.h"
#include "hw_host1x06_vm.h" #include "hw_host1x06_vm.h"
#include "hw_host1x06_hypervisor.h" #include "hw_host1x06_hypervisor.h"

1
drivers/gpu/host1x/hw/host1x07_hardware.h
View File

@ -22,6 +22,7 @@
#include <linux/types.h> #include <linux/types.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include "hw_host1x07_channel.h"
#include "hw_host1x07_uclass.h" #include "hw_host1x07_uclass.h"
#include "hw_host1x07_vm.h" #include "hw_host1x07_vm.h"
#include "hw_host1x07_hypervisor.h" #include "hw_host1x07_hypervisor.h"

11
drivers/gpu/host1x/hw/hw_host1x06_channel.h Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 NVIDIA Corporation.
*/
#ifndef HOST1X_HW_HOST1X06_CHANNEL_H
#define HOST1X_HW_HOST1X06_CHANNEL_H
#define HOST1X_CHANNEL_SMMU_STREAMID 0x084
#endif

11
drivers/gpu/host1x/hw/hw_host1x07_channel.h Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 NVIDIA Corporation.
*/
#ifndef HOST1X_HW_HOST1X07_CHANNEL_H
#define HOST1X_HW_HOST1X07_CHANNEL_H
#define HOST1X_CHANNEL_SMMU_STREAMID 0x084
#endif