AuxXxilium/linux_dsm_epyc7002
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mmc: sdhci: usdhc: do not do tuning for DDR50 mode.

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DDR50 tuning is optinally defined in sd 3.0 spec. And i.MX
uSDHC internally already uses a fixed optimized timing for
DDR50, normally does not require tuning for DDR50 mode.

This patch specify a new execute_tuning function for i.MX
uSDHC, do not impact i.MX eSDHC.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
BOUGH CHEN 2018-12-21 09:20:53 +00:00 committed by Ulf Hansson
parent a98c557e2a
commit de3e1dd09b
1 changed files with 20 additions and 0 deletions
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20
drivers/mmc/host/sdhci-esdhc-imx.c
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@ -801,6 +801,20 @@ static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
SDHCI_HOST_CONTROL);
}
static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
struct sdhci_host *host = mmc_priv(mmc);
/*
* i.MX uSDHC internally already uses a fixed optimized timing for
* DDR50, normally does not require tuning for DDR50 mode.
*/
if (host->timing == MMC_TIMING_UHS_DDR50)
return 0;
return sdhci_execute_tuning(mmc, opcode);
}
static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
{
u32 reg;
@ -1330,6 +1344,12 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
/*
* Link usdhc specific mmc_host_ops execute_tuning function,
* to replace the standard one in sdhci_ops.
*/
host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
}
if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)