From ddb8d0520bbc6ffdf900fb2a2a21d203199c64b8 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Fri, 15 May 2020 10:32:24 +0200 Subject: [PATCH] drm/mgag200: Update mode registers after plane registers Setting the plane registers first and the mode registers afterwards reproduces the sequence used by atomic helpers. Done in preparation of switching to simple KMS helpers. Signed-off-by: Thomas Zimmermann Tested-by: John Donnelly Acked-by: Sam Ravnborg Acked-by: Emil Velikov Link: https://patchwork.freedesktop.org/patch/msgid/20200515083233.32036-7-tzimmermann@suse.de --- drivers/gpu/drm/mgag200/mgag200_mode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c index 2007d7a4754a..4dba0a379c26 100644 --- a/drivers/gpu/drm/mgag200/mgag200_mode.c +++ b/drivers/gpu/drm/mgag200/mgag200_mode.c @@ -1145,8 +1145,6 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc, WREG_CRT(15, 0); WREG_CRT(19, pitch & 0xFF); - mgag200_set_mode_regs(mdev, mode); - ext_vga[0] = 0; /* TODO interlace */ @@ -1182,6 +1180,8 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc, mga_crtc_do_set_base(mdev, fb, old_fb); + mgag200_set_mode_regs(mdev, mode); + /* reset tagfifo */ if (mdev->type == G200_ER) { u32 mem_ctl = RREG32(MGAREG_MEMCTL);