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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 10:20:49 +07:00
objtool: Handle GCC stack pointer adjustment bug
Arnd Bergmann reported the following warning with GCC 7.1.1: fs/fs_pin.o: warning: objtool: pin_kill()+0x139: stack state mismatch: cfa1=7+88 cfa2=7+96 And the kbuild robot reported the following warnings with GCC 5.4.1: fs/fs_pin.o: warning: objtool: pin_kill()+0x182: return with modified stack frame fs/quota/dquot.o: warning: objtool: dquot_alloc_inode()+0x140: stack state mismatch: cfa1=7+120 cfa2=7+128 fs/quota/dquot.o: warning: objtool: dquot_free_inode()+0x11a: stack state mismatch: cfa1=7+112 cfa2=7+120 Those warnings are caused by an unusual GCC non-optimization where it uses an intermediate register to adjust the stack pointer. It does: lea 0x8(%rsp), %rcx ... mov %rcx, %rsp Instead of the obvious: add $0x8, %rsp It makes no sense to use an intermediate register, so I opened a GCC bug to track it: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81813 But it's not exactly a high-priority bug and it looks like we'll be stuck with this issue for a while. So for now we have to track register values when they're loaded with stack pointer offsets. This is kind of a big workaround for a tiny problem, but c'est la vie. I hope to eventually create a GCC plugin to implement a big chunk of objtool's functionality. Hopefully at that point we'll be able to remove of a lot of these GCC-isms from the objtool code. Reported-by: Arnd Bergmann <arnd@arndb.de> Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/6a41a96884c725e7f05413bb7df40cfe824b2444.1504028945.git.jpoimboe@redhat.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -86,8 +86,8 @@ int arch_decode_instruction(struct elf *elf, struct section *sec,
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struct insn insn;
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int x86_64, sign;
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unsigned char op1, op2, rex = 0, rex_b = 0, rex_r = 0, rex_w = 0,
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modrm = 0, modrm_mod = 0, modrm_rm = 0, modrm_reg = 0,
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sib = 0;
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rex_x = 0, modrm = 0, modrm_mod = 0, modrm_rm = 0,
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modrm_reg = 0, sib = 0;
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x86_64 = is_x86_64(elf);
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if (x86_64 == -1)
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@ -114,6 +114,7 @@ int arch_decode_instruction(struct elf *elf, struct section *sec,
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rex = insn.rex_prefix.bytes[0];
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rex_w = X86_REX_W(rex) >> 3;
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rex_r = X86_REX_R(rex) >> 2;
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rex_x = X86_REX_X(rex) >> 1;
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rex_b = X86_REX_B(rex);
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}
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@ -217,6 +218,18 @@ int arch_decode_instruction(struct elf *elf, struct section *sec,
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op->dest.reg = CFI_BP;
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break;
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}
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if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
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/* mov reg, %rsp */
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*type = INSN_STACK;
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op->src.type = OP_SRC_REG;
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op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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break;
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}
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/* fallthrough */
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case 0x88:
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if (!rex_b &&
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@ -269,7 +282,17 @@ int arch_decode_instruction(struct elf *elf, struct section *sec,
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break;
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case 0x8d:
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if (rex == 0x48 && modrm == 0x65) {
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if (sib == 0x24 && rex_w && !rex_b && !rex_x) {
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/* lea disp(%rsp), reg */
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*type = INSN_STACK;
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op->src.type = OP_SRC_ADD;
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op->src.reg = CFI_SP;
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op->src.offset = insn.displacement.value;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
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} else if (rex == 0x48 && modrm == 0x65) {
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/* lea disp(%rbp), %rsp */
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*type = INSN_STACK;
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@ -278,71 +301,9 @@ int arch_decode_instruction(struct elf *elf, struct section *sec,
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op->src.offset = insn.displacement.value;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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break;
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}
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if (rex == 0x48 && (modrm == 0xa4 || modrm == 0x64) &&
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sib == 0x24) {
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/* lea disp(%rsp), %rsp */
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*type = INSN_STACK;
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op->src.type = OP_SRC_ADD;
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op->src.reg = CFI_SP;
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op->src.offset = insn.displacement.value;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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break;
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}
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if (rex == 0x48 && modrm == 0x2c && sib == 0x24) {
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/* lea (%rsp), %rbp */
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*type = INSN_STACK;
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op->src.type = OP_SRC_REG;
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op->src.reg = CFI_SP;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_BP;
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break;
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}
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if (rex == 0x4c && modrm == 0x54 && sib == 0x24 &&
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insn.displacement.value == 8) {
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/*
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* lea 0x8(%rsp), %r10
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*
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* Here r10 is the "drap" pointer, used as a stack
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* pointer helper when the stack gets realigned.
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*/
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*type = INSN_STACK;
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op->src.type = OP_SRC_ADD;
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op->src.reg = CFI_SP;
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op->src.offset = 8;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_R10;
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break;
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}
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if (rex == 0x4c && modrm == 0x6c && sib == 0x24 &&
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insn.displacement.value == 16) {
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/*
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* lea 0x10(%rsp), %r13
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*
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* Here r13 is the "drap" pointer, used as a stack
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* pointer helper when the stack gets realigned.
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*/
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*type = INSN_STACK;
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op->src.type = OP_SRC_ADD;
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op->src.reg = CFI_SP;
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op->src.offset = 16;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_R13;
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break;
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}
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if (rex == 0x49 && modrm == 0x62 &&
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insn.displacement.value == -8) {
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} else if (rex == 0x49 && modrm == 0x62 &&
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insn.displacement.value == -8) {
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/*
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* lea -0x8(%r10), %rsp
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@ -356,11 +317,9 @@ int arch_decode_instruction(struct elf *elf, struct section *sec,
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op->src.offset = -8;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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break;
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}
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if (rex == 0x49 && modrm == 0x65 &&
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insn.displacement.value == -16) {
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} else if (rex == 0x49 && modrm == 0x65 &&
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insn.displacement.value == -16) {
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/*
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* lea -0x10(%r13), %rsp
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@ -374,7 +333,6 @@ int arch_decode_instruction(struct elf *elf, struct section *sec,
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op->src.offset = -16;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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break;
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}
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break;
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@ -40,7 +40,7 @@
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#define CFI_R14 14
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#define CFI_R15 15
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#define CFI_RA 16
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#define CFI_NUM_REGS 17
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#define CFI_NUM_REGS 17
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struct cfi_reg {
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int base;
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@ -218,8 +218,10 @@ static void clear_insn_state(struct insn_state *state)
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memset(state, 0, sizeof(*state));
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state->cfa.base = CFI_UNDEFINED;
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for (i = 0; i < CFI_NUM_REGS; i++)
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for (i = 0; i < CFI_NUM_REGS; i++) {
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state->regs[i].base = CFI_UNDEFINED;
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state->vals[i].base = CFI_UNDEFINED;
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}
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state->drap_reg = CFI_UNDEFINED;
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state->drap_offset = -1;
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}
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@ -1201,24 +1203,47 @@ static int update_insn_state(struct instruction *insn, struct insn_state *state)
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switch (op->src.type) {
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case OP_SRC_REG:
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if (cfa->base == op->src.reg && cfa->base == CFI_SP &&
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op->dest.reg == CFI_BP && regs[CFI_BP].base == CFI_CFA &&
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regs[CFI_BP].offset == -cfa->offset) {
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if (op->src.reg == CFI_SP && op->dest.reg == CFI_BP) {
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/* mov %rsp, %rbp */
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cfa->base = op->dest.reg;
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state->bp_scratch = false;
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} else if (state->drap) {
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if (cfa->base == CFI_SP &&
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regs[CFI_BP].base == CFI_CFA &&
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regs[CFI_BP].offset == -cfa->offset) {
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/* drap: mov %rsp, %rbp */
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regs[CFI_BP].base = CFI_BP;
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regs[CFI_BP].offset = -state->stack_size;
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state->bp_scratch = false;
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} else if (!no_fp) {
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/* mov %rsp, %rbp */
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cfa->base = op->dest.reg;
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state->bp_scratch = false;
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}
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WARN_FUNC("unknown stack-related register move",
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insn->sec, insn->offset);
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return -1;
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else if (state->drap) {
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/* drap: mov %rsp, %rbp */
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regs[CFI_BP].base = CFI_BP;
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regs[CFI_BP].offset = -state->stack_size;
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state->bp_scratch = false;
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}
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}
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else if (op->dest.reg == cfa->base) {
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/* mov %reg, %rsp */
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if (cfa->base == CFI_SP &&
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state->vals[op->src.reg].base == CFI_CFA) {
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/*
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* This is needed for the rare case
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* where GCC does something dumb like:
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*
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* lea 0x8(%rsp), %rcx
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* ...
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* mov %rcx, %rsp
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*/
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cfa->offset = -state->vals[op->src.reg].offset;
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state->stack_size = cfa->offset;
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} else {
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cfa->base = CFI_UNDEFINED;
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cfa->offset = 0;
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}
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}
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break;
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@ -1240,11 +1265,25 @@ static int update_insn_state(struct instruction *insn, struct insn_state *state)
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break;
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}
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if (op->dest.reg != CFI_BP && op->src.reg == CFI_SP &&
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cfa->base == CFI_SP) {
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if (op->src.reg == CFI_SP && cfa->base == CFI_SP) {
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/* drap: lea disp(%rsp), %drap */
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state->drap_reg = op->dest.reg;
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/*
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* lea disp(%rsp), %reg
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*
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* This is needed for the rare case where GCC
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* does something dumb like:
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*
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* lea 0x8(%rsp), %rcx
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* ...
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* mov %rcx, %rsp
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*/
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state->vals[op->dest.reg].base = CFI_CFA;
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state->vals[op->dest.reg].offset = \
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-state->stack_size + op->src.offset;
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break;
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}
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@ -33,6 +33,7 @@ struct insn_state {
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bool bp_scratch;
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bool drap;
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int drap_reg, drap_offset;
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struct cfi_reg vals[CFI_NUM_REGS];
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};
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struct instruction {
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