mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 01:56:40 +07:00
Merge 5.9-rc3 into char-misc-next
We need the fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman
commit
dd5597245d
122
.mailmap
122
.mailmap
@ -15,30 +15,31 @@
|
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Aaron Durbin <adurbin@google.com>
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Adam Oldham <oldhamca@gmail.com>
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Adam Radford <aradford@gmail.com>
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Adrian Bunk <bunk@stusta.de>
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Adriana Reus <adi.reus@gmail.com> <adriana.reus@intel.com>
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Adrian Bunk <bunk@stusta.de>
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Alan Cox <alan@lxorguk.ukuu.org.uk>
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Alan Cox <root@hraefn.swansea.linux.org.uk>
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Aleksey Gorelov <aleksey_gorelov@phoenix.com>
|
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Aleksandar Markovic <aleksandar.markovic@mips.com> <aleksandar.markovic@imgtec.com>
|
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Alex Shi <alex.shi@linux.alibaba.com> <alex.shi@intel.com>
|
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Alex Shi <alex.shi@linux.alibaba.com> <alex.shi@linaro.org>
|
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Aleksey Gorelov <aleksey_gorelov@phoenix.com>
|
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Alexander Lobakin <alobakin@pm.me> <alobakin@dlink.ru>
|
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Alexander Lobakin <alobakin@pm.me> <alobakin@marvell.com>
|
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Alexander Lobakin <alobakin@pm.me> <bloodyreaper@yandex.ru>
|
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Alexandre Belloni <alexandre.belloni@bootlin.com> <alexandre.belloni@free-electrons.com>
|
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Alexei Starovoitov <ast@kernel.org> <ast@plumgrid.com>
|
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Alexei Starovoitov <ast@kernel.org> <alexei.starovoitov@gmail.com>
|
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Alexei Starovoitov <ast@kernel.org> <ast@fb.com>
|
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Alexei Starovoitov <ast@kernel.org> <ast@plumgrid.com>
|
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Alex Shi <alex.shi@linux.alibaba.com> <alex.shi@intel.com>
|
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Alex Shi <alex.shi@linux.alibaba.com> <alex.shi@linaro.org>
|
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Al Viro <viro@ftp.linux.org.uk>
|
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Al Viro <viro@zenIV.linux.org.uk>
|
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Andi Kleen <ak@linux.intel.com> <ak@suse.de>
|
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Andi Shyti <andi@etezian.org> <andi.shyti@samsung.com>
|
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Andreas Herrmann <aherrman@de.ibm.com>
|
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Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>
|
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Andrew Morton <akpm@linux-foundation.org>
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Andrew Murray <amurray@thegoodpenguin.co.uk> <andrew.murray@arm.com>
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Andrew Murray <amurray@thegoodpenguin.co.uk> <amurray@embedded-bits.co.uk>
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Andrew Murray <amurray@thegoodpenguin.co.uk> <andrew.murray@arm.com>
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Andrew Vasquez <andrew.vasquez@qlogic.com>
|
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Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>
|
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Andy Adamson <andros@citi.umich.edu>
|
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Antoine Tenart <antoine.tenart@free-electrons.com>
|
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Antonio Ospite <ao2@ao2.it> <ao2@amarulasolutions.com>
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@ -48,40 +49,42 @@ Arnaud Patard <arnaud.patard@rtp-net.org>
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Arnd Bergmann <arnd@arndb.de>
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Axel Dyks <xl@xlsigned.net>
|
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Axel Lin <axel.lin@gmail.com>
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Bart Van Assche <bvanassche@acm.org> <bart.vanassche@wdc.com>
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Bart Van Assche <bvanassche@acm.org> <bart.vanassche@sandisk.com>
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Bart Van Assche <bvanassche@acm.org> <bart.vanassche@wdc.com>
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Ben Gardner <bgardner@wabtec.com>
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Ben M Cahill <ben.m.cahill@intel.com>
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Björn Steinbrink <B.Steinbrink@gmx.de>
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Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
|
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Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
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Boris Brezillon <bbrezillon@kernel.org> <b.brezillon.dev@gmail.com>
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Boris Brezillon <bbrezillon@kernel.org> <b.brezillon@overkiz.com>
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Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
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Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
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Brian Avery <b.avery@hp.com>
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Brian King <brking@us.ibm.com>
|
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Changbin Du <changbin.du@intel.com> <changbin.du@gmail.com>
|
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Changbin Du <changbin.du@intel.com> <changbin.du@intel.com>
|
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Chao Yu <chao@kernel.org> <chao2.yu@samsung.com>
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Chao Yu <chao@kernel.org> <yuchao0@huawei.com>
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Christoph Hellwig <hch@lst.de>
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Christophe Ricard <christophe.ricard@gmail.com>
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Christoph Hellwig <hch@lst.de>
|
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Corey Minyard <minyard@acm.org>
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Damian Hobson-Garcia <dhobsong@igel.co.jp>
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Daniel Borkmann <daniel@iogearbox.net> <dborkman@redhat.com>
|
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Daniel Borkmann <daniel@iogearbox.net> <dborkmann@redhat.com>
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Daniel Borkmann <daniel@iogearbox.net> <danborkmann@googlemail.com>
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Daniel Borkmann <daniel@iogearbox.net> <danborkmann@iogearbox.net>
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Daniel Borkmann <daniel@iogearbox.net> <daniel.borkmann@tik.ee.ethz.ch>
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Daniel Borkmann <daniel@iogearbox.net> <danborkmann@googlemail.com>
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Daniel Borkmann <daniel@iogearbox.net> <dborkmann@redhat.com>
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Daniel Borkmann <daniel@iogearbox.net> <dborkman@redhat.com>
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Daniel Borkmann <daniel@iogearbox.net> <dxchgb@gmail.com>
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David Brownell <david-b@pacbell.net>
|
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David Woodhouse <dwmw2@shinybook.infradead.org>
|
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Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@mips.com>
|
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Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@imgtec.com>
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Dengcheng Zhu <dzhu@wavecomp.com> <dczhu@mips.com>
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Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@gmail.com>
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Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@imgtec.com>
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Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@mips.com>
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<dev.kurt@vandijck-laurijssen.be> <kurt.van.dijck@eia.be>
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Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
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Dmitry Safonov <0x7f454c46@gmail.com> <dsafonov@virtuozzo.com>
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Dmitry Safonov <0x7f454c46@gmail.com> <d.safonov@partner.samsung.com>
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Dmitry Safonov <0x7f454c46@gmail.com> <dima@arista.com>
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Dmitry Safonov <0x7f454c46@gmail.com> <d.safonov@partner.samsung.com>
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Dmitry Safonov <0x7f454c46@gmail.com> <dsafonov@virtuozzo.com>
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Domen Puncer <domen@coderock.org>
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Douglas Gilbert <dougg@torque.net>
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Ed L. Cashin <ecashin@coraid.com>
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@ -92,20 +95,22 @@ Felix Kuhling <fxkuehl@gmx.de>
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Felix Moeller <felix@derklecks.de>
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Filipe Lautert <filipe@icewall.org>
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Franck Bui-Huu <vagabon.xyz@gmail.com>
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Frank Rowand <frowand.list@gmail.com> <frowand@mvista.com>
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Frank Rowand <frowand.list@gmail.com> <frank.rowand@am.sony.com>
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Frank Rowand <frowand.list@gmail.com> <frank.rowand@sonymobile.com>
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Frank Rowand <frowand.list@gmail.com> <frowand@mvista.com>
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Frank Zago <fzago@systemfabricworks.com>
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Gao Xiang <xiang@kernel.org> <gaoxiang25@huawei.com>
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Gao Xiang <xiang@kernel.org> <hsiangkao@aol.com>
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Gerald Schaefer <gerald.schaefer@linux.ibm.com> <gerald.schaefer@de.ibm.com>
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Gerald Schaefer <gerald.schaefer@linux.ibm.com> <geraldsc@de.ibm.com>
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Gerald Schaefer <gerald.schaefer@linux.ibm.com> <gerald.schaefer@de.ibm.com>
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Gerald Schaefer <gerald.schaefer@linux.ibm.com> <geraldsc@linux.vnet.ibm.com>
|
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Greg Kroah-Hartman <greg@echidna.(none)>
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Greg Kroah-Hartman <gregkh@suse.de>
|
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Greg Kroah-Hartman <greg@kroah.com>
|
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Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
|
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Gregory CLEMENT <gregory.clement@bootlin.com> <gregory.clement@free-electrons.com>
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Gustavo Padovan <gustavo@las.ic.unicamp.br>
|
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Gustavo Padovan <padovan@profusion.mobi>
|
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Hanjun Guo <guohanjun@huawei.com> <hanjun.guo@linaro.org>
|
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Heiko Carstens <hca@linux.ibm.com> <h.carstens@de.ibm.com>
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Heiko Carstens <hca@linux.ibm.com> <heiko.carstens@de.ibm.com>
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@ -115,32 +120,33 @@ Henrik Rydberg <rydberg@bitmath.org>
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Herbert Xu <herbert@gondor.apana.org.au>
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Jacob Shin <Jacob.Shin@amd.com>
|
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Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@google.com>
|
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Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@motorola.com>
|
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Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk.kim@samsung.com>
|
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Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@motorola.com>
|
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Jakub Kicinski <kuba@kernel.org> <jakub.kicinski@netronome.com>
|
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James Bottomley <jejb@mulgrave.(none)>
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James Bottomley <jejb@titanic.il.steeleye.com>
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James E Wilson <wilson@specifix.com>
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James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
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James Hogan <jhogan@kernel.org> <james@albanarts.com>
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James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
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James Ketrenos <jketreno@io.(none)>
|
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Jan Glauber <jan.glauber@gmail.com> <jang@de.ibm.com>
|
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Jan Glauber <jan.glauber@gmail.com> <jang@linux.vnet.ibm.com>
|
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Jan Glauber <jan.glauber@gmail.com> <jglauber@cavium.com>
|
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Jason Gunthorpe <jgg@ziepe.ca> <jgg@mellanox.com>
|
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Jason Gunthorpe <jgg@ziepe.ca> <jgg@nvidia.com>
|
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Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com>
|
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Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com>
|
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<javier@osg.samsung.com> <javier.martinez@collabora.co.uk>
|
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Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com>
|
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Jayachandran C <c.jayachandran@gmail.com> <jayachandranc@netlogicmicro.com>
|
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Jayachandran C <c.jayachandran@gmail.com> <jchandra@broadcom.com>
|
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Jayachandran C <c.jayachandran@gmail.com> <jchandra@digeo.com>
|
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Jayachandran C <c.jayachandran@gmail.com> <jnair@caviumnetworks.com>
|
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Jean Tourrilhes <jt@hpl.hp.com>
|
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<jean-philippe@linaro.org> <jean-philippe.brucker@arm.com>
|
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Jean Tourrilhes <jt@hpl.hp.com>
|
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Jeff Garzik <jgarzik@pretzel.yyz.us>
|
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Jeff Layton <jlayton@kernel.org> <jlayton@redhat.com>
|
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Jeff Layton <jlayton@kernel.org> <jlayton@poochiereds.net>
|
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Jeff Layton <jlayton@kernel.org> <jlayton@primarydata.com>
|
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Jeff Layton <jlayton@kernel.org> <jlayton@redhat.com>
|
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Jens Axboe <axboe@suse.de>
|
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Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
|
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Jiri Slaby <jirislaby@kernel.org> <jirislaby@gmail.com>
|
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@ -164,30 +170,31 @@ Julien Thierry <julien.thierry.kdev@gmail.com> <julien.thierry@arm.com>
|
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Kamil Konieczny <k.konieczny@samsung.com> <k.konieczny@partner.samsung.com>
|
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Kay Sievers <kay.sievers@vrfy.org>
|
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Kenneth W Chen <kenneth.w.chen@intel.com>
|
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Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
|
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Konstantin Khlebnikov <koct9i@gmail.com> <khlebnikov@yandex-team.ru>
|
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Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
|
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Koushik <raghavendra.koushik@neterion.com>
|
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Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski@samsung.com>
|
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Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
|
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Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski@samsung.com>
|
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Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
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Leon Romanovsky <leon@kernel.org> <leon@leon.nu>
|
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Leon Romanovsky <leon@kernel.org> <leonro@mellanox.com>
|
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Leonardo Bras <leobras.c@gmail.com> <leonardo@linux.ibm.com>
|
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Leonid I Ananiev <leonid.i.ananiev@intel.com>
|
||||
Leon Romanovsky <leon@kernel.org> <leon@leon.nu>
|
||||
Leon Romanovsky <leon@kernel.org> <leonro@mellanox.com>
|
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Leon Romanovsky <leon@kernel.org> <leonro@nvidia.com>
|
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Linas Vepstas <linas@austin.ibm.com>
|
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Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
|
||||
Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@ascom.ch>
|
||||
Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org>
|
||||
Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
|
||||
Li Yang <leoyang.li@nxp.com> <leoli@freescale.com>
|
||||
Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org>
|
||||
Lukasz Luba <lukasz.luba@arm.com> <l.luba@partner.samsung.com>
|
||||
Maciej W. Rozycki <macro@mips.com> <macro@imgtec.com>
|
||||
Marc Zyngier <maz@kernel.org> <marc.zyngier@arm.com>
|
||||
Marcin Nowakowski <marcin.nowakowski@mips.com> <marcin.nowakowski@imgtec.com>
|
||||
Marc Zyngier <maz@kernel.org> <marc.zyngier@arm.com>
|
||||
Mark Brown <broonie@sirena.org.uk>
|
||||
Mark Yao <markyao0591@gmail.com> <mark.yao@rock-chips.com>
|
||||
Martin Kepplinger <martink@posteo.de> <martin.kepplinger@theobroma-systems.com>
|
||||
Martin Kepplinger <martink@posteo.de> <martin.kepplinger@ginzinger.com>
|
||||
Martin Kepplinger <martink@posteo.de> <martin.kepplinger@puri.sm>
|
||||
Martin Kepplinger <martink@posteo.de> <martin.kepplinger@theobroma-systems.com>
|
||||
Mathieu Othacehe <m.othacehe@gmail.com>
|
||||
Matthew Wilcox <willy@infradead.org> <matthew.r.wilcox@intel.com>
|
||||
Matthew Wilcox <willy@infradead.org> <matthew@wil.cx>
|
||||
@ -197,17 +204,17 @@ Matthew Wilcox <willy@infradead.org> <willy@debian.org>
|
||||
Matthew Wilcox <willy@infradead.org> <willy@linux.intel.com>
|
||||
Matthew Wilcox <willy@infradead.org> <willy@parisc-linux.org>
|
||||
Matthieu CASTET <castet.matthieu@free.fr>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@brturbo.com.br>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <maurochehab@gmail.com>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@infradead.org>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@redhat.com>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <m.chehab@samsung.com>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@osg.samsung.com>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@s-opensource.com>
|
||||
Matt Ranostay <matt.ranostay@konsulko.com> <matt@ranostay.consulting>
|
||||
Matt Ranostay <mranostay@gmail.com> Matthew Ranostay <mranostay@embeddedalley.com>
|
||||
Matt Ranostay <mranostay@gmail.com> <matt.ranostay@intel.com>
|
||||
Matt Ranostay <matt.ranostay@konsulko.com> <matt@ranostay.consulting>
|
||||
Matt Redfearn <matt.redfearn@mips.com> <matt.redfearn@imgtec.com>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <maurochehab@gmail.com>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@brturbo.com.br>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@infradead.org>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@osg.samsung.com>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@redhat.com>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <m.chehab@samsung.com>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@s-opensource.com>
|
||||
Maxime Ripard <mripard@kernel.org> <maxime.ripard@bootlin.com>
|
||||
Maxime Ripard <mripard@kernel.org> <maxime.ripard@free-electrons.com>
|
||||
Mayuresh Janorkar <mayur@ti.com>
|
||||
@ -239,13 +246,13 @@ Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>
|
||||
Patrick Mochel <mochel@digitalimplant.org>
|
||||
Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
|
||||
Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
|
||||
Paul E. McKenney <paulmck@kernel.org> <paul.mckenney@linaro.org>
|
||||
Paul E. McKenney <paulmck@kernel.org> <paulmck@linux.ibm.com>
|
||||
Paul E. McKenney <paulmck@kernel.org> <paulmck@linux.vnet.ibm.com>
|
||||
Paul E. McKenney <paulmck@kernel.org> <paul.mckenney@linaro.org>
|
||||
Paul E. McKenney <paulmck@kernel.org> <paulmck@us.ibm.com>
|
||||
Peter A Jonsson <pj@ludd.ltu.se>
|
||||
Peter Oruba <peter@oruba.de>
|
||||
Peter Oruba <peter.oruba@amd.com>
|
||||
Peter Oruba <peter@oruba.de>
|
||||
Pratyush Anand <pratyush.anand@gmail.com> <pratyush.anand@st.com>
|
||||
Praveen BP <praveenbp@ti.com>
|
||||
Punit Agrawal <punitagrawal@gmail.com> <punit.agrawal@arm.com>
|
||||
@ -258,23 +265,23 @@ Ralf Baechle <ralf@linux-mips.org>
|
||||
Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
|
||||
Randy Dunlap <rdunlap@infradead.org> <rdunlap@xenotime.net>
|
||||
Rémi Denis-Courmont <rdenis@simphalempin.com>
|
||||
Ricardo Ribalda <ribalda@kernel.org> <ricardo.ribalda@gmail.com>
|
||||
Ricardo Ribalda <ribalda@kernel.org> <ricardo@ribalda.com>
|
||||
Ricardo Ribalda <ribalda@kernel.org> Ricardo Ribalda Delgado <ribalda@kernel.org>
|
||||
Ricardo Ribalda <ribalda@kernel.org> <ricardo.ribalda@gmail.com>
|
||||
Ross Zwisler <zwisler@kernel.org> <ross.zwisler@linux.intel.com>
|
||||
Rudolf Marek <R.Marek@sh.cvut.cz>
|
||||
Rui Saraiva <rmps@joel.ist.utl.pt>
|
||||
Sachin P Sant <ssant@in.ibm.com>
|
||||
Sarangdhar Joshi <spjoshi@codeaurora.org>
|
||||
Sakari Ailus <sakari.ailus@linux.intel.com> <sakari.ailus@iki.fi>
|
||||
Sam Ravnborg <sam@mars.ravnborg.org>
|
||||
Santosh Shilimkar <ssantosh@kernel.org>
|
||||
Santosh Shilimkar <santosh.shilimkar@oracle.org>
|
||||
Santosh Shilimkar <ssantosh@kernel.org>
|
||||
Sarangdhar Joshi <spjoshi@codeaurora.org>
|
||||
Sascha Hauer <s.hauer@pengutronix.de>
|
||||
S.Çağlar Onur <caglar@pardus.org.tr>
|
||||
Sakari Ailus <sakari.ailus@linux.intel.com> <sakari.ailus@iki.fi>
|
||||
Sean Nyekjaer <sean@geanix.com> <sean.nyekjaer@prevas.dk>
|
||||
Sebastian Reichel <sre@kernel.org> <sre@debian.org>
|
||||
Sebastian Reichel <sre@kernel.org> <sebastian.reichel@collabora.co.uk>
|
||||
Sebastian Reichel <sre@kernel.org> <sre@debian.org>
|
||||
Sedat Dilek <sedat.dilek@gmail.com> <sedat.dilek@credativ.de>
|
||||
Shiraz Hashim <shiraz.linux.kernel@gmail.com> <shiraz.hashim@st.com>
|
||||
Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com>
|
||||
@ -285,18 +292,21 @@ Simon Arlott <simon@octiron.net> <simon@fire.lp0.eu>
|
||||
Simon Kelley <simon@thekelleys.org.uk>
|
||||
Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
|
||||
Stephen Hemminger <shemminger@osdl.org>
|
||||
Steve Wise <larrystevenwise@gmail.com> <swise@chelsio.com>
|
||||
Steve Wise <larrystevenwise@gmail.com> <swise@opengridcomputing.com>
|
||||
Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
|
||||
Subhash Jadavani <subhashj@codeaurora.org>
|
||||
Sudeep Holla <sudeep.holla@arm.com> Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
|
||||
Sumit Semwal <sumit.semwal@ti.com>
|
||||
Takashi YOSHII <takashi.yoshii.zj@renesas.com>
|
||||
Tejun Heo <htejun@gmail.com>
|
||||
Thomas Graf <tgraf@suug.ch>
|
||||
Thomas Pedersen <twp@codeaurora.org>
|
||||
Tiezhu Yang <yangtiezhu@loongson.cn> <kernelpatch@126.com>
|
||||
Todor Tomov <todor.too@gmail.com> <todor.tomov@linaro.org>
|
||||
Tony Luck <tony.luck@intel.com>
|
||||
TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn>
|
||||
TripleX Chung <xxx.phy@gmail.com> <triplex@zh-kernel.org>
|
||||
TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn>
|
||||
Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com>
|
||||
Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
|
||||
Uwe Kleine-König <ukl@pengutronix.de>
|
||||
@ -305,22 +315,16 @@ Valdis Kletnieks <Valdis.Kletnieks@vt.edu>
|
||||
Vinod Koul <vkoul@kernel.org> <vinod.koul@intel.com>
|
||||
Vinod Koul <vkoul@kernel.org> <vinod.koul@linux.intel.com>
|
||||
Vinod Koul <vkoul@kernel.org> <vkoul@infradead.org>
|
||||
Viresh Kumar <vireshk@kernel.org> <viresh.kumar2@arm.com>
|
||||
Viresh Kumar <vireshk@kernel.org> <viresh.kumar@st.com>
|
||||
Viresh Kumar <vireshk@kernel.org> <viresh.linux@gmail.com>
|
||||
Viresh Kumar <vireshk@kernel.org> <viresh.kumar2@arm.com>
|
||||
Vivien Didelot <vivien.didelot@gmail.com> <vivien.didelot@savoirfairelinux.com>
|
||||
Vlad Dogaru <ddvlad@gmail.com> <vlad.dogaru@intel.com>
|
||||
Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@virtuozzo.com>
|
||||
Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@parallels.com>
|
||||
Takashi YOSHII <takashi.yoshii.zj@renesas.com>
|
||||
Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@virtuozzo.com>
|
||||
WeiXiong Liao <gmpy.liaowx@gmail.com> <liaoweixiong@allwinnertech.com>
|
||||
Will Deacon <will@kernel.org> <will.deacon@arm.com>
|
||||
Wolfram Sang <wsa@kernel.org> <wsa@the-dreams.de>
|
||||
Wolfram Sang <wsa@kernel.org> <w.sang@pengutronix.de>
|
||||
Wolfram Sang <wsa@kernel.org> <wsa@the-dreams.de>
|
||||
Yakir Yang <kuankuan.y@gmail.com> <ykk@rock-chips.com>
|
||||
Yusuke Goda <goda.yusuke@renesas.com>
|
||||
Gustavo Padovan <gustavo@las.ic.unicamp.br>
|
||||
Gustavo Padovan <padovan@profusion.mobi>
|
||||
Changbin Du <changbin.du@intel.com> <changbin.du@intel.com>
|
||||
Changbin Du <changbin.du@intel.com> <changbin.du@gmail.com>
|
||||
Steve Wise <larrystevenwise@gmail.com> <swise@chelsio.com>
|
||||
Steve Wise <larrystevenwise@gmail.com> <swise@opengridcomputing.com>
|
||||
|
||||
@ -43,7 +43,7 @@ Description: read only
|
||||
This sysfs interface exposes the number of cores per chip
|
||||
present in the system.
|
||||
|
||||
What: /sys/devices/hv_24x7/interface/cpumask
|
||||
What: /sys/devices/hv_24x7/cpumask
|
||||
Date: July 2020
|
||||
Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
|
||||
Description: read only
|
||||
|
||||
@ -489,6 +489,9 @@ Files in /sys/fs/ext4/<devname>:
|
||||
multiple of this tuning parameter if the stripe size is not set in the
|
||||
ext4 superblock
|
||||
|
||||
mb_max_inode_prealloc
|
||||
The maximum length of per-inode ext4_prealloc_space list.
|
||||
|
||||
mb_max_to_scan
|
||||
The maximum number of extents the multiblock allocator will search to
|
||||
find the best extent.
|
||||
@ -529,21 +532,21 @@ Files in /sys/fs/ext4/<devname>:
|
||||
Ioctls
|
||||
======
|
||||
|
||||
There is some Ext4 specific functionality which can be accessed by applications
|
||||
through the system call interfaces. The list of all Ext4 specific ioctls are
|
||||
shown in the table below.
|
||||
Ext4 implements various ioctls which can be used by applications to access
|
||||
ext4-specific functionality. An incomplete list of these ioctls is shown in the
|
||||
table below. This list includes truly ext4-specific ioctls (``EXT4_IOC_*``) as
|
||||
well as ioctls that may have been ext4-specific originally but are now supported
|
||||
by some other filesystem(s) too (``FS_IOC_*``).
|
||||
|
||||
Table of Ext4 specific ioctls
|
||||
Table of Ext4 ioctls
|
||||
|
||||
EXT4_IOC_GETFLAGS
|
||||
FS_IOC_GETFLAGS
|
||||
Get additional attributes associated with inode. The ioctl argument is
|
||||
an integer bitfield, with bit values described in ext4.h. This ioctl is
|
||||
an alias for FS_IOC_GETFLAGS.
|
||||
an integer bitfield, with bit values described in ext4.h.
|
||||
|
||||
EXT4_IOC_SETFLAGS
|
||||
FS_IOC_SETFLAGS
|
||||
Set additional attributes associated with inode. The ioctl argument is
|
||||
an integer bitfield, with bit values described in ext4.h. This ioctl is
|
||||
an alias for FS_IOC_SETFLAGS.
|
||||
an integer bitfield, with bit values described in ext4.h.
|
||||
|
||||
EXT4_IOC_GETVERSION, EXT4_IOC_GETVERSION_OLD
|
||||
Get the inode i_generation number stored for each inode. The
|
||||
|
||||
@ -1233,8 +1233,7 @@
|
||||
efi= [EFI]
|
||||
Format: { "debug", "disable_early_pci_dma",
|
||||
"nochunk", "noruntime", "nosoftreserve",
|
||||
"novamap", "no_disable_early_pci_dma",
|
||||
"old_map" }
|
||||
"novamap", "no_disable_early_pci_dma" }
|
||||
debug: enable misc debug output.
|
||||
disable_early_pci_dma: disable the busmaster bit on all
|
||||
PCI bridges while in the EFI boot stub.
|
||||
@ -1251,8 +1250,6 @@
|
||||
novamap: do not call SetVirtualAddressMap().
|
||||
no_disable_early_pci_dma: Leave the busmaster bit set
|
||||
on all PCI bridges while in the EFI boot stub
|
||||
old_map [X86-64]: switch to the old ioremap-based EFI
|
||||
runtime services mapping. [Needs CONFIG_X86_UV=y]
|
||||
|
||||
efi_no_storage_paranoia [EFI; X86]
|
||||
Using this parameter you can use more than 50% of
|
||||
|
||||
@ -564,8 +564,8 @@ Energy-Performance Preference (EPP) knob (if supported) or its
|
||||
Energy-Performance Bias (EPB) knob. It is also possible to write a positive
|
||||
integer value between 0 to 255, if the EPP feature is present. If the EPP
|
||||
feature is not present, writing integer value to this attribute is not
|
||||
supported. In this case, user can use
|
||||
"/sys/devices/system/cpu/cpu*/power/energy_perf_bias" interface.
|
||||
supported. In this case, user can use the
|
||||
"/sys/devices/system/cpu/cpu*/power/energy_perf_bias" interface.
|
||||
|
||||
[Note that tasks may by migrated from one CPU to another by the scheduler's
|
||||
load-balancing algorithm and if different energy vs performance hints are
|
||||
|
||||
@ -36,6 +36,12 @@ Two sets of Questions and Answers (Q&A) are maintained.
|
||||
bpf_devel_QA
|
||||
|
||||
|
||||
Helper functions
|
||||
================
|
||||
|
||||
* `bpf-helpers(7)`_ maintains a list of helpers available to eBPF programs.
|
||||
|
||||
|
||||
Program types
|
||||
=============
|
||||
|
||||
@ -79,4 +85,5 @@ Other
|
||||
.. _networking-filter: ../networking/filter.rst
|
||||
.. _man-pages: https://www.kernel.org/doc/man-pages/
|
||||
.. _bpf(2): https://man7.org/linux/man-pages/man2/bpf.2.html
|
||||
.. _bpf-helpers(7): https://man7.org/linux/man-pages/man7/bpf-helpers.7.html
|
||||
.. _BPF and XDP Reference Guide: https://docs.cilium.io/en/latest/bpf/
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Clock bindings for Freescale i.MX23
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Clock bindings for Freescale i.MX28
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Freescale MXS GPIO controller
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description: |
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Freescale MXS Inter IC (I2C) Controller
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -1,66 +0,0 @@
|
||||
Texas Instruments K3 Interrupt Aggregator
|
||||
=========================================
|
||||
|
||||
The Interrupt Aggregator (INTA) provides a centralized machine
|
||||
which handles the termination of system events to that they can
|
||||
be coherently processed by the host(s) in the system. A maximum
|
||||
of 64 events can be mapped to a single interrupt.
|
||||
|
||||
|
||||
Interrupt Aggregator
|
||||
+-----------------------------------------+
|
||||
| Intmap VINT |
|
||||
| +--------------+ +------------+ |
|
||||
m ------>| | vint | bit | | 0 |.....|63| vint0 |
|
||||
. | +--------------+ +------------+ | +------+
|
||||
. | . . | | HOST |
|
||||
Globalevents ------>| . . |------>| IRQ |
|
||||
. | . . | | CTRL |
|
||||
. | . . | +------+
|
||||
n ------>| +--------------+ +------------+ |
|
||||
| | vint | bit | | 0 |.....|63| vintx |
|
||||
| +--------------+ +------------+ |
|
||||
| |
|
||||
+-----------------------------------------+
|
||||
|
||||
Configuration of these Intmap registers that maps global events to vint is done
|
||||
by a system controller (like the Device Memory and Security Controller on K3
|
||||
AM654 SoC). Driver should request the system controller to get the range
|
||||
of global events and vints assigned to the requesting host. Management
|
||||
of these requested resources should be handled by driver and requests
|
||||
system controller to map specific global event to vint, bit pair.
|
||||
|
||||
Communication between the host processor running an OS and the system
|
||||
controller happens through a protocol called TI System Control Interface
|
||||
(TISCI protocol). For more details refer:
|
||||
Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
|
||||
|
||||
TISCI Interrupt Aggregator Node:
|
||||
-------------------------------
|
||||
- compatible: Must be "ti,sci-inta".
|
||||
- reg: Should contain registers location and length.
|
||||
- interrupt-controller: Identifies the node as an interrupt controller
|
||||
- msi-controller: Identifies the node as an MSI controller.
|
||||
- interrupt-parent: phandle of irq parent.
|
||||
- ti,sci: Phandle to TI-SCI compatible System controller node.
|
||||
- ti,sci-dev-id: TISCI device ID of the Interrupt Aggregator.
|
||||
- ti,sci-rm-range-vint: Array of TISCI subtype ids representing vints(inta
|
||||
outputs) range within this INTA, assigned to the
|
||||
requesting host context.
|
||||
- ti,sci-rm-range-global-event: Array of TISCI subtype ids representing the
|
||||
global events range reaching this IA and are assigned
|
||||
to the requesting host context.
|
||||
|
||||
Example:
|
||||
--------
|
||||
main_udmass_inta: interrupt-controller@33d00000 {
|
||||
compatible = "ti,sci-inta";
|
||||
reg = <0x0 0x33d00000 0x0 0x100000>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <179>;
|
||||
ti,sci-rm-range-vint = <0x0>;
|
||||
ti,sci-rm-range-global-event = <0x1>;
|
||||
};
|
||||
@ -0,0 +1,98 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments K3 Interrupt Aggregator
|
||||
|
||||
maintainers:
|
||||
- Lokesh Vutla <lokeshvutla@ti.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
|
||||
|
||||
description: |
|
||||
The Interrupt Aggregator (INTA) provides a centralized machine
|
||||
which handles the termination of system events to that they can
|
||||
be coherently processed by the host(s) in the system. A maximum
|
||||
of 64 events can be mapped to a single interrupt.
|
||||
|
||||
Interrupt Aggregator
|
||||
+-----------------------------------------+
|
||||
| Intmap VINT |
|
||||
| +--------------+ +------------+ |
|
||||
m ------>| | vint | bit | | 0 |.....|63| vint0 |
|
||||
. | +--------------+ +------------+ | +------+
|
||||
. | . . | | HOST |
|
||||
Globalevents ------>| . . |----->| IRQ |
|
||||
. | . . | | CTRL |
|
||||
. | . . | +------+
|
||||
n ------>| +--------------+ +------------+ |
|
||||
| | vint | bit | | 0 |.....|63| vintx |
|
||||
| +--------------+ +------------+ |
|
||||
| |
|
||||
+-----------------------------------------+
|
||||
|
||||
Configuration of these Intmap registers that maps global events to vint is
|
||||
done by a system controller (like the Device Memory and Security Controller
|
||||
on AM654 SoC). Driver should request the system controller to get the range
|
||||
of global events and vints assigned to the requesting host. Management
|
||||
of these requested resources should be handled by driver and requests
|
||||
system controller to map specific global event to vint, bit pair.
|
||||
|
||||
Communication between the host processor running an OS and the system
|
||||
controller happens through a protocol called TI System Control Interface
|
||||
(TISCI protocol).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ti,sci-inta
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
msi-controller: true
|
||||
|
||||
ti,interrupt-ranges:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
description: |
|
||||
Interrupt ranges that converts the INTA output hw irq numbers
|
||||
to parents's input interrupt numbers.
|
||||
items:
|
||||
items:
|
||||
- description: |
|
||||
"output_irq" specifies the base for inta output irq
|
||||
- description: |
|
||||
"parent's input irq" specifies the base for parent irq
|
||||
- description: |
|
||||
"limit" specifies the limit for translation
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupt-controller
|
||||
- msi-controller
|
||||
- ti,sci
|
||||
- ti,sci-dev-id
|
||||
- ti,interrupt-ranges
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
main_udmass_inta: msi-controller@33d00000 {
|
||||
compatible = "ti,sci-inta";
|
||||
reg = <0x0 0x33d00000 0x0 0x100000>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <179>;
|
||||
ti,interrupt-ranges = <0 0 256>;
|
||||
};
|
||||
};
|
||||
@ -1,82 +0,0 @@
|
||||
Texas Instruments K3 Interrupt Router
|
||||
=====================================
|
||||
|
||||
The Interrupt Router (INTR) module provides a mechanism to mux M
|
||||
interrupt inputs to N interrupt outputs, where all M inputs are selectable
|
||||
to be driven per N output. An Interrupt Router can either handle edge triggered
|
||||
or level triggered interrupts and that is fixed in hardware.
|
||||
|
||||
Interrupt Router
|
||||
+----------------------+
|
||||
| Inputs Outputs |
|
||||
+-------+ | +------+ +-----+ |
|
||||
| GPIO |----------->| | irq0 | | 0 | | Host IRQ
|
||||
+-------+ | +------+ +-----+ | controller
|
||||
| . . | +-------+
|
||||
+-------+ | . . |----->| IRQ |
|
||||
| INTA |----------->| . . | +-------+
|
||||
+-------+ | . +-----+ |
|
||||
| +------+ | N | |
|
||||
| | irqM | +-----+ |
|
||||
| +------+ |
|
||||
| |
|
||||
+----------------------+
|
||||
|
||||
There is one register per output (MUXCNTL_N) that controls the selection.
|
||||
Configuration of these MUXCNTL_N registers is done by a system controller
|
||||
(like the Device Memory and Security Controller on K3 AM654 SoC). System
|
||||
controller will keep track of the used and unused registers within the Router.
|
||||
Driver should request the system controller to get the range of GIC IRQs
|
||||
assigned to the requesting hosts. It is the drivers responsibility to keep
|
||||
track of Host IRQs.
|
||||
|
||||
Communication between the host processor running an OS and the system
|
||||
controller happens through a protocol called TI System Control Interface
|
||||
(TISCI protocol). For more details refer:
|
||||
Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
|
||||
|
||||
TISCI Interrupt Router Node:
|
||||
----------------------------
|
||||
Required Properties:
|
||||
- compatible: Must be "ti,sci-intr".
|
||||
- ti,intr-trigger-type: Should be one of the following:
|
||||
1: If intr supports edge triggered interrupts.
|
||||
4: If intr supports level triggered interrupts.
|
||||
- interrupt-controller: Identifies the node as an interrupt controller
|
||||
- #interrupt-cells: Specifies the number of cells needed to encode an
|
||||
interrupt source. The value should be 2.
|
||||
First cell should contain the TISCI device ID of source
|
||||
Second cell should contain the interrupt source offset
|
||||
within the device.
|
||||
- ti,sci: Phandle to TI-SCI compatible System controller node.
|
||||
- ti,sci-dst-id: TISCI device ID of the destination IRQ controller.
|
||||
- ti,sci-rm-range-girq: Array of TISCI subtype ids representing the host irqs
|
||||
assigned to this interrupt router. Each subtype id
|
||||
corresponds to a range of host irqs.
|
||||
|
||||
For more details on TISCI IRQ resource management refer:
|
||||
https://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html
|
||||
|
||||
Example:
|
||||
--------
|
||||
The following example demonstrates both interrupt router node and the consumer
|
||||
node(main gpio) on the AM654 SoC:
|
||||
|
||||
main_intr: interrupt-controller0 {
|
||||
compatible = "ti,sci-intr";
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <56>;
|
||||
ti,sci-rm-range-girq = <0x1>;
|
||||
};
|
||||
|
||||
main_gpio0: gpio@600000 {
|
||||
...
|
||||
interrupt-parent = <&main_intr>;
|
||||
interrupts = <57 256>, <57 257>, <57 258>,
|
||||
<57 259>, <57 260>, <57 261>;
|
||||
...
|
||||
};
|
||||
@ -0,0 +1,102 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments K3 Interrupt Router
|
||||
|
||||
maintainers:
|
||||
- Lokesh Vutla <lokeshvutla@ti.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
|
||||
|
||||
description: |
|
||||
The Interrupt Router (INTR) module provides a mechanism to mux M
|
||||
interrupt inputs to N interrupt outputs, where all M inputs are selectable
|
||||
to be driven per N output. An Interrupt Router can either handle edge
|
||||
triggered or level triggered interrupts and that is fixed in hardware.
|
||||
|
||||
Interrupt Router
|
||||
+----------------------+
|
||||
| Inputs Outputs |
|
||||
+-------+ | +------+ +-----+ |
|
||||
| GPIO |----------->| | irq0 | | 0 | | Host IRQ
|
||||
+-------+ | +------+ +-----+ | controller
|
||||
| . . | +-------+
|
||||
+-------+ | . . |----->| IRQ |
|
||||
| INTA |----------->| . . | +-------+
|
||||
+-------+ | . +-----+ |
|
||||
| +------+ | N | |
|
||||
| | irqM | +-----+ |
|
||||
| +------+ |
|
||||
| |
|
||||
+----------------------+
|
||||
|
||||
There is one register per output (MUXCNTL_N) that controls the selection.
|
||||
Configuration of these MUXCNTL_N registers is done by a system controller
|
||||
(like the Device Memory and Security Controller on K3 AM654 SoC). System
|
||||
controller will keep track of the used and unused registers within the Router.
|
||||
Driver should request the system controller to get the range of GIC IRQs
|
||||
assigned to the requesting hosts. It is the drivers responsibility to keep
|
||||
track of Host IRQs.
|
||||
|
||||
Communication between the host processor running an OS and the system
|
||||
controller happens through a protocol called TI System Control Interface
|
||||
(TISCI protocol).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ti,sci-intr
|
||||
|
||||
ti,intr-trigger-type:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 4]
|
||||
description: |
|
||||
Should be one of the following.
|
||||
1 = If intr supports edge triggered interrupts.
|
||||
4 = If intr supports level triggered interrupts.
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 1
|
||||
description: |
|
||||
The 1st cell should contain interrupt router input hw number.
|
||||
|
||||
ti,interrupt-ranges:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
description: |
|
||||
Interrupt ranges that converts the INTR output hw irq numbers
|
||||
to parents's input interrupt numbers.
|
||||
items:
|
||||
items:
|
||||
- description: |
|
||||
"output_irq" specifies the base for intr output irq
|
||||
- description: |
|
||||
"parent's input irq" specifies the base for parent irq
|
||||
- description: |
|
||||
"limit" specifies the limit for translation
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- ti,intr-trigger-type
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- ti,sci
|
||||
- ti,sci-dev-id
|
||||
- ti,interrupt-ranges
|
||||
|
||||
examples:
|
||||
- |
|
||||
main_gpio_intr: interrupt-controller0 {
|
||||
compatible = "ti,sci-intr";
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <131>;
|
||||
ti,interrupt-ranges = <0 360 32>;
|
||||
};
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Freescale MXS MMC controller
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
|
||||
description: |
|
||||
The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller
|
||||
|
||||
@ -54,7 +54,8 @@ properties:
|
||||
|
||||
phy-connection-type:
|
||||
description:
|
||||
Operation mode of the PHY interface
|
||||
Specifies interface type between the Ethernet device and a physical
|
||||
layer (PHY) device.
|
||||
enum:
|
||||
# There is not a standard bus between the MAC and the PHY,
|
||||
# something proprietary is being used to embed the PHY in the
|
||||
|
||||
@ -59,9 +59,15 @@ properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
pinctrl-0: true
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
pinctrl-names: true
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
phy-mode: true
|
||||
|
||||
phy-handle: true
|
||||
|
||||
renesas,no-ether-link:
|
||||
type: boolean
|
||||
@ -74,6 +80,11 @@ properties:
|
||||
specify when the Ether LINK signal is active-low instead of normal
|
||||
active-high
|
||||
|
||||
patternProperties:
|
||||
"^ethernet-phy@[0-9a-f]$":
|
||||
type: object
|
||||
$ref: ethernet-phy.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -83,7 +94,8 @@ required:
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
- clocks
|
||||
- pinctrl-0
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Lager board
|
||||
@ -99,8 +111,6 @@ examples:
|
||||
clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&phy1>;
|
||||
pinctrl-0 = <ðer_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,ether-link-active-low;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -109,7 +119,5 @@ examples:
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-0 = <&phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
@ -9,6 +9,14 @@ title: PCIe RC controller on Intel Gateway SoCs
|
||||
maintainers:
|
||||
- Dilip Kota <eswara.kota@linux.intel.com>
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: intel,lgm-pcie
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Freescale MXS PWM controller
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
- Anson Huang <anson.huang@nxp.com>
|
||||
|
||||
properties:
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Freescale (Enhanced) Configurable Serial Peripheral Interface (CSPI/eCSPI) for i.MX
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: "/schemas/spi/spi-controller.yaml#"
|
||||
|
||||
@ -39,6 +39,7 @@ properties:
|
||||
spi common code does not support use of CS signals discontinuously.
|
||||
i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add
|
||||
this property to re-config the chipselect value in the LPSPI driver.
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: NXP i.MX Thermal Binding
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
properties:
|
||||
|
||||
60
Documentation/devicetree/bindings/timer/sifive,clint.yaml
Normal file
60
Documentation/devicetree/bindings/timer/sifive,clint.yaml
Normal file
@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SiFive Core Local Interruptor
|
||||
|
||||
maintainers:
|
||||
- Palmer Dabbelt <palmer@dabbelt.com>
|
||||
- Anup Patel <anup.patel@wdc.com>
|
||||
|
||||
description:
|
||||
SiFive (and other RISC-V) SOCs include an implementation of the SiFive
|
||||
Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
|
||||
interrupts. It directly connects to the timer and inter-processor interrupt
|
||||
lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
|
||||
interrupt controller is the parent interrupt controller for CLINT device.
|
||||
The clock frequency of CLINT is specified via "timebase-frequency" DT
|
||||
property of "/cpus" DT node. The "timebase-frequency" DT property is
|
||||
described in Documentation/devicetree/bindings/riscv/cpus.yaml
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: sifive,fu540-c000-clint
|
||||
- const: sifive,clint0
|
||||
|
||||
description:
|
||||
Should be "sifive,<chip>-clint" and "sifive,clint<version>".
|
||||
Supported compatible strings are -
|
||||
"sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
|
||||
onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive
|
||||
CLINT v0 IP block with no chip integration tweaks.
|
||||
Please refer to sifive-blocks-ip-versioning.txt for details
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts-extended:
|
||||
minItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts-extended
|
||||
|
||||
examples:
|
||||
- |
|
||||
timer@2000000 {
|
||||
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
|
||||
interrupts-extended = <&cpu1intc 3 &cpu1intc 7
|
||||
&cpu2intc 3 &cpu2intc 7
|
||||
&cpu3intc 3 &cpu3intc 7
|
||||
&cpu4intc 3 &cpu4intc 7>;
|
||||
reg = <0x2000000 0x10000>;
|
||||
};
|
||||
...
|
||||
@ -5,7 +5,7 @@ Writing DeviceTree Bindings in json-schema
|
||||
|
||||
Devicetree bindings are written using json-schema vocabulary. Schema files are
|
||||
written in a JSON compatible subset of YAML. YAML is used instead of JSON as it
|
||||
considered more human readable and has some advantages such as allowing
|
||||
is considered more human readable and has some advantages such as allowing
|
||||
comments (Prefixed with '#').
|
||||
|
||||
Schema Contents
|
||||
@ -19,7 +19,7 @@ $id
|
||||
A json-schema unique identifier string. The string must be a valid
|
||||
URI typically containing the binding's filename and path. For DT schema, it must
|
||||
begin with "http://devicetree.org/schemas/". The URL is used in constructing
|
||||
references to other files specified in schema "$ref" properties. A $ref values
|
||||
references to other files specified in schema "$ref" properties. A $ref value
|
||||
with a leading '/' will have the hostname prepended. A $ref value a relative
|
||||
path or filename only will be prepended with the hostname and path components
|
||||
of the current schema file's '$id' value. A URL is used even for local files,
|
||||
|
||||
@ -3,7 +3,7 @@ NVMe Fault Injection
|
||||
Linux's fault injection framework provides a systematic way to support
|
||||
error injection via debugfs in the /sys/kernel/debug directory. When
|
||||
enabled, the default NVME_SC_INVALID_OPCODE with no retry will be
|
||||
injected into the nvme_end_request. Users can change the default status
|
||||
injected into the nvme_try_complete_req. Users can change the default status
|
||||
code and no retry flag via the debugfs. The list of Generic Command
|
||||
Status can be found in include/linux/nvme.h
|
||||
|
||||
|
||||
@ -39,6 +39,6 @@ entry.
|
||||
Other References
|
||||
----------------
|
||||
|
||||
Also see http://www.nongnu.org/ext2-doc/ for quite a collection of
|
||||
Also see https://www.nongnu.org/ext2-doc/ for quite a collection of
|
||||
information about ext2/3. Here's another old reference:
|
||||
http://wiki.osdev.org/Ext2
|
||||
|
||||
@ -2860,17 +2860,6 @@ version of the linux kernel, found on http://kernel.org
|
||||
The latest version of this document can be found in the latest kernel
|
||||
source (named Documentation/networking/bonding.rst).
|
||||
|
||||
Discussions regarding the usage of the bonding driver take place on the
|
||||
bonding-devel mailing list, hosted at sourceforge.net. If you have questions or
|
||||
problems, post them to the list. The list address is:
|
||||
|
||||
bonding-devel@lists.sourceforge.net
|
||||
|
||||
The administrative interface (to subscribe or unsubscribe) can
|
||||
be found at:
|
||||
|
||||
https://lists.sourceforge.net/lists/listinfo/bonding-devel
|
||||
|
||||
Discussions regarding the development of the bonding driver take place
|
||||
on the main Linux network mailing list, hosted at vger.kernel.org. The list
|
||||
address is:
|
||||
@ -2881,10 +2870,3 @@ The administrative interface (to subscribe or unsubscribe) can
|
||||
be found at:
|
||||
|
||||
http://vger.kernel.org/vger-lists.html#netdev
|
||||
|
||||
Donald Becker's Ethernet Drivers and diag programs may be found at :
|
||||
|
||||
- http://web.archive.org/web/%2E/http://www.scyld.com/network/
|
||||
|
||||
You will also find a lot of information regarding Ethernet, NWay, MII,
|
||||
etc. at www.scyld.com.
|
||||
|
||||
@ -49,16 +49,18 @@ Register preservation rules
|
||||
Register preservation rules match the ELF ABI calling sequence with the
|
||||
following differences:
|
||||
|
||||
=========== ============= ========================================
|
||||
--- For the sc instruction, differences with the ELF ABI ---
|
||||
=========== ============= ========================================
|
||||
r0 Volatile (System call number.)
|
||||
r3 Volatile (Parameter 1, and return value.)
|
||||
r4-r8 Volatile (Parameters 2-6.)
|
||||
cr0 Volatile (cr0.SO is the return error condition.)
|
||||
cr1, cr5-7 Nonvolatile
|
||||
lr Nonvolatile
|
||||
=========== ============= ========================================
|
||||
|
||||
--- For the scv 0 instruction, differences with the ELF ABI ---
|
||||
=========== ============= ========================================
|
||||
r0 Volatile (System call number.)
|
||||
r3 Volatile (Parameter 1, and return value.)
|
||||
r4-r8 Volatile (Parameters 2-6.)
|
||||
|
||||
72
MAINTAINERS
72
MAINTAINERS
@ -3205,6 +3205,7 @@ S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git
|
||||
F: block/
|
||||
F: drivers/block/
|
||||
F: include/linux/blk*
|
||||
F: kernel/trace/blktrace.c
|
||||
F: lib/sbitmap.c
|
||||
|
||||
@ -5050,7 +5051,7 @@ F: include/linux/dm-*.h
|
||||
F: include/uapi/linux/dm-*.h
|
||||
|
||||
DEVLINK
|
||||
M: Jiri Pirko <jiri@mellanox.com>
|
||||
M: Jiri Pirko <jiri@nvidia.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/networking/devlink
|
||||
@ -6081,7 +6082,7 @@ F: include/linux/dynamic_debug.h
|
||||
F: lib/dynamic_debug.c
|
||||
|
||||
DYNAMIC INTERRUPT MODERATION
|
||||
M: Tal Gilboa <talgi@mellanox.com>
|
||||
M: Tal Gilboa <talgi@nvidia.com>
|
||||
S: Maintained
|
||||
F: Documentation/networking/net_dim.rst
|
||||
F: include/linux/dim.h
|
||||
@ -6161,7 +6162,7 @@ F: Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
|
||||
F: drivers/edac/aspeed_edac.c
|
||||
|
||||
EDAC-BLUEFIELD
|
||||
M: Shravan Kumar Ramani <sramani@mellanox.com>
|
||||
M: Shravan Kumar Ramani <sramani@nvidia.com>
|
||||
S: Supported
|
||||
F: drivers/edac/bluefield_edac.c
|
||||
|
||||
@ -6483,8 +6484,8 @@ S: Odd Fixes
|
||||
F: drivers/net/ethernet/agere/
|
||||
|
||||
ETHERNET BRIDGE
|
||||
M: Roopa Prabhu <roopa@cumulusnetworks.com>
|
||||
M: Nikolay Aleksandrov <nikolay@cumulusnetworks.com>
|
||||
M: Roopa Prabhu <roopa@nvidia.com>
|
||||
M: Nikolay Aleksandrov <nikolay@nvidia.com>
|
||||
L: bridge@lists.linux-foundation.org (moderated for non-subscribers)
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
@ -6599,7 +6600,7 @@ F: drivers/iommu/exynos-iommu.c
|
||||
|
||||
EZchip NPS platform support
|
||||
M: Vineet Gupta <vgupta@synopsys.com>
|
||||
M: Ofer Levi <oferle@mellanox.com>
|
||||
M: Ofer Levi <oferle@nvidia.com>
|
||||
S: Supported
|
||||
F: arch/arc/boot/dts/eznps.dts
|
||||
F: arch/arc/plat-eznps
|
||||
@ -8563,7 +8564,7 @@ F: drivers/iio/pressure/dps310.c
|
||||
|
||||
INFINIBAND SUBSYSTEM
|
||||
M: Doug Ledford <dledford@redhat.com>
|
||||
M: Jason Gunthorpe <jgg@mellanox.com>
|
||||
M: Jason Gunthorpe <jgg@nvidia.com>
|
||||
L: linux-rdma@vger.kernel.org
|
||||
S: Supported
|
||||
W: https://github.com/linux-rdma/rdma-core
|
||||
@ -9226,7 +9227,7 @@ F: drivers/firmware/iscsi_ibft*
|
||||
|
||||
ISCSI EXTENSIONS FOR RDMA (ISER) INITIATOR
|
||||
M: Sagi Grimberg <sagi@grimberg.me>
|
||||
M: Max Gurtovoy <maxg@mellanox.com>
|
||||
M: Max Gurtovoy <maxg@nvidia.com>
|
||||
L: linux-rdma@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://www.openfabrics.org
|
||||
@ -11072,7 +11073,7 @@ F: Documentation/devicetree/bindings/input/touchscreen/melfas_mip4.txt
|
||||
F: drivers/input/touchscreen/melfas_mip4.c
|
||||
|
||||
MELLANOX ETHERNET DRIVER (mlx4_en)
|
||||
M: Tariq Toukan <tariqt@mellanox.com>
|
||||
M: Tariq Toukan <tariqt@nvidia.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://www.mellanox.com
|
||||
@ -11080,7 +11081,7 @@ Q: http://patchwork.ozlabs.org/project/netdev/list/
|
||||
F: drivers/net/ethernet/mellanox/mlx4/en_*
|
||||
|
||||
MELLANOX ETHERNET DRIVER (mlx5e)
|
||||
M: Saeed Mahameed <saeedm@mellanox.com>
|
||||
M: Saeed Mahameed <saeedm@nvidia.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://www.mellanox.com
|
||||
@ -11088,7 +11089,7 @@ Q: http://patchwork.ozlabs.org/project/netdev/list/
|
||||
F: drivers/net/ethernet/mellanox/mlx5/core/en_*
|
||||
|
||||
MELLANOX ETHERNET INNOVA DRIVERS
|
||||
R: Boris Pismenny <borisp@mellanox.com>
|
||||
R: Boris Pismenny <borisp@nvidia.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://www.mellanox.com
|
||||
@ -11099,8 +11100,8 @@ F: drivers/net/ethernet/mellanox/mlx5/core/fpga/*
|
||||
F: include/linux/mlx5/mlx5_ifc_fpga.h
|
||||
|
||||
MELLANOX ETHERNET SWITCH DRIVERS
|
||||
M: Jiri Pirko <jiri@mellanox.com>
|
||||
M: Ido Schimmel <idosch@mellanox.com>
|
||||
M: Jiri Pirko <jiri@nvidia.com>
|
||||
M: Ido Schimmel <idosch@nvidia.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://www.mellanox.com
|
||||
@ -11109,7 +11110,7 @@ F: drivers/net/ethernet/mellanox/mlxsw/
|
||||
F: tools/testing/selftests/drivers/net/mlxsw/
|
||||
|
||||
MELLANOX FIRMWARE FLASH LIBRARY (mlxfw)
|
||||
M: mlxsw@mellanox.com
|
||||
M: mlxsw@nvidia.com
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://www.mellanox.com
|
||||
@ -11119,7 +11120,7 @@ F: drivers/net/ethernet/mellanox/mlxfw/
|
||||
MELLANOX HARDWARE PLATFORM SUPPORT
|
||||
M: Andy Shevchenko <andy@infradead.org>
|
||||
M: Darren Hart <dvhart@infradead.org>
|
||||
M: Vadim Pasternak <vadimp@mellanox.com>
|
||||
M: Vadim Pasternak <vadimp@nvidia.com>
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/ABI/testing/sysfs-platform-mellanox-bootctl
|
||||
@ -11127,7 +11128,7 @@ F: drivers/platform/mellanox/
|
||||
F: include/linux/platform_data/mlxreg.h
|
||||
|
||||
MELLANOX MLX4 core VPI driver
|
||||
M: Tariq Toukan <tariqt@mellanox.com>
|
||||
M: Tariq Toukan <tariqt@nvidia.com>
|
||||
L: netdev@vger.kernel.org
|
||||
L: linux-rdma@vger.kernel.org
|
||||
S: Supported
|
||||
@ -11137,7 +11138,7 @@ F: drivers/net/ethernet/mellanox/mlx4/
|
||||
F: include/linux/mlx4/
|
||||
|
||||
MELLANOX MLX4 IB driver
|
||||
M: Yishai Hadas <yishaih@mellanox.com>
|
||||
M: Yishai Hadas <yishaih@nvidia.com>
|
||||
L: linux-rdma@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://www.mellanox.com
|
||||
@ -11147,8 +11148,8 @@ F: include/linux/mlx4/
|
||||
F: include/uapi/rdma/mlx4-abi.h
|
||||
|
||||
MELLANOX MLX5 core VPI driver
|
||||
M: Saeed Mahameed <saeedm@mellanox.com>
|
||||
M: Leon Romanovsky <leonro@mellanox.com>
|
||||
M: Saeed Mahameed <saeedm@nvidia.com>
|
||||
M: Leon Romanovsky <leonro@nvidia.com>
|
||||
L: netdev@vger.kernel.org
|
||||
L: linux-rdma@vger.kernel.org
|
||||
S: Supported
|
||||
@ -11159,7 +11160,7 @@ F: drivers/net/ethernet/mellanox/mlx5/core/
|
||||
F: include/linux/mlx5/
|
||||
|
||||
MELLANOX MLX5 IB driver
|
||||
M: Leon Romanovsky <leonro@mellanox.com>
|
||||
M: Leon Romanovsky <leonro@nvidia.com>
|
||||
L: linux-rdma@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://www.mellanox.com
|
||||
@ -11169,8 +11170,8 @@ F: include/linux/mlx5/
|
||||
F: include/uapi/rdma/mlx5-abi.h
|
||||
|
||||
MELLANOX MLXCPLD I2C AND MUX DRIVER
|
||||
M: Vadim Pasternak <vadimp@mellanox.com>
|
||||
M: Michael Shych <michaelsh@mellanox.com>
|
||||
M: Vadim Pasternak <vadimp@nvidia.com>
|
||||
M: Michael Shych <michaelsh@nvidia.com>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/i2c/busses/i2c-mlxcpld.rst
|
||||
@ -11178,7 +11179,7 @@ F: drivers/i2c/busses/i2c-mlxcpld.c
|
||||
F: drivers/i2c/muxes/i2c-mux-mlxcpld.c
|
||||
|
||||
MELLANOX MLXCPLD LED DRIVER
|
||||
M: Vadim Pasternak <vadimp@mellanox.com>
|
||||
M: Vadim Pasternak <vadimp@nvidia.com>
|
||||
L: linux-leds@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/leds/leds-mlxcpld.rst
|
||||
@ -11186,7 +11187,7 @@ F: drivers/leds/leds-mlxcpld.c
|
||||
F: drivers/leds/leds-mlxreg.c
|
||||
|
||||
MELLANOX PLATFORM DRIVER
|
||||
M: Vadim Pasternak <vadimp@mellanox.com>
|
||||
M: Vadim Pasternak <vadimp@nvidia.com>
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/platform/x86/mlx-platform.c
|
||||
@ -12167,8 +12168,8 @@ F: net/ipv6/syncookies.c
|
||||
F: net/ipv6/tcp*.c
|
||||
|
||||
NETWORKING [TLS]
|
||||
M: Boris Pismenny <borisp@mellanox.com>
|
||||
M: Aviad Yehezkel <aviadye@mellanox.com>
|
||||
M: Boris Pismenny <borisp@nvidia.com>
|
||||
M: Aviad Yehezkel <aviadye@nvidia.com>
|
||||
M: John Fastabend <john.fastabend@gmail.com>
|
||||
M: Daniel Borkmann <daniel@iogearbox.net>
|
||||
M: Jakub Kicinski <kuba@kernel.org>
|
||||
@ -12468,7 +12469,7 @@ S: Supported
|
||||
F: drivers/nfc/nxp-nci
|
||||
|
||||
OBJAGG
|
||||
M: Jiri Pirko <jiri@mellanox.com>
|
||||
M: Jiri Pirko <jiri@nvidia.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
F: include/linux/objagg.h
|
||||
@ -13110,7 +13111,7 @@ F: drivers/video/logo/logo_parisc*
|
||||
F: include/linux/hp_sdc.h
|
||||
|
||||
PARMAN
|
||||
M: Jiri Pirko <jiri@mellanox.com>
|
||||
M: Jiri Pirko <jiri@nvidia.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
F: include/linux/parman.h
|
||||
@ -16034,7 +16035,7 @@ F: drivers/infiniband/sw/siw/
|
||||
F: include/uapi/rdma/siw-abi.h
|
||||
|
||||
SOFT-ROCE DRIVER (rxe)
|
||||
M: Zhu Yanjun <yanjunz@mellanox.com>
|
||||
M: Zhu Yanjun <yanjunz@nvidia.com>
|
||||
L: linux-rdma@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/infiniband/sw/rxe/
|
||||
@ -17116,8 +17117,8 @@ S: Maintained
|
||||
F: Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml
|
||||
F: Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
|
||||
F: Documentation/devicetree/bindings/clock/ti,sci-clk.txt
|
||||
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt
|
||||
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
|
||||
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml
|
||||
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
|
||||
F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt
|
||||
F: Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
|
||||
F: drivers/clk/keystone/sci-clk.c
|
||||
@ -18874,6 +18875,15 @@ S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core
|
||||
F: arch/x86/platform
|
||||
|
||||
X86 PLATFORM UV HPE SUPERDOME FLEX
|
||||
M: Steve Wahl <steve.wahl@hpe.com>
|
||||
R: Dimitri Sivanich <dimitri.sivanich@hpe.com>
|
||||
R: Russ Anderson <russ.anderson@hpe.com>
|
||||
S: Supported
|
||||
F: arch/x86/include/asm/uv/
|
||||
F: arch/x86/kernel/apic/x2apic_uv_x.c
|
||||
F: arch/x86/platform/uv/
|
||||
|
||||
X86 VDSO
|
||||
M: Andy Lutomirski <luto@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
|
||||
7
Makefile
7
Makefile
@ -2,7 +2,7 @@
|
||||
VERSION = 5
|
||||
PATCHLEVEL = 9
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc1
|
||||
EXTRAVERSION = -rc3
|
||||
NAME = Kleptomaniac Octopus
|
||||
|
||||
# *DOCUMENTATION*
|
||||
@ -265,8 +265,7 @@ no-dot-config-targets := $(clean-targets) \
|
||||
$(version_h) headers headers_% archheaders archscripts \
|
||||
%asm-generic kernelversion %src-pkg dt_binding_check \
|
||||
outputmakefile
|
||||
no-sync-config-targets := $(no-dot-config-targets) install %install \
|
||||
kernelrelease
|
||||
no-sync-config-targets := $(no-dot-config-targets) %install kernelrelease
|
||||
single-targets := %.a %.i %.ko %.lds %.ll %.lst %.mod %.o %.s %.symtypes %/
|
||||
|
||||
config-build :=
|
||||
@ -292,7 +291,7 @@ ifneq ($(KBUILD_EXTMOD),)
|
||||
endif
|
||||
|
||||
ifeq ($(KBUILD_EXTMOD),)
|
||||
ifneq ($(filter config %config,$(MAKECMDGOALS)),)
|
||||
ifneq ($(filter %config,$(MAKECMDGOALS)),)
|
||||
config-build := 1
|
||||
ifneq ($(words $(MAKECMDGOALS)),1)
|
||||
mixed-build := 1
|
||||
|
||||
@ -212,7 +212,7 @@ apply_relocate_add(Elf64_Shdr *sechdrs, const char *strtab,
|
||||
STO_ALPHA_STD_GPLOAD)
|
||||
/* Omit the prologue. */
|
||||
value += 8;
|
||||
/* FALLTHRU */
|
||||
fallthrough;
|
||||
case R_ALPHA_BRADDR:
|
||||
value -= (u64)location + 4;
|
||||
if (value & 3)
|
||||
|
||||
@ -453,7 +453,7 @@ syscall_restart(unsigned long r0, unsigned long r19,
|
||||
regs->r0 = EINTR;
|
||||
break;
|
||||
}
|
||||
/* fallthrough */
|
||||
fallthrough;
|
||||
case ERESTARTNOINTR:
|
||||
regs->r0 = r0; /* reset v0 and a3 and replay syscall */
|
||||
regs->r19 = r19;
|
||||
|
||||
@ -883,7 +883,7 @@ do_entUnaUser(void __user * va, unsigned long opcode,
|
||||
|
||||
case 0x26: /* sts */
|
||||
fake_reg = s_reg_to_mem(alpha_read_fp_reg(reg));
|
||||
/* FALLTHRU */
|
||||
fallthrough;
|
||||
|
||||
case 0x2c: /* stl */
|
||||
__asm__ __volatile__(
|
||||
@ -911,7 +911,7 @@ do_entUnaUser(void __user * va, unsigned long opcode,
|
||||
|
||||
case 0x27: /* stt */
|
||||
fake_reg = alpha_read_fp_reg(reg);
|
||||
/* FALLTHRU */
|
||||
fallthrough;
|
||||
|
||||
case 0x2d: /* stq */
|
||||
__asm__ __volatile__(
|
||||
|
||||
@ -339,7 +339,7 @@ void __kprobes disasm_instr(unsigned long addr, struct disasm_state *state,
|
||||
|
||||
case op_LDWX_S: /* LDWX_S c, [b, u6] */
|
||||
state->x = 1;
|
||||
/* intentional fall-through */
|
||||
fallthrough;
|
||||
|
||||
case op_LDW_S: /* LDW_S c, [b, u6] */
|
||||
state->zz = 2;
|
||||
|
||||
@ -321,7 +321,7 @@ static void arc_restart_syscall(struct k_sigaction *ka, struct pt_regs *regs)
|
||||
regs->r0 = -EINTR;
|
||||
break;
|
||||
}
|
||||
/* fallthrough */
|
||||
fallthrough;
|
||||
|
||||
case -ERESTARTNOINTR:
|
||||
/*
|
||||
|
||||
@ -572,7 +572,7 @@ static unsigned long read_pointer(const u8 **pLoc, const void *end,
|
||||
#else
|
||||
BUILD_BUG_ON(sizeof(u32) != sizeof(value));
|
||||
#endif
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case DW_EH_PE_native:
|
||||
if (end < (const void *)(ptr.pul + 1))
|
||||
return 0;
|
||||
@ -827,7 +827,7 @@ static int processCFI(const u8 *start, const u8 *end, unsigned long targetLoc,
|
||||
case DW_CFA_def_cfa:
|
||||
state->cfa.reg = get_uleb128(&ptr.p8, end);
|
||||
unw_debug("cfa_def_cfa: r%lu ", state->cfa.reg);
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case DW_CFA_def_cfa_offset:
|
||||
state->cfa.offs = get_uleb128(&ptr.p8, end);
|
||||
unw_debug("cfa_def_cfa_offset: 0x%lx ",
|
||||
@ -835,7 +835,7 @@ static int processCFI(const u8 *start, const u8 *end, unsigned long targetLoc,
|
||||
break;
|
||||
case DW_CFA_def_cfa_sf:
|
||||
state->cfa.reg = get_uleb128(&ptr.p8, end);
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case DW_CFA_def_cfa_offset_sf:
|
||||
state->cfa.offs = get_sleb128(&ptr.p8, end)
|
||||
* state->dataAlign;
|
||||
|
||||
@ -547,7 +547,7 @@ static int arch_build_bp_info(struct perf_event *bp,
|
||||
if ((hw->ctrl.type != ARM_BREAKPOINT_EXECUTE)
|
||||
&& max_watchpoint_len >= 8)
|
||||
break;
|
||||
/* Else, fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -612,12 +612,12 @@ int hw_breakpoint_arch_parse(struct perf_event *bp,
|
||||
/* Allow halfword watchpoints and breakpoints. */
|
||||
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
|
||||
break;
|
||||
/* Else, fall through */
|
||||
fallthrough;
|
||||
case 3:
|
||||
/* Allow single byte watchpoint. */
|
||||
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
|
||||
break;
|
||||
/* Else, fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
@ -884,7 +884,7 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
|
||||
break;
|
||||
case ARM_ENTRY_ASYNC_WATCHPOINT:
|
||||
WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case ARM_ENTRY_SYNC_WATCHPOINT:
|
||||
watchpoint_handler(addr, fsr, regs);
|
||||
break;
|
||||
@ -933,7 +933,7 @@ static bool core_has_os_save_restore(void)
|
||||
ARM_DBG_READ(c1, c1, 4, oslsr);
|
||||
if (oslsr & ARM_OSLSR_OSLM0)
|
||||
return true;
|
||||
/* Else, fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -596,7 +596,7 @@ static int do_signal(struct pt_regs *regs, int syscall)
|
||||
switch (retval) {
|
||||
case -ERESTART_RESTARTBLOCK:
|
||||
restart -= 2;
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case -ERESTARTNOHAND:
|
||||
case -ERESTARTSYS:
|
||||
case -ERESTARTNOINTR:
|
||||
|
||||
@ -49,7 +49,7 @@ static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t)
|
||||
* FALLTHROUGH: Ensure we don't try to overwrite our newly
|
||||
* initialised state information on the first fault.
|
||||
*/
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
|
||||
case THREAD_NOTIFY_EXIT:
|
||||
crunch_task_release(thread);
|
||||
|
||||
@ -123,19 +123,19 @@ void mmp2_pm_enter_lowpower_mode(int state)
|
||||
case POWER_MODE_SYS_SLEEP:
|
||||
apcr |= MPMU_PCR_PJ_SLPEN; /* set the SLPEN bit */
|
||||
apcr |= MPMU_PCR_PJ_VCTCXOSD; /* set VCTCXOSD */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_CHIP_SLEEP:
|
||||
apcr |= MPMU_PCR_PJ_SLPEN;
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_APPS_SLEEP:
|
||||
apcr |= MPMU_PCR_PJ_APBSD; /* set APBSD */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_APPS_IDLE:
|
||||
apcr |= MPMU_PCR_PJ_AXISD; /* set AXISDD bit */
|
||||
apcr |= MPMU_PCR_PJ_DDRCORSD; /* set DDRCORSD bit */
|
||||
idle_cfg |= APMU_PJ_IDLE_CFG_PJ_PWRDWN; /* PJ power down */
|
||||
apcr |= MPMU_PCR_PJ_SPSD;
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_CORE_EXTIDLE:
|
||||
idle_cfg |= APMU_PJ_IDLE_CFG_PJ_IDLE; /* set the IDLE bit */
|
||||
idle_cfg &= ~APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK;
|
||||
|
||||
@ -145,23 +145,23 @@ void pxa910_pm_enter_lowpower_mode(int state)
|
||||
case POWER_MODE_UDR:
|
||||
/* only shutdown APB in UDR */
|
||||
apcr |= MPMU_APCR_STBYEN | MPMU_APCR_APBSD;
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_SYS_SLEEP:
|
||||
apcr |= MPMU_APCR_SLPEN; /* set the SLPEN bit */
|
||||
apcr |= MPMU_APCR_VCTCXOSD; /* set VCTCXOSD */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_APPS_SLEEP:
|
||||
apcr |= MPMU_APCR_DDRCORSD; /* set DDRCORSD */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_APPS_IDLE:
|
||||
apcr |= MPMU_APCR_AXISD; /* set AXISDD bit */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_CORE_EXTIDLE:
|
||||
idle_cfg |= APMU_MOH_IDLE_CFG_MOH_IDLE;
|
||||
idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN;
|
||||
idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWR_SW(3)
|
||||
| APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(3);
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case POWER_MODE_CORE_INTIDLE:
|
||||
break;
|
||||
}
|
||||
|
||||
@ -396,7 +396,6 @@ void __init omap3xxx_check_revision(void)
|
||||
cpu_rev = "3.1";
|
||||
break;
|
||||
case 7:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
/* Use the latest known revision as default */
|
||||
omap_revision = OMAP3430_REV_ES3_1_2;
|
||||
@ -416,7 +415,6 @@ void __init omap3xxx_check_revision(void)
|
||||
cpu_rev = "1.0";
|
||||
break;
|
||||
case 1:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = AM35XX_REV_ES1_1;
|
||||
cpu_rev = "1.1";
|
||||
@ -435,7 +433,6 @@ void __init omap3xxx_check_revision(void)
|
||||
cpu_rev = "1.1";
|
||||
break;
|
||||
case 2:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = OMAP3630_REV_ES1_2;
|
||||
cpu_rev = "1.2";
|
||||
@ -456,7 +453,6 @@ void __init omap3xxx_check_revision(void)
|
||||
cpu_rev = "2.0";
|
||||
break;
|
||||
case 3:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = TI8168_REV_ES2_1;
|
||||
cpu_rev = "2.1";
|
||||
@ -473,7 +469,6 @@ void __init omap3xxx_check_revision(void)
|
||||
cpu_rev = "2.0";
|
||||
break;
|
||||
case 2:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = AM335X_REV_ES2_1;
|
||||
cpu_rev = "2.1";
|
||||
@ -491,7 +486,6 @@ void __init omap3xxx_check_revision(void)
|
||||
cpu_rev = "1.1";
|
||||
break;
|
||||
case 2:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = AM437X_REV_ES1_2;
|
||||
cpu_rev = "1.2";
|
||||
@ -502,7 +496,6 @@ void __init omap3xxx_check_revision(void)
|
||||
case 0xb968:
|
||||
switch (rev) {
|
||||
case 0:
|
||||
/* FALLTHROUGH */
|
||||
case 1:
|
||||
omap_revision = TI8148_REV_ES1_0;
|
||||
cpu_rev = "1.0";
|
||||
@ -512,7 +505,6 @@ void __init omap3xxx_check_revision(void)
|
||||
cpu_rev = "2.0";
|
||||
break;
|
||||
case 3:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = TI8148_REV_ES2_1;
|
||||
cpu_rev = "2.1";
|
||||
|
||||
@ -240,7 +240,7 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
|
||||
if (pdev->dev.of_node)
|
||||
omap_device_build_from_dt(pdev);
|
||||
omap_auxdata_legacy_init(dev);
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
od = to_omap_device(pdev);
|
||||
if (od)
|
||||
|
||||
@ -298,11 +298,7 @@ static void omap3_pm_idle(void)
|
||||
if (omap_irq_pending())
|
||||
return;
|
||||
|
||||
trace_cpu_idle_rcuidle(1, smp_processor_id());
|
||||
|
||||
omap_sram_idle();
|
||||
|
||||
trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
|
||||
@ -624,7 +624,7 @@ static void __init dns323_init(void)
|
||||
dns323ab_leds[0].active_low = 1;
|
||||
gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
|
||||
gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case DNS323_REV_B1:
|
||||
i2c_register_board_info(0, dns323ab_i2c_devices,
|
||||
ARRAY_SIZE(dns323ab_i2c_devices));
|
||||
|
||||
@ -46,7 +46,7 @@ static int __init parse_tag_acorn(const struct tag *tag)
|
||||
switch (tag->u.acorn.vram_pages) {
|
||||
case 512:
|
||||
vram_size += PAGE_SIZE * 256;
|
||||
/* Fall through - ??? */
|
||||
fallthrough; /* ??? */
|
||||
case 256:
|
||||
vram_size += PAGE_SIZE * 256;
|
||||
default:
|
||||
|
||||
@ -70,7 +70,7 @@ static void __init tegra_cpu_reset_handler_enable(void)
|
||||
switch (err) {
|
||||
case -ENOSYS:
|
||||
tegra_cpu_reset_handler_set(reset_address);
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case 0:
|
||||
is_enabled = true;
|
||||
break;
|
||||
|
||||
@ -694,7 +694,7 @@ thumb2arm(u16 tinstr)
|
||||
return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
|
||||
(tinstr & 255); /* register_list */
|
||||
}
|
||||
/* Else, fall through - for illegal instruction case */
|
||||
fallthrough; /* for illegal instruction case */
|
||||
|
||||
default:
|
||||
return BAD_INSTR;
|
||||
@ -750,7 +750,7 @@ do_alignment_t32_to_handler(u32 *pinstr, struct pt_regs *regs,
|
||||
case 0xe8e0:
|
||||
case 0xe9e0:
|
||||
poffset->un = (tinst2 & 0xff) << 2;
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
|
||||
case 0xe940:
|
||||
case 0xe9c0:
|
||||
|
||||
@ -71,7 +71,7 @@ static void cpu_v7_spectre_init(void)
|
||||
/* Other ARM CPUs require no workaround */
|
||||
if (read_cpuid_implementor() == ARM_CPU_IMP_ARM)
|
||||
break;
|
||||
/* fallthrough */
|
||||
fallthrough;
|
||||
/* Cortex A57/A72 require firmware workaround */
|
||||
case ARM_CPU_PART_CORTEX_A57:
|
||||
case ARM_CPU_PART_CORTEX_A72: {
|
||||
|
||||
@ -309,14 +309,14 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
|
||||
* not supported by current hardware on OMAP1
|
||||
* w |= (0x03 << 7);
|
||||
*/
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case OMAP_DMA_DATA_BURST_16:
|
||||
if (dma_omap2plus()) {
|
||||
burst = 0x3;
|
||||
break;
|
||||
}
|
||||
/* OMAP1 don't support burst 16 */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
@ -393,7 +393,7 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
|
||||
break;
|
||||
}
|
||||
/* OMAP1 don't support burst 16 */
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
printk(KERN_ERR "Invalid DMA burst mode\n");
|
||||
BUG();
|
||||
|
||||
@ -307,7 +307,7 @@ static bool __kprobes decode_regs(probes_opcode_t *pinsn, u32 regs, bool modify)
|
||||
case REG_TYPE_NOPCWB:
|
||||
if (!is_writeback(insn))
|
||||
break; /* No writeback, so any register is OK */
|
||||
/* fall through... */
|
||||
fallthrough;
|
||||
case REG_TYPE_NOPC:
|
||||
case REG_TYPE_NOPCX:
|
||||
/* Reject PC (R15) */
|
||||
|
||||
@ -280,7 +280,7 @@ void __kprobes kprobe_handler(struct pt_regs *regs)
|
||||
/* A nested probe was hit in FIQ, it is a BUG */
|
||||
pr_warn("Unrecoverable kprobe detected.\n");
|
||||
dump_kprobe(p);
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
/* impossible cases */
|
||||
BUG();
|
||||
|
||||
@ -82,8 +82,8 @@ endif
|
||||
# compiler to generate them and consequently to break the single image contract
|
||||
# we pass it only to the assembler. This option is utilized only in case of non
|
||||
# integrated assemblers.
|
||||
ifneq ($(CONFIG_AS_HAS_ARMV8_4), y)
|
||||
branch-prot-flags-$(CONFIG_AS_HAS_PAC) += -Wa,-march=armv8.3-a
|
||||
ifeq ($(CONFIG_AS_HAS_PAC), y)
|
||||
asm-arch := armv8.3-a
|
||||
endif
|
||||
endif
|
||||
|
||||
@ -91,7 +91,12 @@ KBUILD_CFLAGS += $(branch-prot-flags-y)
|
||||
|
||||
ifeq ($(CONFIG_AS_HAS_ARMV8_4), y)
|
||||
# make sure to pass the newest target architecture to -march.
|
||||
KBUILD_CFLAGS += -Wa,-march=armv8.4-a
|
||||
asm-arch := armv8.4-a
|
||||
endif
|
||||
|
||||
ifdef asm-arch
|
||||
KBUILD_CFLAGS += -Wa,-march=$(asm-arch) \
|
||||
-DARM64_ASM_ARCH='"$(asm-arch)"'
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SHADOW_CALL_STACK), y)
|
||||
@ -165,6 +170,8 @@ zinstall install:
|
||||
PHONY += vdso_install
|
||||
vdso_install:
|
||||
$(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso $@
|
||||
$(if $(CONFIG_COMPAT_VDSO), \
|
||||
$(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso32 $@)
|
||||
|
||||
# We use MRPROPER_FILES and CLEAN_FILES now
|
||||
archclean:
|
||||
|
||||
@ -417,10 +417,10 @@ intr_main_gpio: interrupt-controller0 {
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <56>;
|
||||
ti,sci-rm-range-girq = <0x1>;
|
||||
ti,sci-dev-id = <100>;
|
||||
ti,interrupt-ranges = <0 392 32>;
|
||||
};
|
||||
|
||||
main_navss {
|
||||
@ -438,10 +438,11 @@ intr_main_navss: interrupt-controller1 {
|
||||
ti,intr-trigger-type = <4>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <56>;
|
||||
ti,sci-rm-range-girq = <0x0>, <0x2>;
|
||||
ti,sci-dev-id = <182>;
|
||||
ti,interrupt-ranges = <0 64 64>,
|
||||
<64 448 64>;
|
||||
};
|
||||
|
||||
inta_main_udmass: interrupt-controller@33d00000 {
|
||||
@ -452,8 +453,7 @@ inta_main_udmass: interrupt-controller@33d00000 {
|
||||
msi-controller;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <179>;
|
||||
ti,sci-rm-range-vint = <0x0>;
|
||||
ti,sci-rm-range-global-event = <0x1>;
|
||||
ti,interrupt-ranges = <0 0 256>;
|
||||
};
|
||||
|
||||
secure_proxy_main: mailbox@32c00000 {
|
||||
@ -589,7 +589,7 @@ ringacc: ringacc@3c000000 {
|
||||
<0x0 0x33000000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <818>;
|
||||
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,dma-ring-reset-quirk;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <187>;
|
||||
@ -609,11 +609,11 @@ main_udmap: dma-controller@31150000 {
|
||||
ti,sci-dev-id = <188>;
|
||||
ti,ringacc = <&ringacc>;
|
||||
|
||||
ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
|
||||
<0x2>; /* TX_CHAN */
|
||||
ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
|
||||
<0x5>; /* RX_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
|
||||
ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
|
||||
<0xd>; /* TX_CHAN */
|
||||
ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
|
||||
<0xa>; /* RX_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
|
||||
};
|
||||
|
||||
cpts@310d0000 {
|
||||
@ -622,7 +622,7 @@ cpts@310d0000 {
|
||||
reg-names = "cpts";
|
||||
clocks = <&main_cpts_mux>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&intr_main_navss 163 0>;
|
||||
interrupts-extended = <&intr_main_navss 391>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-periodic-outputs = <6>;
|
||||
ti,cpts-ext-ts-inputs = <8>;
|
||||
@ -645,8 +645,7 @@ main_gpio0: main_gpio0@600000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&intr_main_gpio>;
|
||||
interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,
|
||||
<57 261>;
|
||||
interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <96>;
|
||||
@ -661,8 +660,7 @@ main_gpio1: main_gpio1@601000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&intr_main_gpio>;
|
||||
interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,
|
||||
<58 261>;
|
||||
interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <90>;
|
||||
|
||||
@ -134,7 +134,7 @@ mcu_ringacc: ringacc@2b800000 {
|
||||
<0x0 0x2a500000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <286>;
|
||||
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,dma-ring-reset-quirk;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <195>;
|
||||
@ -154,11 +154,11 @@ mcu_udmap: dma-controller@285c0000 {
|
||||
ti,sci-dev-id = <194>;
|
||||
ti,ringacc = <&mcu_ringacc>;
|
||||
|
||||
ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
|
||||
<0x2>; /* TX_CHAN */
|
||||
ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
|
||||
<0x4>; /* RX_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
|
||||
ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
|
||||
<0xd>; /* TX_CHAN */
|
||||
ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
|
||||
<0xa>; /* RX_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -74,10 +74,10 @@ intr_wkup_gpio: interrupt-controller2 {
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <56>;
|
||||
ti,sci-rm-range-girq = <0x4>;
|
||||
ti,sci-dev-id = <156>;
|
||||
ti,interrupt-ranges = <0 712 16>;
|
||||
};
|
||||
|
||||
wkup_gpio0: wkup_gpio0@42110000 {
|
||||
@ -86,7 +86,7 @@ wkup_gpio0: wkup_gpio0@42110000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&intr_wkup_gpio>;
|
||||
interrupts = <59 128>, <59 129>, <59 130>, <59 131>;
|
||||
interrupts = <60>, <61>, <62>, <63>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <56>;
|
||||
|
||||
@ -384,7 +384,7 @@ &pcie1_ep {
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
interrupts = <164 0>;
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
@ -393,7 +393,7 @@ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
interrupts = <165 0>;
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
|
||||
@ -287,7 +287,7 @@ &wkup_gpio1 {
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
interrupts = <214 0>;
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
@ -301,7 +301,7 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
interrupts = <215 0>;
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
@ -315,7 +315,7 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
interrupts = <216 0>;
|
||||
interrupts = <428>;
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
@ -329,7 +329,7 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
interrupts = <217 0>;
|
||||
interrupts = <424>;
|
||||
|
||||
mbox_c66_0: mbox-c66-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
@ -343,7 +343,7 @@ mbox_c66_1: mbox-c66-1 {
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
interrupts = <218 0>;
|
||||
interrupts = <420>;
|
||||
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
|
||||
@ -80,10 +80,10 @@ main_gpio_intr: interrupt-controller0 {
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <14>;
|
||||
ti,sci-rm-range-girq = <0x1>;
|
||||
ti,sci-dev-id = <131>;
|
||||
ti,interrupt-ranges = <8 392 56>;
|
||||
};
|
||||
|
||||
main_navss {
|
||||
@ -101,10 +101,12 @@ main_navss_intr: interrupt-controller1 {
|
||||
ti,intr-trigger-type = <4>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <14>;
|
||||
ti,sci-rm-range-girq = <0>, <2>;
|
||||
ti,sci-dev-id = <213>;
|
||||
ti,interrupt-ranges = <0 64 64>,
|
||||
<64 448 64>,
|
||||
<128 672 64>;
|
||||
};
|
||||
|
||||
main_udmass_inta: interrupt-controller@33d00000 {
|
||||
@ -115,8 +117,7 @@ main_udmass_inta: interrupt-controller@33d00000 {
|
||||
msi-controller;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <209>;
|
||||
ti,sci-rm-range-vint = <0xa>;
|
||||
ti,sci-rm-range-global-event = <0xd>;
|
||||
ti,interrupt-ranges = <0 0 256>;
|
||||
};
|
||||
|
||||
secure_proxy_main: mailbox@32c00000 {
|
||||
@ -296,7 +297,7 @@ cpts@310d0000 {
|
||||
reg-names = "cpts";
|
||||
clocks = <&k3_clks 201 1>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&main_navss_intr 201 0>;
|
||||
interrupts-extended = <&main_navss_intr 391>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-periodic-outputs = <6>;
|
||||
ti,cpts-ext-ts-inputs = <8>;
|
||||
@ -688,8 +689,8 @@ main_gpio0: gpio@600000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <105 0>, <105 1>, <105 2>, <105 3>,
|
||||
<105 4>, <105 5>, <105 6>, <105 7>;
|
||||
interrupts = <256>, <257>, <258>, <259>,
|
||||
<260>, <261>, <262>, <263>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <128>;
|
||||
@ -705,7 +706,7 @@ main_gpio1: gpio@601000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <106 0>, <106 1>, <106 2>;
|
||||
interrupts = <288>, <289>, <290>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <36>;
|
||||
@ -721,8 +722,8 @@ main_gpio2: gpio@610000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <107 0>, <107 1>, <107 2>, <107 3>,
|
||||
<107 4>, <107 5>, <107 6>, <107 7>;
|
||||
interrupts = <264>, <265>, <266>, <267>,
|
||||
<268>, <269>, <270>, <271>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <128>;
|
||||
@ -738,7 +739,7 @@ main_gpio3: gpio@611000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <108 0>, <108 1>, <108 2>;
|
||||
interrupts = <292>, <293>, <294>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <36>;
|
||||
@ -754,8 +755,8 @@ main_gpio4: gpio@620000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <109 0>, <109 1>, <109 2>, <109 3>,
|
||||
<109 4>, <109 5>, <109 6>, <109 7>;
|
||||
interrupts = <272>, <273>, <274>, <275>,
|
||||
<276>, <277>, <278>, <279>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <128>;
|
||||
@ -771,7 +772,7 @@ main_gpio5: gpio@621000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <110 0>, <110 1>, <110 2>;
|
||||
interrupts = <296>, <297>, <298>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <36>;
|
||||
@ -787,8 +788,8 @@ main_gpio6: gpio@630000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <111 0>, <111 1>, <111 2>, <111 3>,
|
||||
<111 4>, <111 5>, <111 6>, <111 7>;
|
||||
interrupts = <280>, <281>, <282>, <283>,
|
||||
<284>, <285>, <286>, <287>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <128>;
|
||||
@ -804,7 +805,7 @@ main_gpio7: gpio@631000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <112 0>, <112 1>, <112 2>;
|
||||
interrupts = <300>, <301>, <302>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <36>;
|
||||
|
||||
@ -101,10 +101,10 @@ wkup_gpio_intr: interrupt-controller2 {
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <14>;
|
||||
ti,sci-rm-range-girq = <0x5>;
|
||||
ti,sci-dev-id = <137>;
|
||||
ti,interrupt-ranges = <16 960 16>;
|
||||
};
|
||||
|
||||
wkup_gpio0: gpio@42110000 {
|
||||
@ -113,8 +113,7 @@ wkup_gpio0: gpio@42110000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&wkup_gpio_intr>;
|
||||
interrupts = <113 0>, <113 1>, <113 2>,
|
||||
<113 3>, <113 4>, <113 5>;
|
||||
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <84>;
|
||||
@ -130,8 +129,7 @@ wkup_gpio1: gpio@42100000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&wkup_gpio_intr>;
|
||||
interrupts = <114 0>, <114 1>, <114 2>,
|
||||
<114 3>, <114 4>, <114 5>;
|
||||
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <84>;
|
||||
|
||||
@ -2,6 +2,12 @@
|
||||
#ifndef __ASM_COMPILER_H
|
||||
#define __ASM_COMPILER_H
|
||||
|
||||
#ifdef ARM64_ASM_ARCH
|
||||
#define ARM64_ASM_PREAMBLE ".arch " ARM64_ASM_ARCH "\n"
|
||||
#else
|
||||
#define ARM64_ASM_PREAMBLE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The EL0/EL1 pointer bits used by a pointer authentication code.
|
||||
* This is dependent on TBI0/TBI1 being enabled, or bits 63:56 would also apply.
|
||||
|
||||
@ -95,6 +95,11 @@ static inline int arch_irqs_disabled_flags(unsigned long flags)
|
||||
return res;
|
||||
}
|
||||
|
||||
static inline int arch_irqs_disabled(void)
|
||||
{
|
||||
return arch_irqs_disabled_flags(arch_local_save_flags());
|
||||
}
|
||||
|
||||
static inline unsigned long arch_local_irq_save(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
@ -71,11 +71,12 @@
|
||||
* IMO: Override CPSR.I and enable signaling with VI
|
||||
* FMO: Override CPSR.F and enable signaling with VF
|
||||
* SWIO: Turn set/way invalidates into set/way clean+invalidate
|
||||
* PTW: Take a stage2 fault if a stage1 walk steps in device memory
|
||||
*/
|
||||
#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
|
||||
HCR_BSU_IS | HCR_FB | HCR_TAC | \
|
||||
HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
|
||||
HCR_FMO | HCR_IMO)
|
||||
HCR_FMO | HCR_IMO | HCR_PTW )
|
||||
#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
|
||||
#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK)
|
||||
#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
|
||||
|
||||
@ -169,6 +169,34 @@ extern char __smccc_workaround_1_smc[__SMCCC_WORKAROUND_1_SMC_SZ];
|
||||
*__hyp_this_cpu_ptr(sym); \
|
||||
})
|
||||
|
||||
#define __KVM_EXTABLE(from, to) \
|
||||
" .pushsection __kvm_ex_table, \"a\"\n" \
|
||||
" .align 3\n" \
|
||||
" .long (" #from " - .), (" #to " - .)\n" \
|
||||
" .popsection\n"
|
||||
|
||||
|
||||
#define __kvm_at(at_op, addr) \
|
||||
( { \
|
||||
int __kvm_at_err = 0; \
|
||||
u64 spsr, elr; \
|
||||
asm volatile( \
|
||||
" mrs %1, spsr_el2\n" \
|
||||
" mrs %2, elr_el2\n" \
|
||||
"1: at "at_op", %3\n" \
|
||||
" isb\n" \
|
||||
" b 9f\n" \
|
||||
"2: msr spsr_el2, %1\n" \
|
||||
" msr elr_el2, %2\n" \
|
||||
" mov %w0, %4\n" \
|
||||
"9:\n" \
|
||||
__KVM_EXTABLE(1b, 2b) \
|
||||
: "+r" (__kvm_at_err), "=&r" (spsr), "=&r" (elr) \
|
||||
: "r" (addr), "i" (-EFAULT)); \
|
||||
__kvm_at_err; \
|
||||
} )
|
||||
|
||||
|
||||
#else /* __ASSEMBLY__ */
|
||||
|
||||
.macro hyp_adr_this_cpu reg, sym, tmp
|
||||
@ -193,6 +221,21 @@ extern char __smccc_workaround_1_smc[__SMCCC_WORKAROUND_1_SMC_SZ];
|
||||
ldr \vcpu, [\ctxt, #HOST_CONTEXT_VCPU]
|
||||
.endm
|
||||
|
||||
/*
|
||||
* KVM extable for unexpected exceptions.
|
||||
* In the same format _asm_extable, but output to a different section so that
|
||||
* it can be mapped to EL2. The KVM version is not sorted. The caller must
|
||||
* ensure:
|
||||
* x18 has the hypervisor value to allow any Shadow-Call-Stack instrumented
|
||||
* code to write to it, and that SPSR_EL2 and ELR_EL2 are restored by the fixup.
|
||||
*/
|
||||
.macro _kvm_extable, from, to
|
||||
.pushsection __kvm_ex_table, "a"
|
||||
.align 3
|
||||
.long (\from - .), (\to - .)
|
||||
.popsection
|
||||
.endm
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ARM_KVM_ASM_H__ */
|
||||
|
||||
@ -473,7 +473,7 @@ int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
|
||||
|
||||
#define KVM_ARCH_WANT_MMU_NOTIFIER
|
||||
int kvm_unmap_hva_range(struct kvm *kvm,
|
||||
unsigned long start, unsigned long end);
|
||||
unsigned long start, unsigned long end, unsigned flags);
|
||||
int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
|
||||
int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
|
||||
int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
|
||||
|
||||
@ -28,14 +28,16 @@
|
||||
* not. The macros handles invoking the asm with or without the
|
||||
* register argument as appropriate.
|
||||
*/
|
||||
#define __TLBI_0(op, arg) asm ("tlbi " #op "\n" \
|
||||
#define __TLBI_0(op, arg) asm (ARM64_ASM_PREAMBLE \
|
||||
"tlbi " #op "\n" \
|
||||
ALTERNATIVE("nop\n nop", \
|
||||
"dsb ish\n tlbi " #op, \
|
||||
ARM64_WORKAROUND_REPEAT_TLBI, \
|
||||
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \
|
||||
: : )
|
||||
|
||||
#define __TLBI_1(op, arg) asm ("tlbi " #op ", %0\n" \
|
||||
#define __TLBI_1(op, arg) asm (ARM64_ASM_PREAMBLE \
|
||||
"tlbi " #op ", %0\n" \
|
||||
ALTERNATIVE("nop\n nop", \
|
||||
"dsb ish\n tlbi " #op ", %0", \
|
||||
ARM64_WORKAROUND_REPEAT_TLBI, \
|
||||
|
||||
@ -322,7 +322,7 @@ void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size)
|
||||
*/
|
||||
if (memblock_is_map_memory(phys))
|
||||
return (void __iomem *)__phys_to_virt(phys);
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
|
||||
default:
|
||||
if (region->attribute & EFI_MEMORY_WB)
|
||||
|
||||
@ -910,6 +910,8 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
|
||||
.desc = "ARM erratum 1418040",
|
||||
.capability = ARM64_WORKAROUND_1418040,
|
||||
ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
|
||||
.type = (ARM64_CPUCAP_SCOPE_LOCAL_CPU |
|
||||
ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU),
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
|
||||
|
||||
@ -686,7 +686,7 @@ static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
|
||||
case FTR_HIGHER_OR_ZERO_SAFE:
|
||||
if (!cur || !new)
|
||||
break;
|
||||
/* Fallthrough */
|
||||
fallthrough;
|
||||
case FTR_HIGHER_SAFE:
|
||||
ret = new > cur ? new : cur;
|
||||
break;
|
||||
|
||||
@ -327,7 +327,6 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
|
||||
set_bit(ICACHEF_VPIPT, &__icache_flags);
|
||||
break;
|
||||
default:
|
||||
/* Fallthrough */
|
||||
case ICACHE_POLICY_VIPT:
|
||||
/* Assume aliasing */
|
||||
set_bit(ICACHEF_ALIASING, &__icache_flags);
|
||||
|
||||
@ -170,19 +170,6 @@ alternative_cb_end
|
||||
stp x28, x29, [sp, #16 * 14]
|
||||
|
||||
.if \el == 0
|
||||
.if \regsize == 32
|
||||
/*
|
||||
* If we're returning from a 32-bit task on a system affected by
|
||||
* 1418040 then re-enable userspace access to the virtual counter.
|
||||
*/
|
||||
#ifdef CONFIG_ARM64_ERRATUM_1418040
|
||||
alternative_if ARM64_WORKAROUND_1418040
|
||||
mrs x0, cntkctl_el1
|
||||
orr x0, x0, #2 // ARCH_TIMER_USR_VCT_ACCESS_EN
|
||||
msr cntkctl_el1, x0
|
||||
alternative_else_nop_endif
|
||||
#endif
|
||||
.endif
|
||||
clear_gp_regs
|
||||
mrs x21, sp_el0
|
||||
ldr_this_cpu tsk, __entry_task, x20
|
||||
@ -294,14 +281,6 @@ alternative_else_nop_endif
|
||||
tst x22, #PSR_MODE32_BIT // native task?
|
||||
b.eq 3f
|
||||
|
||||
#ifdef CONFIG_ARM64_ERRATUM_1418040
|
||||
alternative_if ARM64_WORKAROUND_1418040
|
||||
mrs x0, cntkctl_el1
|
||||
bic x0, x0, #2 // ARCH_TIMER_USR_VCT_ACCESS_EN
|
||||
msr cntkctl_el1, x0
|
||||
alternative_else_nop_endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM64_ERRATUM_845719
|
||||
alternative_if ARM64_WORKAROUND_845719
|
||||
#ifdef CONFIG_PID_IN_CONTEXTIDR
|
||||
|
||||
@ -257,7 +257,7 @@ static int hw_breakpoint_control(struct perf_event *bp,
|
||||
* level.
|
||||
*/
|
||||
enable_debug_monitors(dbg_el);
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case HW_BREAKPOINT_RESTORE:
|
||||
/* Setup the address register. */
|
||||
write_wb_reg(val_reg, i, info->address);
|
||||
@ -541,13 +541,13 @@ int hw_breakpoint_arch_parse(struct perf_event *bp,
|
||||
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
|
||||
break;
|
||||
|
||||
/* Fallthrough */
|
||||
fallthrough;
|
||||
case 3:
|
||||
/* Allow single byte watchpoint. */
|
||||
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
|
||||
break;
|
||||
|
||||
/* Fallthrough */
|
||||
fallthrough;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@ -103,6 +103,10 @@ KVM_NVHE_ALIAS(vgic_v3_cpuif_trap);
|
||||
KVM_NVHE_ALIAS(gic_pmr_sync);
|
||||
#endif
|
||||
|
||||
/* EL2 exception handling */
|
||||
KVM_NVHE_ALIAS(__start___kvm_ex_table);
|
||||
KVM_NVHE_ALIAS(__stop___kvm_ex_table);
|
||||
|
||||
#endif /* CONFIG_KVM */
|
||||
|
||||
#endif /* __ARM64_KERNEL_IMAGE_VARS_H */
|
||||
|
||||
@ -315,21 +315,21 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
|
||||
/* MOVW instruction relocations. */
|
||||
case R_AARCH64_MOVW_UABS_G0_NC:
|
||||
overflow_check = false;
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case R_AARCH64_MOVW_UABS_G0:
|
||||
ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
|
||||
AARCH64_INSN_IMM_MOVKZ);
|
||||
break;
|
||||
case R_AARCH64_MOVW_UABS_G1_NC:
|
||||
overflow_check = false;
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case R_AARCH64_MOVW_UABS_G1:
|
||||
ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
|
||||
AARCH64_INSN_IMM_MOVKZ);
|
||||
break;
|
||||
case R_AARCH64_MOVW_UABS_G2_NC:
|
||||
overflow_check = false;
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case R_AARCH64_MOVW_UABS_G2:
|
||||
ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
|
||||
AARCH64_INSN_IMM_MOVKZ);
|
||||
@ -397,7 +397,7 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
|
||||
break;
|
||||
case R_AARCH64_ADR_PREL_PG_HI21_NC:
|
||||
overflow_check = false;
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case R_AARCH64_ADR_PREL_PG_HI21:
|
||||
ovf = reloc_insn_adrp(me, sechdrs, loc, val);
|
||||
if (ovf && ovf != -ERANGE)
|
||||
|
||||
@ -123,10 +123,8 @@ void arch_cpu_idle(void)
|
||||
* This should do all the clock switching and wait for interrupt
|
||||
* tricks
|
||||
*/
|
||||
trace_cpu_idle_rcuidle(1, smp_processor_id());
|
||||
cpu_do_idle();
|
||||
local_irq_enable();
|
||||
trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
@ -515,6 +513,39 @@ static void entry_task_switch(struct task_struct *next)
|
||||
__this_cpu_write(__entry_task, next);
|
||||
}
|
||||
|
||||
/*
|
||||
* ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT.
|
||||
* Assuming the virtual counter is enabled at the beginning of times:
|
||||
*
|
||||
* - disable access when switching from a 64bit task to a 32bit task
|
||||
* - enable access when switching from a 32bit task to a 64bit task
|
||||
*/
|
||||
static void erratum_1418040_thread_switch(struct task_struct *prev,
|
||||
struct task_struct *next)
|
||||
{
|
||||
bool prev32, next32;
|
||||
u64 val;
|
||||
|
||||
if (!(IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040) &&
|
||||
cpus_have_const_cap(ARM64_WORKAROUND_1418040)))
|
||||
return;
|
||||
|
||||
prev32 = is_compat_thread(task_thread_info(prev));
|
||||
next32 = is_compat_thread(task_thread_info(next));
|
||||
|
||||
if (prev32 == next32)
|
||||
return;
|
||||
|
||||
val = read_sysreg(cntkctl_el1);
|
||||
|
||||
if (!next32)
|
||||
val |= ARCH_TIMER_USR_VCT_ACCESS_EN;
|
||||
else
|
||||
val &= ~ARCH_TIMER_USR_VCT_ACCESS_EN;
|
||||
|
||||
write_sysreg(val, cntkctl_el1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Thread switching.
|
||||
*/
|
||||
@ -530,6 +561,7 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev,
|
||||
entry_task_switch(next);
|
||||
uao_thread_switch(next);
|
||||
ssbs_thread_switch(next);
|
||||
erratum_1418040_thread_switch(prev, next);
|
||||
|
||||
/*
|
||||
* Complete any pending TLB or cache maintenance on this CPU in case
|
||||
|
||||
@ -151,7 +151,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
|
||||
break;
|
||||
}
|
||||
pr_crit("CPU%u: may not have shut down cleanly\n", cpu);
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case CPU_STUCK_IN_KERNEL:
|
||||
pr_crit("CPU%u: is stuck in kernel\n", cpu);
|
||||
if (status & CPU_STUCK_REASON_52_BIT_VA)
|
||||
|
||||
@ -208,7 +208,7 @@ quiet_cmd_vdsosym = VDSOSYM $@
|
||||
cmd_vdsosym = $(NM) $< | $(gen-vdsosym) | LC_ALL=C sort > $@
|
||||
|
||||
# Install commands for the unstripped file
|
||||
quiet_cmd_vdso_install = INSTALL $@
|
||||
quiet_cmd_vdso_install = INSTALL32 $@
|
||||
cmd_vdso_install = cp $(obj)/$@.dbg $(MODLIB)/vdso/vdso32.so
|
||||
|
||||
vdso.so: $(obj)/vdso.so.dbg
|
||||
|
||||
@ -20,6 +20,13 @@ ENTRY(_text)
|
||||
|
||||
jiffies = jiffies_64;
|
||||
|
||||
|
||||
#define HYPERVISOR_EXTABLE \
|
||||
. = ALIGN(SZ_8); \
|
||||
__start___kvm_ex_table = .; \
|
||||
*(__kvm_ex_table) \
|
||||
__stop___kvm_ex_table = .;
|
||||
|
||||
#define HYPERVISOR_TEXT \
|
||||
/* \
|
||||
* Align to 4 KB so that \
|
||||
@ -35,6 +42,7 @@ jiffies = jiffies_64;
|
||||
__hyp_idmap_text_end = .; \
|
||||
__hyp_text_start = .; \
|
||||
*(.hyp.text) \
|
||||
HYPERVISOR_EXTABLE \
|
||||
__hyp_text_end = .;
|
||||
|
||||
#define IDMAP_TEXT \
|
||||
|
||||
@ -1640,6 +1640,10 @@ int kvm_arch_init(void *opaque)
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (cpus_have_final_cap(ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE))
|
||||
kvm_info("Guests without required CPU erratum workarounds can deadlock system!\n" \
|
||||
"Only trusted guests should be used on this system.\n");
|
||||
|
||||
for_each_online_cpu(cpu) {
|
||||
smp_call_function_single(cpu, check_kvm_target_cpu, &ret, 1);
|
||||
if (ret < 0) {
|
||||
|
||||
@ -128,7 +128,7 @@ static int kvm_handle_guest_debug(struct kvm_vcpu *vcpu)
|
||||
switch (ESR_ELx_EC(esr)) {
|
||||
case ESR_ELx_EC_WATCHPT_LOW:
|
||||
run->debug.arch.far = vcpu->arch.fault.far_el2;
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case ESR_ELx_EC_SOFTSTP_LOW:
|
||||
case ESR_ELx_EC_BREAKPT_LOW:
|
||||
case ESR_ELx_EC_BKPT32:
|
||||
|
||||
@ -196,20 +196,23 @@ alternative_endif
|
||||
// This is our single instruction exception window. A pending
|
||||
// SError is guaranteed to occur at the earliest when we unmask
|
||||
// it, and at the latest just after the ISB.
|
||||
.global abort_guest_exit_start
|
||||
abort_guest_exit_start:
|
||||
|
||||
isb
|
||||
|
||||
.global abort_guest_exit_end
|
||||
abort_guest_exit_end:
|
||||
|
||||
msr daifset, #4 // Mask aborts
|
||||
ret
|
||||
|
||||
// If the exception took place, restore the EL1 exception
|
||||
// context so that we can report some information.
|
||||
// Merge the exception code with the SError pending bit.
|
||||
tbz x0, #ARM_EXIT_WITH_SERROR_BIT, 1f
|
||||
_kvm_extable abort_guest_exit_start, 9997f
|
||||
_kvm_extable abort_guest_exit_end, 9997f
|
||||
9997:
|
||||
msr daifset, #4 // Mask aborts
|
||||
mov x0, #(1 << ARM_EXIT_WITH_SERROR_BIT)
|
||||
|
||||
// restore the EL1 exception context so that we can report some
|
||||
// information. Merge the exception code with the SError pending bit.
|
||||
msr elr_el2, x2
|
||||
msr esr_el2, x3
|
||||
msr spsr_el2, x4
|
||||
|
||||
@ -15,6 +15,30 @@
|
||||
#include <asm/kvm_mmu.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
.macro save_caller_saved_regs_vect
|
||||
/* x0 and x1 were saved in the vector entry */
|
||||
stp x2, x3, [sp, #-16]!
|
||||
stp x4, x5, [sp, #-16]!
|
||||
stp x6, x7, [sp, #-16]!
|
||||
stp x8, x9, [sp, #-16]!
|
||||
stp x10, x11, [sp, #-16]!
|
||||
stp x12, x13, [sp, #-16]!
|
||||
stp x14, x15, [sp, #-16]!
|
||||
stp x16, x17, [sp, #-16]!
|
||||
.endm
|
||||
|
||||
.macro restore_caller_saved_regs_vect
|
||||
ldp x16, x17, [sp], #16
|
||||
ldp x14, x15, [sp], #16
|
||||
ldp x12, x13, [sp], #16
|
||||
ldp x10, x11, [sp], #16
|
||||
ldp x8, x9, [sp], #16
|
||||
ldp x6, x7, [sp], #16
|
||||
ldp x4, x5, [sp], #16
|
||||
ldp x2, x3, [sp], #16
|
||||
ldp x0, x1, [sp], #16
|
||||
.endm
|
||||
|
||||
.text
|
||||
|
||||
.macro do_el2_call
|
||||
@ -143,13 +167,19 @@ el1_error:
|
||||
b __guest_exit
|
||||
|
||||
el2_sync:
|
||||
/* Check for illegal exception return, otherwise panic */
|
||||
/* Check for illegal exception return */
|
||||
mrs x0, spsr_el2
|
||||
tbnz x0, #20, 1f
|
||||
|
||||
/* if this was something else, then panic! */
|
||||
tst x0, #PSR_IL_BIT
|
||||
b.eq __hyp_panic
|
||||
save_caller_saved_regs_vect
|
||||
stp x29, x30, [sp, #-16]!
|
||||
bl kvm_unexpected_el2_exception
|
||||
ldp x29, x30, [sp], #16
|
||||
restore_caller_saved_regs_vect
|
||||
|
||||
eret
|
||||
|
||||
1:
|
||||
/* Let's attempt a recovery from the illegal exception return */
|
||||
get_vcpu_ptr x1, x0
|
||||
mov x0, #ARM_EXCEPTION_IL
|
||||
@ -157,27 +187,14 @@ el2_sync:
|
||||
|
||||
|
||||
el2_error:
|
||||
ldp x0, x1, [sp], #16
|
||||
save_caller_saved_regs_vect
|
||||
stp x29, x30, [sp, #-16]!
|
||||
|
||||
bl kvm_unexpected_el2_exception
|
||||
|
||||
ldp x29, x30, [sp], #16
|
||||
restore_caller_saved_regs_vect
|
||||
|
||||
/*
|
||||
* Only two possibilities:
|
||||
* 1) Either we come from the exit path, having just unmasked
|
||||
* PSTATE.A: change the return code to an EL2 fault, and
|
||||
* carry on, as we're already in a sane state to handle it.
|
||||
* 2) Or we come from anywhere else, and that's a bug: we panic.
|
||||
*
|
||||
* For (1), x0 contains the original return code and x1 doesn't
|
||||
* contain anything meaningful at that stage. We can reuse them
|
||||
* as temp registers.
|
||||
* For (2), who cares?
|
||||
*/
|
||||
mrs x0, elr_el2
|
||||
adr x1, abort_guest_exit_start
|
||||
cmp x0, x1
|
||||
adr x1, abort_guest_exit_end
|
||||
ccmp x0, x1, #4, ne
|
||||
b.ne __hyp_panic
|
||||
mov x0, #(1 << ARM_EXIT_WITH_SERROR_BIT)
|
||||
eret
|
||||
sb
|
||||
|
||||
|
||||
@ -21,70 +21,70 @@
|
||||
#define save_debug(ptr,reg,nr) \
|
||||
switch (nr) { \
|
||||
case 15: ptr[15] = read_debug(reg, 15); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 14: ptr[14] = read_debug(reg, 14); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 13: ptr[13] = read_debug(reg, 13); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 12: ptr[12] = read_debug(reg, 12); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 11: ptr[11] = read_debug(reg, 11); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 10: ptr[10] = read_debug(reg, 10); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 9: ptr[9] = read_debug(reg, 9); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 8: ptr[8] = read_debug(reg, 8); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 7: ptr[7] = read_debug(reg, 7); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 6: ptr[6] = read_debug(reg, 6); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 5: ptr[5] = read_debug(reg, 5); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 4: ptr[4] = read_debug(reg, 4); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 3: ptr[3] = read_debug(reg, 3); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 2: ptr[2] = read_debug(reg, 2); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 1: ptr[1] = read_debug(reg, 1); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
default: ptr[0] = read_debug(reg, 0); \
|
||||
}
|
||||
|
||||
#define restore_debug(ptr,reg,nr) \
|
||||
switch (nr) { \
|
||||
case 15: write_debug(ptr[15], reg, 15); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 14: write_debug(ptr[14], reg, 14); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 13: write_debug(ptr[13], reg, 13); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 12: write_debug(ptr[12], reg, 12); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 11: write_debug(ptr[11], reg, 11); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 10: write_debug(ptr[10], reg, 10); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 9: write_debug(ptr[9], reg, 9); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 8: write_debug(ptr[8], reg, 8); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 7: write_debug(ptr[7], reg, 7); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 6: write_debug(ptr[6], reg, 6); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 5: write_debug(ptr[5], reg, 5); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 4: write_debug(ptr[4], reg, 4); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 3: write_debug(ptr[3], reg, 3); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 2: write_debug(ptr[2], reg, 2); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
case 1: write_debug(ptr[1], reg, 1); \
|
||||
/* Fall through */ \
|
||||
fallthrough; \
|
||||
default: write_debug(ptr[0], reg, 0); \
|
||||
}
|
||||
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
|
||||
#include <asm/barrier.h>
|
||||
#include <asm/cpufeature.h>
|
||||
#include <asm/extable.h>
|
||||
#include <asm/kprobes.h>
|
||||
#include <asm/kvm_asm.h>
|
||||
#include <asm/kvm_emulate.h>
|
||||
@ -29,6 +30,9 @@
|
||||
|
||||
extern const char __hyp_panic_string[];
|
||||
|
||||
extern struct exception_table_entry __start___kvm_ex_table;
|
||||
extern struct exception_table_entry __stop___kvm_ex_table;
|
||||
|
||||
/* Check whether the FP regs were dirtied while in the host-side run loop: */
|
||||
static inline bool update_fp_enabled(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
@ -142,10 +146,10 @@ static inline bool __translate_far_to_hpfar(u64 far, u64 *hpfar)
|
||||
* saved the guest context yet, and we may return early...
|
||||
*/
|
||||
par = read_sysreg(par_el1);
|
||||
asm volatile("at s1e1r, %0" : : "r" (far));
|
||||
isb();
|
||||
|
||||
if (!__kvm_at("s1e1r", far))
|
||||
tmp = read_sysreg(par_el1);
|
||||
else
|
||||
tmp = SYS_PAR_EL1_F; /* back to the guest */
|
||||
write_sysreg(par, par_el1);
|
||||
|
||||
if (unlikely(tmp & SYS_PAR_EL1_F))
|
||||
@ -508,4 +512,31 @@ static inline void __set_host_arch_workaround_state(struct kvm_vcpu *vcpu)
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void __kvm_unexpected_el2_exception(void)
|
||||
{
|
||||
unsigned long addr, fixup;
|
||||
struct kvm_cpu_context *host_ctxt;
|
||||
struct exception_table_entry *entry, *end;
|
||||
unsigned long elr_el2 = read_sysreg(elr_el2);
|
||||
|
||||
entry = hyp_symbol_addr(__start___kvm_ex_table);
|
||||
end = hyp_symbol_addr(__stop___kvm_ex_table);
|
||||
host_ctxt = &__hyp_this_cpu_ptr(kvm_host_data)->host_ctxt;
|
||||
|
||||
while (entry < end) {
|
||||
addr = (unsigned long)&entry->insn + entry->insn;
|
||||
fixup = (unsigned long)&entry->fixup + entry->fixup;
|
||||
|
||||
if (addr != elr_el2) {
|
||||
entry++;
|
||||
continue;
|
||||
}
|
||||
|
||||
write_sysreg(fixup, elr_el2);
|
||||
return;
|
||||
}
|
||||
|
||||
hyp_panic(host_ctxt);
|
||||
}
|
||||
|
||||
#endif /* __ARM64_KVM_HYP_SWITCH_H__ */
|
||||
|
||||
@ -270,3 +270,8 @@ void __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
|
||||
read_sysreg(hpfar_el2), par, vcpu);
|
||||
unreachable();
|
||||
}
|
||||
|
||||
asmlinkage void kvm_unexpected_el2_exception(void)
|
||||
{
|
||||
return __kvm_unexpected_el2_exception();
|
||||
}
|
||||
|
||||
@ -340,10 +340,10 @@ void __vgic_v3_save_aprs(struct vgic_v3_cpu_if *cpu_if)
|
||||
case 7:
|
||||
cpu_if->vgic_ap0r[3] = __vgic_v3_read_ap0rn(3);
|
||||
cpu_if->vgic_ap0r[2] = __vgic_v3_read_ap0rn(2);
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case 6:
|
||||
cpu_if->vgic_ap0r[1] = __vgic_v3_read_ap0rn(1);
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
cpu_if->vgic_ap0r[0] = __vgic_v3_read_ap0rn(0);
|
||||
}
|
||||
@ -352,10 +352,10 @@ void __vgic_v3_save_aprs(struct vgic_v3_cpu_if *cpu_if)
|
||||
case 7:
|
||||
cpu_if->vgic_ap1r[3] = __vgic_v3_read_ap1rn(3);
|
||||
cpu_if->vgic_ap1r[2] = __vgic_v3_read_ap1rn(2);
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case 6:
|
||||
cpu_if->vgic_ap1r[1] = __vgic_v3_read_ap1rn(1);
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
cpu_if->vgic_ap1r[0] = __vgic_v3_read_ap1rn(0);
|
||||
}
|
||||
@ -373,10 +373,10 @@ void __vgic_v3_restore_aprs(struct vgic_v3_cpu_if *cpu_if)
|
||||
case 7:
|
||||
__vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[3], 3);
|
||||
__vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[2], 2);
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case 6:
|
||||
__vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[1], 1);
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
__vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[0], 0);
|
||||
}
|
||||
@ -385,10 +385,10 @@ void __vgic_v3_restore_aprs(struct vgic_v3_cpu_if *cpu_if)
|
||||
case 7:
|
||||
__vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[3], 3);
|
||||
__vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[2], 2);
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case 6:
|
||||
__vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[1], 1);
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
default:
|
||||
__vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[0], 0);
|
||||
}
|
||||
|
||||
@ -217,3 +217,8 @@ void __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
|
||||
__hyp_call_panic(spsr, elr, par, host_ctxt);
|
||||
unreachable();
|
||||
}
|
||||
|
||||
asmlinkage void kvm_unexpected_el2_exception(void)
|
||||
{
|
||||
return __kvm_unexpected_el2_exception();
|
||||
}
|
||||
|
||||
@ -343,7 +343,8 @@ static void unmap_stage2_p4ds(struct kvm_s2_mmu *mmu, pgd_t *pgd,
|
||||
* destroying the VM), otherwise another faulting VCPU may come in and mess
|
||||
* with things behind our backs.
|
||||
*/
|
||||
static void unmap_stage2_range(struct kvm_s2_mmu *mmu, phys_addr_t start, u64 size)
|
||||
static void __unmap_stage2_range(struct kvm_s2_mmu *mmu, phys_addr_t start, u64 size,
|
||||
bool may_block)
|
||||
{
|
||||
struct kvm *kvm = mmu->kvm;
|
||||
pgd_t *pgd;
|
||||
@ -369,11 +370,16 @@ static void unmap_stage2_range(struct kvm_s2_mmu *mmu, phys_addr_t start, u64 si
|
||||
* If the range is too large, release the kvm->mmu_lock
|
||||
* to prevent starvation and lockup detector warnings.
|
||||
*/
|
||||
if (next != end)
|
||||
if (may_block && next != end)
|
||||
cond_resched_lock(&kvm->mmu_lock);
|
||||
} while (pgd++, addr = next, addr != end);
|
||||
}
|
||||
|
||||
static void unmap_stage2_range(struct kvm_s2_mmu *mmu, phys_addr_t start, u64 size)
|
||||
{
|
||||
__unmap_stage2_range(mmu, start, size, true);
|
||||
}
|
||||
|
||||
static void stage2_flush_ptes(struct kvm_s2_mmu *mmu, pmd_t *pmd,
|
||||
phys_addr_t addr, phys_addr_t end)
|
||||
{
|
||||
@ -2208,18 +2214,21 @@ static int handle_hva_to_gpa(struct kvm *kvm,
|
||||
|
||||
static int kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, u64 size, void *data)
|
||||
{
|
||||
unmap_stage2_range(&kvm->arch.mmu, gpa, size);
|
||||
unsigned flags = *(unsigned *)data;
|
||||
bool may_block = flags & MMU_NOTIFIER_RANGE_BLOCKABLE;
|
||||
|
||||
__unmap_stage2_range(&kvm->arch.mmu, gpa, size, may_block);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int kvm_unmap_hva_range(struct kvm *kvm,
|
||||
unsigned long start, unsigned long end)
|
||||
unsigned long start, unsigned long end, unsigned flags)
|
||||
{
|
||||
if (!kvm->arch.mmu.pgd)
|
||||
return 0;
|
||||
|
||||
trace_kvm_unmap_hva_range(start, end);
|
||||
handle_hva_to_gpa(kvm, start, end, &kvm_unmap_hva_handler, NULL);
|
||||
handle_hva_to_gpa(kvm, start, end, &kvm_unmap_hva_handler, &flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -45,7 +45,7 @@ static u32 get_cpu_asid_bits(void)
|
||||
default:
|
||||
pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n",
|
||||
smp_processor_id(), fld);
|
||||
/* Fallthrough */
|
||||
fallthrough;
|
||||
case 0:
|
||||
asid = 8;
|
||||
break;
|
||||
|
||||
@ -220,7 +220,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
|
||||
regs->a4 = -EINTR;
|
||||
break;
|
||||
}
|
||||
/* fallthrough */
|
||||
fallthrough;
|
||||
case -ERESTARTNOINTR:
|
||||
do_restart:
|
||||
regs->a4 = regs->orig_a4;
|
||||
@ -252,7 +252,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs,
|
||||
break;
|
||||
}
|
||||
|
||||
/* fallthrough */
|
||||
fallthrough;
|
||||
case -ERESTARTNOINTR:
|
||||
regs->a4 = regs->orig_a4;
|
||||
regs->pc -= 4;
|
||||
|
||||
@ -194,7 +194,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs)
|
||||
regs->a0 = -EINTR;
|
||||
break;
|
||||
}
|
||||
/* fallthrough */
|
||||
fallthrough;
|
||||
case -ERESTARTNOINTR:
|
||||
regs->a0 = regs->orig_a0;
|
||||
regs->pc -= TRAP0_SIZE;
|
||||
|
||||
@ -227,7 +227,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka)
|
||||
regs->er0 = -EINTR;
|
||||
break;
|
||||
}
|
||||
/* fallthrough */
|
||||
fallthrough;
|
||||
case -ERESTARTNOINTR:
|
||||
do_restart:
|
||||
regs->er0 = regs->orig_er0;
|
||||
|
||||
@ -120,7 +120,7 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
|
||||
}
|
||||
case R_HEXAGON_HI16:
|
||||
value = (value>>16) & 0xffff;
|
||||
/* fallthrough */
|
||||
fallthrough;
|
||||
case R_HEXAGON_LO16:
|
||||
*location &= ~0x00c03fff;
|
||||
*location |= value & 0x3fff;
|
||||
|
||||
@ -155,7 +155,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs)
|
||||
regs->r00 = -EINTR;
|
||||
break;
|
||||
}
|
||||
/* Fall through */
|
||||
fallthrough;
|
||||
case -ERESTARTNOINTR:
|
||||
regs->r06 = regs->syscall_nr;
|
||||
pt_set_elr(regs, pt_elr(regs) - 4);
|
||||
|
||||
@ -366,6 +366,15 @@ pgd_index (unsigned long address)
|
||||
}
|
||||
#define pgd_index pgd_index
|
||||
|
||||
/*
|
||||
* In the kernel's mapped region we know everything is in region number 5, so
|
||||
* as an optimisation its PGD already points to the area for that region.
|
||||
* However, this also means that we cannot use pgd_index() and we must
|
||||
* never add the region here.
|
||||
*/
|
||||
#define pgd_offset_k(addr) \
|
||||
(init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
|
||||
|
||||
/* Look up a pgd entry in the gate area. On IA-64, the gate-area
|
||||
resides in the kernel-mapped segment, hence we use pgd_offset_k()
|
||||
here. */
|
||||
|
||||
@ -163,7 +163,7 @@ kdump_init_notifier(struct notifier_block *self, unsigned long val, void *data)
|
||||
case DIE_INIT_MONARCH_LEAVE:
|
||||
if (!kdump_freeze_monarch)
|
||||
break;
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case DIE_INIT_SLAVE_LEAVE:
|
||||
case DIE_INIT_MONARCH_ENTER:
|
||||
case DIE_MCA_RENDZVOUS_LEAVE:
|
||||
|
||||
@ -654,7 +654,7 @@ do_reloc (struct module *mod, uint8_t r_type, Elf64_Sym *sym, uint64_t addend,
|
||||
}
|
||||
} else if (!is_internal(mod, val))
|
||||
val = get_plt(mod, location, val, &ok);
|
||||
/* FALL THROUGH */
|
||||
fallthrough;
|
||||
default:
|
||||
val -= bundle(location);
|
||||
break;
|
||||
|
||||
@ -3472,7 +3472,7 @@ pfm_restart(pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs)
|
||||
break;
|
||||
case PFM_CTX_LOADED:
|
||||
if (CTX_HAS_SMPL(ctx) && fmt->fmt_restart_active) break;
|
||||
/* fall through */
|
||||
fallthrough;
|
||||
case PFM_CTX_UNLOADED:
|
||||
case PFM_CTX_ZOMBIE:
|
||||
DPRINT(("invalid state=%d\n", state));
|
||||
|
||||
@ -374,7 +374,7 @@ ia64_do_signal (struct sigscratch *scr, long in_syscall)
|
||||
/* note: scr->pt.r10 is already -1 */
|
||||
break;
|
||||
}
|
||||
/*FALLTHRU*/
|
||||
fallthrough;
|
||||
case ERESTARTNOINTR:
|
||||
ia64_decrement_ip(&scr->pt);
|
||||
restart = 0; /* don't restart twice if handle_signal() fails... */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user