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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/amdgpu: implement initialization part on VCN2.0 for SRIOV
something need to do for VCN2.0 enablement on SRIOV: 1)use one dec ring and one enc ring 2)allocate MM table for MMSCH usage 3)implement SRIOV version vcn_start which orgnize vcn programing with patcket format and implement start mmsch for to run those packet 4)doorbell is changed for SRIOV Singed-off-by: darlington Opara <darlington.opara@amd.com> Signed-off-by: Jinage Zhao <jiange.zhao@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Monk Liu
Alex Deucher
parent
fe44249186
commit
dd26858a9c
@ -29,6 +29,7 @@
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#include "soc15d.h"
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#include "amdgpu_pm.h"
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#include "amdgpu_psp.h"
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#include "mmsch_v2_0.h"
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#include "vcn/vcn_2_0_0_offset.h"
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#include "vcn/vcn_2_0_0_sh_mask.h"
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@ -54,7 +55,7 @@ static int vcn_v2_0_set_powergating_state(void *handle,
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enum amd_powergating_state state);
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static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
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int inst_idx, struct dpg_pause_state *new_state);
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static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
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/**
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* vcn_v2_0_early_init - set function pointers
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*
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@ -67,7 +68,10 @@ static int vcn_v2_0_early_init(void *handle)
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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adev->vcn.num_vcn_inst = 1;
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adev->vcn.num_enc_rings = 2;
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if (amdgpu_sriov_vf(adev))
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adev->vcn.num_enc_rings = 1;
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else
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adev->vcn.num_enc_rings = 2;
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vcn_v2_0_set_dec_ring_funcs(adev);
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vcn_v2_0_set_enc_ring_funcs(adev);
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@ -154,7 +158,10 @@ static int vcn_v2_0_sw_init(void *handle)
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for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
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ring = &adev->vcn.inst->ring_enc[i];
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ring->use_doorbell = true;
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ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
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if (!amdgpu_sriov_vf(adev))
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ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
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else
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ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
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sprintf(ring->name, "vcn_enc%d", i);
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r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
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if (r)
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@ -163,6 +170,10 @@ static int vcn_v2_0_sw_init(void *handle)
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adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
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r = amdgpu_virt_alloc_mm_table(adev);
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if (r)
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return r;
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return 0;
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}
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@ -178,6 +189,8 @@ static int vcn_v2_0_sw_fini(void *handle)
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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amdgpu_virt_free_mm_table(adev);
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r = amdgpu_vcn_suspend(adev);
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if (r)
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return r;
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@ -203,6 +216,9 @@ static int vcn_v2_0_hw_init(void *handle)
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adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
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ring->doorbell_index, 0);
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if (amdgpu_sriov_vf(adev))
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vcn_v2_0_start_sriov(adev);
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r = amdgpu_ring_test_helper(ring);
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if (r)
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goto done;
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@ -1680,6 +1696,215 @@ static int vcn_v2_0_set_powergating_state(void *handle,
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return ret;
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}
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static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,
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struct amdgpu_mm_table *table)
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{
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uint32_t data = 0, loop;
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uint64_t addr = table->gpu_addr;
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struct mmsch_v2_0_init_header *header;
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uint32_t size;
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int i;
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header = (struct mmsch_v2_0_init_header *)table->cpu_addr;
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size = header->header_size + header->vcn_table_size;
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/* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
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* of memory descriptor location
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*/
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WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
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WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
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/* 2, update vmid of descriptor */
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data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
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data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
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/* use domain0 for MM scheduler */
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data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
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WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
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/* 3, notify mmsch about the size of this descriptor */
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WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
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/* 4, set resp to zero */
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WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
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adev->vcn.inst->ring_dec.wptr = 0;
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adev->vcn.inst->ring_dec.wptr_old = 0;
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vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
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for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
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adev->vcn.inst->ring_enc[i].wptr = 0;
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adev->vcn.inst->ring_enc[i].wptr_old = 0;
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vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
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}
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/* 5, kick off the initialization and wait until
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* VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
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*/
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WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
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data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
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loop = 1000;
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while ((data & 0x10000002) != 0x10000002) {
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udelay(10);
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data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
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loop--;
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if (!loop)
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break;
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}
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if (!loop) {
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DRM_ERROR("failed to init MMSCH, " \
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"mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);
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return -EBUSY;
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}
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return 0;
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}
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static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
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{
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int r;
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uint32_t tmp;
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struct amdgpu_ring *ring;
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uint32_t offset, size;
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uint32_t table_size = 0;
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struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
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struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
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struct mmsch_v2_0_cmd_direct_polling direct_poll = { {0} };
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struct mmsch_v2_0_cmd_end end = { {0} };
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struct mmsch_v2_0_init_header *header;
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uint32_t *init_table = adev->virt.mm_table.cpu_addr;
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uint8_t i = 0;
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header = (struct mmsch_v2_0_init_header *)init_table;
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direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
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direct_rd_mod_wt.cmd_header.command_type =
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MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
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direct_poll.cmd_header.command_type =
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MMSCH_COMMAND__DIRECT_REG_POLLING;
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end.cmd_header.command_type = MMSCH_COMMAND__END;
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if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {
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header->version = MMSCH_VERSION;
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header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;
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header->vcn_table_offset = header->header_size;
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init_table += header->vcn_table_offset;
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size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
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MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
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SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
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0xFFFFFFFF, 0x00000004);
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/* mc resume*/
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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tmp = AMDGPU_UCODE_ID_VCN;
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i,
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mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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adev->firmware.ucode[tmp].tmr_mc_addr_lo);
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i,
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mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
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adev->firmware.ucode[tmp].tmr_mc_addr_hi);
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offset = 0;
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} else {
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i,
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mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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lower_32_bits(adev->vcn.inst->gpu_addr));
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i,
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mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
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upper_32_bits(adev->vcn.inst->gpu_addr));
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offset = size;
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}
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
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0);
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
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size);
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i,
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mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
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lower_32_bits(adev->vcn.inst->gpu_addr + offset));
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i,
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mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
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upper_32_bits(adev->vcn.inst->gpu_addr + offset));
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
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0);
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
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AMDGPU_VCN_STACK_SIZE);
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i,
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mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
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lower_32_bits(adev->vcn.inst->gpu_addr + offset +
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AMDGPU_VCN_STACK_SIZE));
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i,
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mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
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upper_32_bits(adev->vcn.inst->gpu_addr + offset +
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AMDGPU_VCN_STACK_SIZE));
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
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0);
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
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AMDGPU_VCN_CONTEXT_SIZE);
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for (r = 0; r < adev->vcn.num_enc_rings; ++r) {
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ring = &adev->vcn.inst->ring_enc[r];
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ring->wptr = 0;
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
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lower_32_bits(ring->gpu_addr));
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
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upper_32_bits(ring->gpu_addr));
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
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ring->ring_size / 4);
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}
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ring = &adev->vcn.inst->ring_dec;
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ring->wptr = 0;
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i,
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mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
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lower_32_bits(ring->gpu_addr));
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i,
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mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
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upper_32_bits(ring->gpu_addr));
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/* force RBC into idle state */
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tmp = order_base_2(ring->ring_size);
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tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
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MMSCH_V2_0_INSERT_DIRECT_WT(
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SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
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/* add end packet */
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tmp = sizeof(struct mmsch_v2_0_cmd_end);
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memcpy((void *)init_table, &end, tmp);
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table_size += (tmp / 4);
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header->vcn_table_size = table_size;
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}
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return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
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}
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static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
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.name = "vcn_v2_0",
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.early_init = vcn_v2_0_early_init,
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