AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-11-27 01:40:56 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM: shmobile: r8a7794: Add MMP and VSP1 clocks to device tree

Browse Source 
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Yoshifumi Hosoya 2014-11-12 17:55:57 +09:00 committed by Simon Horman
parent 3e58a5424c
commit dc3cf93d89
2 changed files with 15 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/arm/boot/dts/r8a7794.dtsi
View File

@ -461,15 +461,19 @@ mstp0_clks: mstp0_clks@e6150130 {
mstp1_clks: mstp1_clks@e6150134 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
clocks = <&p_clk>, <&zg_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
<&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
<&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7794_CLK_TMU1 R8A7794_CLK_3DG R8A7794_CLK_TMU3
R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 R8A7794_CLK_TMU0
R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
>;
clock-output-names =
"tmu1", "3dg", "tmu3", "tmu2", "cmt0", "tmu0";
"vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
"tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
};
mstp2_clks: mstp2_clks@e6150138 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";

6
include/dt-bindings/clock/r8a7794-clock.h
View File

@ -26,12 +26,18 @@
#define R8A7794_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7794_CLK_VCP0 1
#define R8A7794_CLK_VPC0 3
#define R8A7794_CLK_TMU1 11
#define R8A7794_CLK_3DG 12
#define R8A7794_CLK_2DDMAC 15
#define R8A7794_CLK_FDP1_0 19
#define R8A7794_CLK_TMU3 21
#define R8A7794_CLK_TMU2 22
#define R8A7794_CLK_CMT0 24
#define R8A7794_CLK_TMU0 25
#define R8A7794_CLK_VSP1_DU0 28
#define R8A7794_CLK_VSP1_S 31
/* MSTP2 */
#define R8A7794_CLK_SCIFA2 2