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drm/amdgpu: add define for gfx ras subblock
Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dennis Li
Alex Deucher
parent
4bb6b8c758
commit
dc23a08f03
@ -52,6 +52,236 @@ enum amdgpu_ras_block {
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#define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST
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#define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
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enum amdgpu_ras_gfx_subblock {
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/* CPC */
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AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
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AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
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AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
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AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
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AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
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AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
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AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
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AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
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AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
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AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
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AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
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/* CPF */
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AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
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AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
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AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
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AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
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/* CPG */
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AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
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AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
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AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
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AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
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/* GDS */
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AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
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AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
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AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
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AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
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AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
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AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
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/* SPI */
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AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
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/* SQ */
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AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
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AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
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AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
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AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
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/* SQC (3 ranges) */
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AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
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/* SQC range 0 */
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AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
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AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
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AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
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AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
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/* SQC range 1 */
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AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
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AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
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AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
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AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
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AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
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AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
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AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
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/* SQC range 2 */
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AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
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AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
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AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
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AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
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AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
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AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
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AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
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AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
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AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
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AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
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/* TA */
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AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
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AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
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AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
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AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
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AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
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AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
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/* TCA */
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AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
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AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
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AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
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AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
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/* TCC (5 sub-ranges) */
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
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/* TCC range 0 */
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
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AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
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AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
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AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
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AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
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AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
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AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
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AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
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AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
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/* TCC range 1 */
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
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AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
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AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
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AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
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/* TCC range 2 */
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
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AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
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AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
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AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
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AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
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AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
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AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
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AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
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AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
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AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
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/* TCC range 3 */
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
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AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
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AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
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AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
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/* TCC range 4 */
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
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AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
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AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
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AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
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AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
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/* TCI */
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AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
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/* TCP */
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AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
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AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
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AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
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AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
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AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
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AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
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AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
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AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
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AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
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/* TD */
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AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
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AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
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AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
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AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
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/* EA (3 sub-ranges) */
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AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
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/* EA range 0 */
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AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
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AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
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AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
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AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
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AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
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AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
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AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
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AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
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AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
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AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
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AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
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AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
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AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
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/* EA range 1 */
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AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
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AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
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AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
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AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
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AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
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AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
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AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
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AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
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AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
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AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
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AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
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/* EA range 2 */
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AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
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AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
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AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
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AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
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AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
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AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
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AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
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AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
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AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
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AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
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/* UTC VM L2 bank */
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AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
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/* UTC VM walker */
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AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
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/* UTC ATC L2 2MB cache */
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AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
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/* UTC ATC L2 4KB cache */
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AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
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AMDGPU_RAS_BLOCK__GFX_MAX
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};
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enum amdgpu_ras_error_type {
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AMDGPU_RAS_ERROR__NONE = 0,
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AMDGPU_RAS_ERROR__PARITY = 1,
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@ -121,6 +121,207 @@ MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin");
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#define mmTCP_CHAN_STEER_5_ARCT 0x0b0c
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#define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0
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enum ta_ras_gfx_subblock {
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/*CPC*/
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TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
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TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START,
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TA_RAS_BLOCK__GFX_CPC_UCODE,
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TA_RAS_BLOCK__GFX_DC_STATE_ME1,
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TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
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TA_RAS_BLOCK__GFX_DC_RESTORE_ME1,
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TA_RAS_BLOCK__GFX_DC_STATE_ME2,
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TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
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TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
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TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
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/* CPF*/
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TA_RAS_BLOCK__GFX_CPF_INDEX_START,
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TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START,
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TA_RAS_BLOCK__GFX_CPF_ROQ_ME1,
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TA_RAS_BLOCK__GFX_CPF_TAG,
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TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG,
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/* CPG*/
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TA_RAS_BLOCK__GFX_CPG_INDEX_START,
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TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START,
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TA_RAS_BLOCK__GFX_CPG_DMA_TAG,
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TA_RAS_BLOCK__GFX_CPG_TAG,
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TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG,
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/* GDS*/
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TA_RAS_BLOCK__GFX_GDS_INDEX_START,
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TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START,
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TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
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TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
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TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
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TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
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TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
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/* SPI*/
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TA_RAS_BLOCK__GFX_SPI_SR_MEM,
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/* SQ*/
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TA_RAS_BLOCK__GFX_SQ_INDEX_START,
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TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START,
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TA_RAS_BLOCK__GFX_SQ_LDS_D,
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TA_RAS_BLOCK__GFX_SQ_LDS_I,
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TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/
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TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR,
|
||||
/* SQC (3 ranges)*/
|
||||
TA_RAS_BLOCK__GFX_SQC_INDEX_START,
|
||||
/* SQC range 0*/
|
||||
TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START,
|
||||
TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
|
||||
TA_RAS_BLOCK__GFX_SQC_INDEX0_START,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
|
||||
TA_RAS_BLOCK__GFX_SQC_INDEX0_END =
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
|
||||
/* SQC range 1*/
|
||||
TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
|
||||
TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
|
||||
TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
|
||||
TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
|
||||
TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
|
||||
TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
|
||||
TA_RAS_BLOCK__GFX_SQC_INDEX1_END =
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
|
||||
/* SQC range 2*/
|
||||
TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
|
||||
TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
|
||||
TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
|
||||
TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
|
||||
TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
|
||||
TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
|
||||
TA_RAS_BLOCK__GFX_SQC_INDEX2_END =
|
||||
TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
|
||||
TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END,
|
||||
/* TA*/
|
||||
TA_RAS_BLOCK__GFX_TA_INDEX_START,
|
||||
TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START,
|
||||
TA_RAS_BLOCK__GFX_TA_FS_AFIFO,
|
||||
TA_RAS_BLOCK__GFX_TA_FL_LFIFO,
|
||||
TA_RAS_BLOCK__GFX_TA_FX_LFIFO,
|
||||
TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
|
||||
TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
|
||||
/* TCA*/
|
||||
TA_RAS_BLOCK__GFX_TCA_INDEX_START,
|
||||
TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START,
|
||||
TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
|
||||
TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
|
||||
/* TCC (5 sub-ranges)*/
|
||||
TA_RAS_BLOCK__GFX_TCC_INDEX_START,
|
||||
/* TCC range 0*/
|
||||
TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START,
|
||||
TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START,
|
||||
TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
|
||||
TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
|
||||
TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
|
||||
TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
|
||||
TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
|
||||
TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
|
||||
TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
|
||||
TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
|
||||
/* TCC range 1*/
|
||||
TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
|
||||
TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
|
||||
TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
|
||||
TA_RAS_BLOCK__GFX_TCC_INDEX1_END =
|
||||
TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
|
||||
/* TCC range 2*/
|
||||
TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
|
||||
TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
|
||||
TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
|
||||
TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
|
||||
TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
|
||||
TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
|
||||
TA_RAS_BLOCK__GFX_TCC_SRC_FIFO,
|
||||
TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
|
||||
TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
|
||||
TA_RAS_BLOCK__GFX_TCC_INDEX2_END =
|
||||
TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
|
||||
/* TCC range 3*/
|
||||
TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
|
||||
TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
|
||||
TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
|
||||
TA_RAS_BLOCK__GFX_TCC_INDEX3_END =
|
||||
TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
|
||||
/* TCC range 4*/
|
||||
TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
|
||||
TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
|
||||
TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
|
||||
TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
|
||||
TA_RAS_BLOCK__GFX_TCC_INDEX4_END =
|
||||
TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
|
||||
TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END,
|
||||
/* TCI*/
|
||||
TA_RAS_BLOCK__GFX_TCI_WRITE_RAM,
|
||||
/* TCP*/
|
||||
TA_RAS_BLOCK__GFX_TCP_INDEX_START,
|
||||
TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START,
|
||||
TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
|
||||
TA_RAS_BLOCK__GFX_TCP_CMD_FIFO,
|
||||
TA_RAS_BLOCK__GFX_TCP_VM_FIFO,
|
||||
TA_RAS_BLOCK__GFX_TCP_DB_RAM,
|
||||
TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
|
||||
TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
|
||||
TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
|
||||
/* TD*/
|
||||
TA_RAS_BLOCK__GFX_TD_INDEX_START,
|
||||
TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START,
|
||||
TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
|
||||
TA_RAS_BLOCK__GFX_TD_CS_FIFO,
|
||||
TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO,
|
||||
/* EA (3 sub-ranges)*/
|
||||
TA_RAS_BLOCK__GFX_EA_INDEX_START,
|
||||
/* EA range 0*/
|
||||
TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START,
|
||||
TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START,
|
||||
TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
|
||||
TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
|
||||
TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
|
||||
TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
|
||||
TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
|
||||
TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
|
||||
TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
|
||||
TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
|
||||
/* EA range 1*/
|
||||
TA_RAS_BLOCK__GFX_EA_INDEX1_START,
|
||||
TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START,
|
||||
TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
|
||||
TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
|
||||
TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
|
||||
TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
|
||||
TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
|
||||
TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
|
||||
TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
|
||||
/* EA range 2*/
|
||||
TA_RAS_BLOCK__GFX_EA_INDEX2_START,
|
||||
TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START,
|
||||
TA_RAS_BLOCK__GFX_EA_MAM_D1MEM,
|
||||
TA_RAS_BLOCK__GFX_EA_MAM_D2MEM,
|
||||
TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
|
||||
TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
|
||||
TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END,
|
||||
/* UTC VM L2 bank*/
|
||||
TA_RAS_BLOCK__UTC_VML2_BANK_CACHE,
|
||||
/* UTC VM walker*/
|
||||
TA_RAS_BLOCK__UTC_VML2_WALKER,
|
||||
/* UTC ATC L2 2MB cache*/
|
||||
TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
|
||||
/* UTC ATC L2 4KB cache*/
|
||||
TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
|
||||
TA_RAS_BLOCK__GFX_MAX
|
||||
};
|
||||
static const struct soc15_reg_golden golden_settings_gc_9_0[] =
|
||||
{
|
||||
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user