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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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qed: Initialize hardware for new protocols
RoCE and iSCSI would require some added/changed hw configuration in order to properly run; The biggest single change being the requirement of allocating and mapping host memory for several HW blocks that aren't being used by qede [SRC, QM, TM, etc.]. In addition, whereas qede is only using context memory for HW blocks, the new protocol would also require task memories to be added. Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yuval Mintz
David S. Miller
parent
c5ac93191d
commit
dbb799c397
@ -187,6 +187,8 @@ struct qed_hw_info {
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#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
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#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
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#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
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RESC_NUM(_p_hwfn, resc))
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#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
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u8 num_tc;
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@ -259,6 +261,7 @@ struct qed_qm_info {
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u8 pure_lb_pq;
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u8 offload_pq;
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u8 pure_ack_pq;
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u8 ooo_pq;
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u8 vf_queues_offset;
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u16 num_pqs;
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u16 num_vf_pqs;
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@ -271,6 +274,7 @@ struct qed_qm_info {
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u8 pf_wfq;
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u32 pf_rl;
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struct qed_wfq_data *wfq_data;
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u8 num_pf_rls;
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};
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struct storm_stats {
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@ -316,6 +320,7 @@ struct qed_hwfn {
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bool hw_init_done;
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u8 num_funcs_on_engine;
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u8 enabled_func_idx;
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/* BAR access */
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void __iomem *regview;
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@ -354,6 +359,9 @@ struct qed_hwfn {
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/* Protocol related */
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struct qed_pf_params pf_params;
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bool b_rdma_enabled_in_prs;
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u32 rdma_prs_search_reg;
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/* Array of sb_info of all status blocks */
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struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
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u16 num_sbs;
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@ -559,6 +567,7 @@ static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
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}
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#define PURE_LB_TC 8
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#define OOO_LB_TC 9
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int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
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void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate);
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File diff suppressed because it is too large
Load Diff
@ -21,6 +21,14 @@ struct qed_cxt_info {
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enum protocol_type type;
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};
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#define MAX_TID_BLOCKS 512
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struct qed_tid_mem {
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u32 tid_size;
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u32 num_tids_per_block;
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u32 waste;
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u8 *blocks[MAX_TID_BLOCKS]; /* 4K */
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};
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/**
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* @brief qed_cxt_acquire - Acquire a new cid of a specific protocol type
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*
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@ -46,8 +54,22 @@ int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
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int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn,
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struct qed_cxt_info *p_info);
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/**
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* @brief qed_cxt_get_tid_mem_info
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*
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* @param p_hwfn
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* @param p_info
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*
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* @return int
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*/
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int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
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struct qed_tid_mem *p_info);
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#define QED_CXT_ISCSI_TID_SEG PROTOCOLID_ISCSI
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#define QED_CXT_ROCE_TID_SEG PROTOCOLID_ROCE
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enum qed_cxt_elem_type {
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QED_ELEM_CXT,
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QED_ELEM_SRQ,
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QED_ELEM_TASK
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};
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@ -149,4 +171,6 @@ int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
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void qed_cxt_release_cid(struct qed_hwfn *p_hwfn,
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u32 cid);
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#define QED_CTX_WORKING_MEM 0
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#define QED_CTX_FL_MEM 1
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#endif
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@ -161,9 +161,13 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
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u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
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struct qed_qm_info *qm_info = &p_hwfn->qm_info;
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struct init_qm_port_params *p_qm_port;
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bool init_rdma_offload_pq = false;
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bool init_pure_ack_pq = false;
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bool init_ooo_pq = false;
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u16 num_pqs, multi_cos_tcs = 1;
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u8 pf_wfq = qm_info->pf_wfq;
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u32 pf_rl = qm_info->pf_rl;
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u16 num_pf_rls = 0;
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u16 num_vfs = 0;
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#ifdef CONFIG_QED_SRIOV
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@ -175,6 +179,25 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
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num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */
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num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
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if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
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num_pqs++; /* for RoCE queue */
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init_rdma_offload_pq = true;
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/* we subtract num_vfs because each require a rate limiter,
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* and one default rate limiter
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*/
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if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn)
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num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1;
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num_pqs += num_pf_rls;
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qm_info->num_pf_rls = (u8) num_pf_rls;
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}
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if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
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num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */
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init_pure_ack_pq = true;
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init_ooo_pq = true;
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}
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/* Sanity checking that setup requires legal number of resources */
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if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
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DP_ERR(p_hwfn,
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@ -212,12 +235,22 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
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vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
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/* First init rate limited queues */
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for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
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qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
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qm_info->qm_pq_params[curr_queue].tc_id =
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p_hwfn->hw_info.non_offload_tc;
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qm_info->qm_pq_params[curr_queue].wrr_group = 1;
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qm_info->qm_pq_params[curr_queue].rl_valid = 1;
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}
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/* First init per-TC PQs */
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for (i = 0; i < multi_cos_tcs; i++) {
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struct init_qm_pq_params *params =
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&qm_info->qm_pq_params[curr_queue++];
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if (p_hwfn->hw_info.personality == QED_PCI_ETH) {
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if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
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p_hwfn->hw_info.personality == QED_PCI_ETH) {
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params->vport_id = vport_id;
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params->tc_id = p_hwfn->hw_info.non_offload_tc;
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params->wrr_group = 1;
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@ -237,6 +270,32 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
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curr_queue++;
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qm_info->offload_pq = 0;
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if (init_rdma_offload_pq) {
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qm_info->offload_pq = curr_queue;
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qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
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qm_info->qm_pq_params[curr_queue].tc_id =
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p_hwfn->hw_info.offload_tc;
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qm_info->qm_pq_params[curr_queue].wrr_group = 1;
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curr_queue++;
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}
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if (init_pure_ack_pq) {
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qm_info->pure_ack_pq = curr_queue;
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qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
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qm_info->qm_pq_params[curr_queue].tc_id =
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p_hwfn->hw_info.offload_tc;
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qm_info->qm_pq_params[curr_queue].wrr_group = 1;
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curr_queue++;
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}
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if (init_ooo_pq) {
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qm_info->ooo_pq = curr_queue;
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qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
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qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
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qm_info->qm_pq_params[curr_queue].wrr_group = 1;
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curr_queue++;
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}
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/* Then init per-VF PQs */
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vf_offset = curr_queue;
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for (i = 0; i < num_vfs; i++) {
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@ -371,21 +430,20 @@ int qed_resc_alloc(struct qed_dev *cdev)
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if (!p_hwfn->p_tx_cids) {
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DP_NOTICE(p_hwfn,
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"Failed to allocate memory for Tx Cids\n");
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rc = -ENOMEM;
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goto alloc_err;
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goto alloc_no_mem;
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}
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p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
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if (!p_hwfn->p_rx_cids) {
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DP_NOTICE(p_hwfn,
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"Failed to allocate memory for Rx Cids\n");
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rc = -ENOMEM;
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goto alloc_err;
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goto alloc_no_mem;
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}
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}
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for_each_hwfn(cdev, i) {
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struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
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u32 n_eqes, num_cons;
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/* First allocate the context manager structure */
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rc = qed_cxt_mngr_alloc(p_hwfn);
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@ -434,18 +492,34 @@ int qed_resc_alloc(struct qed_dev *cdev)
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goto alloc_err;
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/* EQ */
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p_eq = qed_eq_alloc(p_hwfn, 256);
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if (!p_eq) {
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rc = -ENOMEM;
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n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
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if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
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num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
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PROTOCOLID_ROCE,
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0) * 2;
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n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
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} else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
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num_cons =
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qed_cxt_get_proto_cid_count(p_hwfn,
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PROTOCOLID_ISCSI, 0);
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n_eqes += 2 * num_cons;
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}
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if (n_eqes > 0xFFFF) {
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DP_ERR(p_hwfn,
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"Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
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n_eqes, 0xFFFF);
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goto alloc_err;
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}
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p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
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if (!p_eq)
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goto alloc_no_mem;
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p_hwfn->p_eq = p_eq;
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p_consq = qed_consq_alloc(p_hwfn);
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if (!p_consq) {
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rc = -ENOMEM;
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goto alloc_err;
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}
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if (!p_consq)
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goto alloc_no_mem;
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p_hwfn->p_consq = p_consq;
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/* DMA info initialization */
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@ -474,6 +548,8 @@ int qed_resc_alloc(struct qed_dev *cdev)
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return 0;
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alloc_no_mem:
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rc = -ENOMEM;
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alloc_err:
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qed_resc_free(cdev);
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return rc;
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@ -639,6 +715,7 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
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struct qed_qm_info *qm_info = &p_hwfn->qm_info;
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struct qed_qm_common_rt_init_params params;
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struct qed_dev *cdev = p_hwfn->cdev;
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u16 num_pfs, pf_id;
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u32 concrete_fid;
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int rc = 0;
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u8 vf_id;
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@ -687,9 +764,16 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
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qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
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qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
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/* Disable relaxed ordering in the PCI config space */
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qed_wr(p_hwfn, p_ptt, 0x20b4,
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qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10);
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if (QED_IS_BB(p_hwfn->cdev)) {
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num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
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for (pf_id = 0; pf_id < num_pfs; pf_id++) {
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qed_fid_pretend(p_hwfn, p_ptt, pf_id);
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qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
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qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
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}
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/* pretend to original PF */
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qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
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}
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for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
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concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
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@ -779,7 +863,8 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
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}
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/* Protocl Configuration */
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STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0);
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STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
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(p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
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STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
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STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
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@ -1256,8 +1341,9 @@ static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
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num_features);
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}
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static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
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static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
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{
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u8 enabled_func_idx = p_hwfn->enabled_func_idx;
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u32 *resc_start = p_hwfn->hw_info.resc_start;
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u8 num_funcs = p_hwfn->num_funcs_on_engine;
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u32 *resc_num = p_hwfn->hw_info.resc_num;
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@ -1281,14 +1367,22 @@ static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
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resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
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resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
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resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
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resc_num[QED_RL] = 8;
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resc_num[QED_RL] = min_t(u32, 64, resc_num[QED_VPORT]);
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resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
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resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
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num_funcs;
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resc_num[QED_ILT] = 950;
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resc_num[QED_ILT] = PXP_NUM_ILT_RECORDS_BB / num_funcs;
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for (i = 0; i < QED_MAX_RESC; i++)
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resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
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resc_start[i] = resc_num[i] * enabled_func_idx;
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/* Sanity for ILT */
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if (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB) {
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DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
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RESC_START(p_hwfn, QED_ILT),
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RESC_END(p_hwfn, QED_ILT) - 1);
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return -EINVAL;
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}
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qed_hw_set_feat(p_hwfn);
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@ -1318,6 +1412,8 @@ static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
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p_hwfn->hw_info.resc_start[QED_VLAN],
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p_hwfn->hw_info.resc_num[QED_ILT],
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p_hwfn->hw_info.resc_start[QED_ILT]);
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return 0;
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}
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static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn,
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@ -1484,8 +1580,8 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn,
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static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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u32 reg_function_hide, tmp, eng_mask;
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u8 num_funcs;
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u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
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u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
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||||
num_funcs = MAX_NUM_PFS_BB;
|
||||
|
||||
@ -1515,9 +1611,19 @@ static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
|
||||
num_funcs++;
|
||||
tmp >>= 0x1;
|
||||
}
|
||||
|
||||
/* Get the PF index within the enabled functions */
|
||||
low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
|
||||
tmp = reg_function_hide & eng_mask & low_pfs_mask;
|
||||
while (tmp) {
|
||||
if (tmp & 0x1)
|
||||
enabled_func_idx--;
|
||||
tmp >>= 0x1;
|
||||
}
|
||||
}
|
||||
|
||||
p_hwfn->num_funcs_on_engine = num_funcs;
|
||||
p_hwfn->enabled_func_idx = enabled_func_idx;
|
||||
|
||||
DP_VERBOSE(p_hwfn,
|
||||
NETIF_MSG_PROBE,
|
||||
@ -1587,9 +1693,7 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn,
|
||||
|
||||
qed_get_num_funcs(p_hwfn, p_ptt);
|
||||
|
||||
qed_hw_get_resc(p_hwfn);
|
||||
|
||||
return rc;
|
||||
return qed_hw_get_resc(p_hwfn);
|
||||
}
|
||||
|
||||
static int qed_get_dev_info(struct qed_dev *cdev)
|
||||
|
||||
@ -791,16 +791,16 @@ qed_dmae_host2host(struct qed_hwfn *p_hwfn,
|
||||
}
|
||||
|
||||
u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn,
|
||||
enum protocol_type proto,
|
||||
union qed_qm_pq_params *p_params)
|
||||
enum protocol_type proto, union qed_qm_pq_params *p_params)
|
||||
{
|
||||
u16 pq_id = 0;
|
||||
|
||||
if ((proto == PROTOCOLID_CORE || proto == PROTOCOLID_ETH) &&
|
||||
!p_params) {
|
||||
if ((proto == PROTOCOLID_CORE ||
|
||||
proto == PROTOCOLID_ETH ||
|
||||
proto == PROTOCOLID_ISCSI ||
|
||||
proto == PROTOCOLID_ROCE) && !p_params) {
|
||||
DP_NOTICE(p_hwfn,
|
||||
"Protocol %d received NULL PQ params\n",
|
||||
proto);
|
||||
"Protocol %d received NULL PQ params\n", proto);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -808,6 +808,8 @@ u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn,
|
||||
case PROTOCOLID_CORE:
|
||||
if (p_params->core.tc == LB_TC)
|
||||
pq_id = p_hwfn->qm_info.pure_lb_pq;
|
||||
else if (p_params->core.tc == OOO_LB_TC)
|
||||
pq_id = p_hwfn->qm_info.ooo_pq;
|
||||
else
|
||||
pq_id = p_hwfn->qm_info.offload_pq;
|
||||
break;
|
||||
@ -817,6 +819,18 @@ u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn,
|
||||
pq_id += p_hwfn->qm_info.vf_queues_offset +
|
||||
p_params->eth.vf_id;
|
||||
break;
|
||||
case PROTOCOLID_ISCSI:
|
||||
if (p_params->iscsi.q_idx == 1)
|
||||
pq_id = p_hwfn->qm_info.pure_ack_pq;
|
||||
break;
|
||||
case PROTOCOLID_ROCE:
|
||||
if (p_params->roce.dcqcn)
|
||||
pq_id = p_params->roce.qpid;
|
||||
else
|
||||
pq_id = p_hwfn->qm_info.offload_pq;
|
||||
if (pq_id > p_hwfn->qm_info.num_pf_rls)
|
||||
pq_id = p_hwfn->qm_info.offload_pq;
|
||||
break;
|
||||
default:
|
||||
pq_id = 0;
|
||||
}
|
||||
|
||||
@ -253,6 +253,10 @@ int qed_dmae_info_alloc(struct qed_hwfn *p_hwfn);
|
||||
void qed_dmae_info_free(struct qed_hwfn *p_hwfn);
|
||||
|
||||
union qed_qm_pq_params {
|
||||
struct {
|
||||
u8 q_idx;
|
||||
} iscsi;
|
||||
|
||||
struct {
|
||||
u8 tc;
|
||||
} core;
|
||||
@ -262,11 +266,15 @@ union qed_qm_pq_params {
|
||||
u8 vf_id;
|
||||
u8 tc;
|
||||
} eth;
|
||||
|
||||
struct {
|
||||
u8 dcqcn;
|
||||
u8 qpid; /* roce relative */
|
||||
} roce;
|
||||
};
|
||||
|
||||
u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn,
|
||||
enum protocol_type proto,
|
||||
union qed_qm_pq_params *params);
|
||||
enum protocol_type proto, union qed_qm_pq_params *params);
|
||||
|
||||
int qed_init_fw_data(struct qed_dev *cdev,
|
||||
const u8 *fw_data);
|
||||
|
||||
@ -27,6 +27,35 @@
|
||||
#define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
|
||||
0xff << 24)
|
||||
|
||||
#define CDU_REG_SEGMENT0_PARAMS \
|
||||
0x580904UL
|
||||
#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \
|
||||
(0xfff << 0)
|
||||
#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \
|
||||
0
|
||||
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \
|
||||
(0xff << 16)
|
||||
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \
|
||||
16
|
||||
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \
|
||||
(0xff << 24)
|
||||
#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \
|
||||
24
|
||||
#define CDU_REG_SEGMENT1_PARAMS \
|
||||
0x580908UL
|
||||
#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \
|
||||
(0xfff << 0)
|
||||
#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \
|
||||
0
|
||||
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \
|
||||
(0xff << 16)
|
||||
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \
|
||||
16
|
||||
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \
|
||||
(0xff << 24)
|
||||
#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \
|
||||
24
|
||||
|
||||
#define XSDM_REG_OPERATION_GEN \
|
||||
0xf80408UL
|
||||
#define NIG_REG_RX_BRB_OUT_EN \
|
||||
@ -225,6 +254,8 @@
|
||||
0x1f0000UL
|
||||
#define PRS_REG_MSG_INFO \
|
||||
0x1f0a1cUL
|
||||
#define PRS_REG_ROCE_DEST_QP_MAX_PF \
|
||||
0x1f0430UL
|
||||
#define PSDM_REG_ENABLE_IN1 \
|
||||
0xfa0004UL
|
||||
#define PSEM_REG_ENABLE_IN \
|
||||
@ -233,6 +264,8 @@
|
||||
0x280020UL
|
||||
#define PSWRQ2_REG_CDUT_P_SIZE \
|
||||
0x24000cUL
|
||||
#define PSWRQ2_REG_ILT_MEMORY \
|
||||
0x260000UL
|
||||
#define PSWHST_REG_DISCARD_INTERNAL_WRITES \
|
||||
0x2a0040UL
|
||||
#define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user