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clk: renesas: rcar-gen3: Add RPC clocks

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The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all
the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field
is different between SoCs; it makes sense to support the most common case
of this encoding in the R-Car gen3 CPG driver...

After adding the RPCSRC clock, we can add the RPC[D2] clocks derived from
it and controlled by the RPCCKCR register on all the R-Car gen3 SoCs except
V3M (R8A77970); the composite clock driver seems handy for this task, using
the spinlock added in the previous patch...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Sergei Shtylyov 2019-01-22 22:59:35 +03:00 committed by Geert Uytterhoeven
parent 875e8f6b01
commit db4a0073cc
2 changed files with 105 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

101
drivers/clk/renesas/rcar-gen3-cpg.c
View File

@ -422,6 +422,92 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
return clk;
}
struct rpc_clock {
struct clk_divider div;
struct clk_gate gate;
/*
* One notifier covers both RPC and RPCD2 clocks as they are both
* controlled by the same RPCCKCR register...
*/
struct cpg_simple_notifier csn;
};
static const struct clk_div_table cpg_rpcsrc_div_table[] = {
{ 2, 5 }, { 3, 6 }, { 0, 0 },
};
static const struct clk_div_table cpg_rpc_div_table[] = {
{ 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
};
static struct clk * __init cpg_rpc_clk_register(const char *name,
void __iomem *base, const char *parent_name,
struct raw_notifier_head *notifiers)
{
struct rpc_clock *rpc;
struct clk *clk;
rpc = kzalloc(sizeof(*rpc), GFP_KERNEL);
if (!rpc)
return ERR_PTR(-ENOMEM);
rpc->div.reg = base + CPG_RPCCKCR;
rpc->div.width = 3;
rpc->div.table = cpg_rpc_div_table;
rpc->div.lock = &cpg_lock;
rpc->gate.reg = base + CPG_RPCCKCR;
rpc->gate.bit_idx = 8;
rpc->gate.flags = CLK_GATE_SET_TO_DISABLE;
rpc->gate.lock = &cpg_lock;
rpc->csn.reg = base + CPG_RPCCKCR;
clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
&rpc->div.hw, &clk_divider_ops,
&rpc->gate.hw, &clk_gate_ops, 0);
if (IS_ERR(clk)) {
kfree(rpc);
return clk;
}
cpg_simple_notifier_register(notifiers, &rpc->csn);
return clk;
}
struct rpcd2_clock {
struct clk_fixed_factor fixed;
struct clk_gate gate;
};
static struct clk * __init cpg_rpcd2_clk_register(const char *name,
void __iomem *base,
const char *parent_name)
{
struct rpcd2_clock *rpcd2;
struct clk *clk;
rpcd2 = kzalloc(sizeof(*rpcd2), GFP_KERNEL);
if (!rpcd2)
return ERR_PTR(-ENOMEM);
rpcd2->fixed.mult = 1;
rpcd2->fixed.div = 2;
rpcd2->gate.reg = base + CPG_RPCCKCR;
rpcd2->gate.bit_idx = 9;
rpcd2->gate.flags = CLK_GATE_SET_TO_DISABLE;
rpcd2->gate.lock = &cpg_lock;
clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
&rpcd2->fixed.hw, &clk_fixed_factor_ops,
&rpcd2->gate.hw, &clk_gate_ops, 0);
if (IS_ERR(clk))
kfree(rpcd2);
return clk;
}
static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
static unsigned int cpg_clk_extalr __initdata;
@ -600,6 +686,21 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
}
break;
case CLK_TYPE_GEN3_RPCSRC:
return clk_register_divider_table(NULL, core->name,
__clk_get_name(parent), 0,
base + CPG_RPCCKCR, 3, 2, 0,
cpg_rpcsrc_div_table,
&cpg_lock);
case CLK_TYPE_GEN3_RPC:
return cpg_rpc_clk_register(core->name, base,
__clk_get_name(parent), notifiers);
case CLK_TYPE_GEN3_RPCD2:
return cpg_rpcd2_clk_register(core->name, base,
__clk_get_name(parent));
default:
return ERR_PTR(-EINVAL);
}

4
drivers/clk/renesas/rcar-gen3-cpg.h
View File

@ -23,6 +23,9 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_Z2,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
CLK_TYPE_GEN3_RPCSRC,
CLK_TYPE_GEN3_RPC,
CLK_TYPE_GEN3_RPCD2,
/* SoC specific definitions start here */
CLK_TYPE_GEN3_SOC_BASE,
@ -57,6 +60,7 @@ struct rcar_gen3_cpg_pll_config {
u8 osc_prediv;
};
#define CPG_RPCCKCR 0x238
#define CPG_RCKCR 0x240
struct clk *rcar_gen3_cpg_clk_register(struct device *dev,