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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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sh: Revert TLB miss fast-path changes that broke PTEA parts.
This ended up causing problems for older parts (particularly ones using PTEA). Revert this for now, it can be added back in once it's had some more testing. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
401e9093a3
commit
db2e1fa3f0
@ -13,10 +13,8 @@
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <asm/unistd.h>
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#include <asm/cpu/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/unistd.h>
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! NOTE:
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! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address
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@ -138,14 +136,29 @@ ENTRY(tlb_protection_violation_store)
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call_dpf:
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mov.l 1f, r0
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mov.l @r0, r6 ! address
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mov r5, r8
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mov.l @r0, r6
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mov r6, r9
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mov.l 2f, r0
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sts pr, r10
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jsr @r0
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mov r15, r4
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!
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tst r0, r0
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bf/s 0f
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lds r10, pr
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rts
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nop
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0: sti
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mov.l 3f, r0
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mov r9, r6
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mov r8, r5
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jmp @r0
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mov r15, r4 ! regs
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mov r15, r4
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.align 2
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1: .long MMU_TEA
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2: .long __do_page_fault
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3: .long do_page_fault
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.align 2
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@ -332,171 +345,9 @@ general_exception:
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!
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!
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/* gas doesn't flag impossible values for mov #immediate as an error */
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#if (_PAGE_PRESENT >> 2) > 0x7f
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#error cannot load PAGE_PRESENT as an immediate
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#endif
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#if _PAGE_DIRTY > 0x7f
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#error cannot load PAGE_DIRTY as an immediate
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#endif
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#if (_PAGE_PRESENT << 2) != _PAGE_ACCESSED
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#error cannot derive PAGE_ACCESSED from PAGE_PRESENT
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#endif
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#if defined(CONFIG_CPU_SH4)
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#define ldmmupteh(r) mov.l 8f, r
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#else
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#define ldmmupteh(r) mov #MMU_PTEH, r
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#endif
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.balign 1024,0,1024
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tlb_miss:
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#ifdef COUNT_EXCEPTIONS
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! Increment the counts
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mov.l 9f, k1
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mov.l @k1, k2
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add #1, k2
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mov.l k2, @k1
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#endif
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! k0 scratch
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! k1 pgd and pte pointers
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! k2 faulting address
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! k3 pgd and pte index masks
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! k4 shift
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! Load up the pgd entry (k1)
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ldmmupteh(k0) ! 9 LS (latency=2) MMU_PTEH
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mov.w 4f, k3 ! 8 LS (latency=2) (PTRS_PER_PGD-1) << 2
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mov #-(PGDIR_SHIFT-2), k4 ! 6 EX
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mov.l @(MMU_TEA-MMU_PTEH,k0), k2 ! 18 LS (latency=2)
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mov.l @(MMU_TTB-MMU_PTEH,k0), k1 ! 18 LS (latency=2)
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mov k2, k0 ! 5 MT (latency=0)
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shld k4, k0 ! 99 EX
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and k3, k0 ! 78 EX
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mov.l @(k0, k1), k1 ! 21 LS (latency=2)
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mov #-(PAGE_SHIFT-2), k4 ! 6 EX
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! Load up the pte entry (k2)
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mov k2, k0 ! 5 MT (latency=0)
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shld k4, k0 ! 99 EX
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tst k1, k1 ! 86 MT
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bt 20f ! 110 BR
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mov.w 3f, k3 ! 8 LS (latency=2) (PTRS_PER_PTE-1) << 2
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and k3, k0 ! 78 EX
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mov.w 5f, k4 ! 8 LS (latency=2) _PAGE_PRESENT
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mov.l @(k0, k1), k2 ! 21 LS (latency=2)
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add k0, k1 ! 49 EX
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#ifdef CONFIG_CPU_HAS_PTEA
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! Test the entry for present and _PAGE_ACCESSED
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mov #-28, k3 ! 6 EX
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mov k2, k0 ! 5 MT (latency=0)
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tst k4, k2 ! 68 MT
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shld k3, k0 ! 99 EX
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bt 20f ! 110 BR
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! Set PTEA register
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! MMU_PTEA = ((pteval >> 28) & 0xe) | (pteval & 0x1)
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!
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! k0=pte>>28, k1=pte*, k2=pte, k3=<unused>, k4=_PAGE_PRESENT
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and #0xe, k0 ! 79 EX
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mov k0, k3 ! 5 MT (latency=0)
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mov k2, k0 ! 5 MT (latency=0)
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and #1, k0 ! 79 EX
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or k0, k3 ! 82 EX
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ldmmupteh(k0) ! 9 LS (latency=2)
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shll2 k4 ! 101 EX _PAGE_ACCESSED
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tst k4, k2 ! 68 MT
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mov.l k3, @(MMU_PTEA-MMU_PTEH,k0) ! 27 LS
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mov.l 7f, k3 ! 9 LS (latency=2) _PAGE_FLAGS_HARDWARE_MASK
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! k0=MMU_PTEH, k1=pte*, k2=pte, k3=_PAGE_FLAGS_HARDWARE, k4=_PAGE_ACCESSED
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#else
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! Test the entry for present and _PAGE_ACCESSED
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mov.l 7f, k3 ! 9 LS (latency=2) _PAGE_FLAGS_HARDWARE_MASK
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tst k4, k2 ! 68 MT
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shll2 k4 ! 101 EX _PAGE_ACCESSED
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ldmmupteh(k0) ! 9 LS (latency=2)
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bt 20f ! 110 BR
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tst k4, k2 ! 68 MT
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! k0=MMU_PTEH, k1=pte*, k2=pte, k3=_PAGE_FLAGS_HARDWARE, k4=_PAGE_ACCESSED
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#endif
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! Set up the entry
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and k2, k3 ! 78 EX
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bt/s 10f ! 108 BR
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mov.l k3, @(MMU_PTEL-MMU_PTEH,k0) ! 27 LS
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ldtlb ! 128 CO
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! At least one instruction between ldtlb and rte
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nop ! 119 NOP
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rte ! 126 CO
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nop ! 119 NOP
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10: or k4, k2 ! 82 EX
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ldtlb ! 128 CO
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! At least one instruction between ldtlb and rte
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mov.l k2, @k1 ! 27 LS
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rte ! 126 CO
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! Note we cannot execute mov here, because it is executed after
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! restoring SSR, so would be executed in user space.
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nop ! 119 NOP
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.align 5
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! Once cache line if possible...
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1: .long swapper_pg_dir
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3: .short (PTRS_PER_PTE-1) << 2
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4: .short (PTRS_PER_PGD-1) << 2
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5: .long _PAGE_PRESENT
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7: .long _PAGE_FLAGS_HARDWARE_MASK
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8: .long MMU_PTEH
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#ifdef COUNT_EXCEPTIONS
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9: .long exception_count_miss
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#endif
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! Either pgd or pte not present
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20: mov.l 1f, k2
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mov.l 1f, k2
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mov.l 4f, k3
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bra handle_exception
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mov.l @k2, k2
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@ -647,15 +498,6 @@ skip_save:
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bf interrupt_exception
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shlr2 r8
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shlr r8
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#ifdef COUNT_EXCEPTIONS
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mov.l 5f, r9
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add r8, r9
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mov.l @r9, r10
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add #1, r10
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mov.l r10, @r9
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#endif
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mov.l 4f, r9
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add r8, r9
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mov.l @r9, r9
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@ -669,9 +511,6 @@ skip_save:
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2: .long 0x000080f0 ! FD=1, IMASK=15
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3: .long 0xcfffffff ! RB=0, BL=0
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4: .long exception_handling_table
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#ifdef COUNT_EXCEPTIONS
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5: .long exception_count_table
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#endif
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interrupt_exception:
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mov.l 1f, r9
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@ -17,6 +17,7 @@
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#include <linux/kprobes.h>
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#include <asm/system.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/kgdb.h>
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extern void die(const char *,struct pt_regs *,long);
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@ -224,3 +225,89 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
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if (!user_mode(regs))
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goto no_context;
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}
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#ifdef CONFIG_SH_STORE_QUEUES
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/*
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* This is a special case for the SH-4 store queues, as pages for this
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* space still need to be faulted in before it's possible to flush the
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* store queue cache for writeout to the remapped region.
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*/
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#define P3_ADDR_MAX (P4SEG_STORE_QUE + 0x04000000)
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#else
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#define P3_ADDR_MAX P4SEG
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#endif
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/*
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* Called with interrupts disabled.
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*/
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asmlinkage int __kprobes __do_page_fault(struct pt_regs *regs,
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unsigned long writeaccess,
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unsigned long address)
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{
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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pte_t entry;
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struct mm_struct *mm = current->mm;
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spinlock_t *ptl;
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int ret = 1;
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#ifdef CONFIG_SH_KGDB
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if (kgdb_nofault && kgdb_bus_err_hook)
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kgdb_bus_err_hook();
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#endif
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/*
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* We don't take page faults for P1, P2, and parts of P4, these
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* are always mapped, whether it be due to legacy behaviour in
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* 29-bit mode, or due to PMB configuration in 32-bit mode.
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*/
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if (address >= P3SEG && address < P3_ADDR_MAX) {
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pgd = pgd_offset_k(address);
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mm = NULL;
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} else {
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if (unlikely(address >= TASK_SIZE || !mm))
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return 1;
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pgd = pgd_offset(mm, address);
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}
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pud = pud_offset(pgd, address);
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if (pud_none_or_clear_bad(pud))
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return 1;
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pmd = pmd_offset(pud, address);
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if (pmd_none_or_clear_bad(pmd))
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return 1;
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if (mm)
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pte = pte_offset_map_lock(mm, pmd, address, &ptl);
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else
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pte = pte_offset_kernel(pmd, address);
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entry = *pte;
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if (unlikely(pte_none(entry) || pte_not_present(entry)))
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goto unlock;
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if (unlikely(writeaccess && !pte_write(entry)))
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goto unlock;
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if (writeaccess)
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entry = pte_mkdirty(entry);
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entry = pte_mkyoung(entry);
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#ifdef CONFIG_CPU_SH4
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/*
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* ITLB is not affected by "ldtlb" instruction.
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* So, we need to flush the entry by ourselves.
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*/
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local_flush_tlb_one(get_asid(), address & PAGE_MASK);
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#endif
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set_pte(pte, entry);
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update_mmu_cache(NULL, address, entry);
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ret = 0;
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unlock:
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if (mm)
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pte_unmap_unlock(pte, ptl);
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return ret;
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}
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@ -43,7 +43,7 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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/* PGD bits */
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#define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
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#define PGDIR_BITS (32 - PGDIR_SHIFT)
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#define PGDIR_SIZE (1 << PGDIR_SHIFT)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/* Entries per level */
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