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drm/amd/display: add line number to reg_wait timeout print
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -129,7 +129,7 @@ uint32_t generic_reg_get(const struct dc_context *ctx,
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uint32_t generic_reg_wait(const struct dc_context *ctx,
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uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value,
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unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
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const char *func_name)
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const char *func_name, int line)
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{
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uint32_t field_value;
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uint32_t reg_val;
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@ -158,8 +158,8 @@ uint32_t generic_reg_wait(const struct dc_context *ctx,
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return reg_val;
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}
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dm_error("REG_WAIT timeout %dus * %d tries - %s\n",
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delay_between_poll_us, time_out_num_tries, func_name);
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dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n",
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delay_between_poll_us, time_out_num_tries, func_name, line);
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if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
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BREAK_TO_DEBUGGER();
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@ -194,7 +194,7 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
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unsigned int generic_reg_wait(const struct dc_context *ctx,
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uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,
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unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
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const char *func_name);
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const char *func_name, int line);
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/* These macros need to be used with soc15 registers in order to retrieve
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@ -188,7 +188,7 @@
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#define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \
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generic_reg_wait(CTX, \
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REG(reg_name), FN(reg_name, field), val,\
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delay_between_poll_us, max_try, __func__)
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delay_between_poll_us, max_try, __func__, __LINE__)
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/* macro to update (read, modify, write) register fields
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*/
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