mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 15:26:48 +07:00
Merge branch 'sfc-code-refactoring'
Alex Maftei says: ==================== sfc: code refactoring Splitting some of the driver code into different files, which will later be used in another driver for a new product. ==================== Reviewed-by: Edward Cree <ecree@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
daea5b4dc1
@ -1,7 +1,10 @@
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||||
# SPDX-License-Identifier: GPL-2.0
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sfc-y += efx.o nic.o farch.o siena.o ef10.o tx.o rx.o \
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sfc-y += efx.o efx_common.o efx_channels.o nic.o \
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farch.o siena.o ef10.o \
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tx.o tx_common.o rx.o rx_common.o \
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selftest.o ethtool.o ptp.o tx_tso.o \
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mcdi.o mcdi_port.o mcdi_mon.o
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mcdi.o mcdi_port.o \
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mcdi_mon.o
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sfc-$(CONFIG_SFC_MTD) += mtd.o
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sfc-$(CONFIG_SFC_SRIOV) += sriov.o siena_sriov.o ef10_sriov.o
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@ -5,14 +5,17 @@
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*/
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#include "net_driver.h"
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#include "rx_common.h"
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#include "ef10_regs.h"
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#include "io.h"
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#include "mcdi.h"
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#include "mcdi_pcol.h"
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#include "mcdi_port_common.h"
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#include "nic.h"
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#include "workarounds.h"
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#include "selftest.h"
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#include "ef10_sriov.h"
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#include "rx_common.h"
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#include <linux/in.h>
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#include <linux/jhash.h>
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#include <linux/wait.h>
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|
File diff suppressed because it is too large
Load Diff
@ -15,31 +15,19 @@ int efx_net_open(struct net_device *net_dev);
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int efx_net_stop(struct net_device *net_dev);
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/* TX */
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int efx_probe_tx_queue(struct efx_tx_queue *tx_queue);
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void efx_remove_tx_queue(struct efx_tx_queue *tx_queue);
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void efx_init_tx_queue(struct efx_tx_queue *tx_queue);
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void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue);
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void efx_fini_tx_queue(struct efx_tx_queue *tx_queue);
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netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
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struct net_device *net_dev);
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netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb);
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void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index);
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int efx_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
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void *type_data);
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unsigned int efx_tx_max_skb_descs(struct efx_nic *efx);
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extern unsigned int efx_piobuf_size;
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extern bool efx_separate_tx_channels;
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/* RX */
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void efx_set_default_rx_indir_table(struct efx_nic *efx,
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struct efx_rss_context *ctx);
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void efx_rx_config_page_split(struct efx_nic *efx);
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int efx_probe_rx_queue(struct efx_rx_queue *rx_queue);
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void efx_remove_rx_queue(struct efx_rx_queue *rx_queue);
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void efx_init_rx_queue(struct efx_rx_queue *rx_queue);
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void efx_fini_rx_queue(struct efx_rx_queue *rx_queue);
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void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue, bool atomic);
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void efx_rx_slow_fill(struct timer_list *t);
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void __efx_rx_packet(struct efx_channel *channel);
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void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index,
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unsigned int n_frags, unsigned int len, u16 flags);
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@ -48,7 +36,9 @@ static inline void efx_rx_flush_packet(struct efx_channel *channel)
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if (channel->rx_pkt_n_frags)
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__efx_rx_packet(channel);
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}
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void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue);
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void efx_init_rx_recycle_ring(struct efx_rx_queue *rx_queue);
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struct page *efx_reuse_page(struct efx_rx_queue *rx_queue);
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#define EFX_MAX_DMAQ_SIZE 4096UL
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#define EFX_DEFAULT_DMAQ_SIZE 1024UL
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@ -80,8 +70,6 @@ static inline bool efx_rss_enabled(struct efx_nic *efx)
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/* Filters */
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void efx_mac_reconfigure(struct efx_nic *efx);
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/**
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* efx_filter_insert_filter - add or replace a filter
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* @efx: NIC in which to insert the filter
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@ -218,26 +206,10 @@ static inline bool efx_rss_active(struct efx_rss_context *ctx)
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return ctx->context_id != EFX_EF10_RSS_CONTEXT_INVALID;
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}
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/* Channels */
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int efx_channel_dummy_op_int(struct efx_channel *channel);
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void efx_channel_dummy_op_void(struct efx_channel *channel);
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int efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries);
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/* Ports */
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int efx_reconfigure_port(struct efx_nic *efx);
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int __efx_reconfigure_port(struct efx_nic *efx);
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/* Ethtool support */
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extern const struct ethtool_ops efx_ethtool_ops;
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/* Reset handling */
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int efx_reset(struct efx_nic *efx, enum reset_type method);
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void efx_reset_down(struct efx_nic *efx, enum reset_type method);
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int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok);
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int efx_try_recovery(struct efx_nic *efx);
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/* Global */
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void efx_schedule_reset(struct efx_nic *efx, enum reset_type type);
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unsigned int efx_usecs_to_ticks(struct efx_nic *efx, unsigned int usecs);
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unsigned int efx_ticks_to_usecs(struct efx_nic *efx, unsigned int ticks);
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int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
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@ -245,8 +217,6 @@ int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
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bool rx_may_override_tx);
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void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
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unsigned int *rx_usecs, bool *rx_adaptive);
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void efx_stop_eventq(struct efx_channel *channel);
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void efx_start_eventq(struct efx_channel *channel);
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/* Dummy PHY ops for PHY drivers */
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int efx_port_dummy_op_int(struct efx_nic *efx);
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@ -293,9 +263,6 @@ static inline void efx_schedule_channel_irq(struct efx_channel *channel)
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efx_schedule_channel(channel);
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}
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void efx_link_status_changed(struct efx_nic *efx);
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void efx_link_set_advertising(struct efx_nic *efx,
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const unsigned long *advertising);
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void efx_link_clear_advertising(struct efx_nic *efx);
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void efx_link_set_wanted_fc(struct efx_nic *efx, u8);
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|
1232
drivers/net/ethernet/sfc/efx_channels.c
Normal file
1232
drivers/net/ethernet/sfc/efx_channels.c
Normal file
File diff suppressed because it is too large
Load Diff
55
drivers/net/ethernet/sfc/efx_channels.h
Normal file
55
drivers/net/ethernet/sfc/efx_channels.h
Normal file
@ -0,0 +1,55 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2018 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#ifndef EFX_CHANNELS_H
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#define EFX_CHANNELS_H
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int efx_probe_interrupts(struct efx_nic *efx);
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void efx_remove_interrupts(struct efx_nic *efx);
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int efx_soft_enable_interrupts(struct efx_nic *efx);
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void efx_soft_disable_interrupts(struct efx_nic *efx);
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int efx_enable_interrupts(struct efx_nic *efx);
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void efx_disable_interrupts(struct efx_nic *efx);
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void efx_set_interrupt_affinity(struct efx_nic *efx);
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void efx_clear_interrupt_affinity(struct efx_nic *efx);
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int efx_probe_eventq(struct efx_channel *channel);
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int efx_init_eventq(struct efx_channel *channel);
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void efx_start_eventq(struct efx_channel *channel);
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void efx_stop_eventq(struct efx_channel *channel);
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void efx_fini_eventq(struct efx_channel *channel);
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void efx_remove_eventq(struct efx_channel *channel);
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struct efx_channel *
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efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel);
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int efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries);
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void efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len);
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void efx_set_channel_names(struct efx_nic *efx);
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int efx_init_channels(struct efx_nic *efx);
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int efx_probe_channels(struct efx_nic *efx);
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int efx_set_channels(struct efx_nic *efx);
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bool efx_default_channel_want_txqs(struct efx_channel *channel);
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void efx_remove_channel(struct efx_channel *channel);
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void efx_remove_channels(struct efx_nic *efx);
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void efx_fini_channels(struct efx_nic *efx);
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struct efx_channel *efx_copy_channel(const struct efx_channel *old_channel);
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void efx_start_channels(struct efx_nic *efx);
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void efx_stop_channels(struct efx_nic *efx);
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void efx_init_napi_channel(struct efx_channel *channel);
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void efx_init_napi(struct efx_nic *efx);
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void efx_fini_napi_channel(struct efx_channel *channel);
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void efx_fini_napi(struct efx_nic *efx);
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int efx_channel_dummy_op_int(struct efx_channel *channel);
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void efx_channel_dummy_op_void(struct efx_channel *channel);
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#endif
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999
drivers/net/ethernet/sfc/efx_common.c
Normal file
999
drivers/net/ethernet/sfc/efx_common.c
Normal file
@ -0,0 +1,999 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2018 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include "net_driver.h"
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include "efx_common.h"
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#include "efx_channels.h"
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#include "efx.h"
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#include "mcdi.h"
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#include "selftest.h"
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#include "rx_common.h"
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#include "tx_common.h"
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#include "nic.h"
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#include "io.h"
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#include "mcdi_pcol.h"
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static unsigned int debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
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NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
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NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
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NETIF_MSG_TX_ERR | NETIF_MSG_HW);
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module_param(debug, uint, 0);
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MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
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/* This is the time (in jiffies) between invocations of the hardware
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* monitor.
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* On Falcon-based NICs, this will:
|
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* - Check the on-board hardware monitor;
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* - Poll the link state and reconfigure the hardware as necessary.
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* On Siena-based NICs for power systems with EEH support, this will give EEH a
|
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* chance to start.
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*/
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static unsigned int efx_monitor_interval = 1 * HZ;
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/* How often and how many times to poll for a reset while waiting for a
|
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* BIST that another function started to complete.
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*/
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#define BIST_WAIT_DELAY_MS 100
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#define BIST_WAIT_DELAY_COUNT 100
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/* Default stats update time */
|
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#define STATS_PERIOD_MS_DEFAULT 1000
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const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
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const char *const efx_reset_type_names[] = {
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[RESET_TYPE_INVISIBLE] = "INVISIBLE",
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[RESET_TYPE_ALL] = "ALL",
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[RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
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[RESET_TYPE_WORLD] = "WORLD",
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[RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
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[RESET_TYPE_DATAPATH] = "DATAPATH",
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[RESET_TYPE_MC_BIST] = "MC_BIST",
|
||||
[RESET_TYPE_DISABLE] = "DISABLE",
|
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[RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
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||||
[RESET_TYPE_INT_ERROR] = "INT_ERROR",
|
||||
[RESET_TYPE_DMA_ERROR] = "DMA_ERROR",
|
||||
[RESET_TYPE_TX_SKIP] = "TX_SKIP",
|
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[RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
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||||
[RESET_TYPE_MCDI_TIMEOUT] = "MCDI_TIMEOUT (FLR)",
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||||
};
|
||||
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#define RESET_TYPE(type) \
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STRING_TABLE_LOOKUP(type, efx_reset_type)
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||||
|
||||
/* Loopback mode names (see LOOPBACK_MODE()) */
|
||||
const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
|
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const char *const efx_loopback_mode_names[] = {
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||||
[LOOPBACK_NONE] = "NONE",
|
||||
[LOOPBACK_DATA] = "DATAPATH",
|
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[LOOPBACK_GMAC] = "GMAC",
|
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[LOOPBACK_XGMII] = "XGMII",
|
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[LOOPBACK_XGXS] = "XGXS",
|
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[LOOPBACK_XAUI] = "XAUI",
|
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[LOOPBACK_GMII] = "GMII",
|
||||
[LOOPBACK_SGMII] = "SGMII",
|
||||
[LOOPBACK_XGBR] = "XGBR",
|
||||
[LOOPBACK_XFI] = "XFI",
|
||||
[LOOPBACK_XAUI_FAR] = "XAUI_FAR",
|
||||
[LOOPBACK_GMII_FAR] = "GMII_FAR",
|
||||
[LOOPBACK_SGMII_FAR] = "SGMII_FAR",
|
||||
[LOOPBACK_XFI_FAR] = "XFI_FAR",
|
||||
[LOOPBACK_GPHY] = "GPHY",
|
||||
[LOOPBACK_PHYXS] = "PHYXS",
|
||||
[LOOPBACK_PCS] = "PCS",
|
||||
[LOOPBACK_PMAPMD] = "PMA/PMD",
|
||||
[LOOPBACK_XPORT] = "XPORT",
|
||||
[LOOPBACK_XGMII_WS] = "XGMII_WS",
|
||||
[LOOPBACK_XAUI_WS] = "XAUI_WS",
|
||||
[LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
|
||||
[LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
|
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[LOOPBACK_GMII_WS] = "GMII_WS",
|
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[LOOPBACK_XFI_WS] = "XFI_WS",
|
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[LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
|
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[LOOPBACK_PHYXS_WS] = "PHYXS_WS",
|
||||
};
|
||||
|
||||
/* Reset workqueue. If any NIC has a hardware failure then a reset will be
|
||||
* queued onto this work queue. This is not a per-nic work queue, because
|
||||
* efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
|
||||
*/
|
||||
static struct workqueue_struct *reset_workqueue;
|
||||
|
||||
int efx_create_reset_workqueue(void)
|
||||
{
|
||||
reset_workqueue = create_singlethread_workqueue("sfc_reset");
|
||||
if (!reset_workqueue) {
|
||||
printk(KERN_ERR "Failed to create reset workqueue\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void efx_queue_reset_work(struct efx_nic *efx)
|
||||
{
|
||||
queue_work(reset_workqueue, &efx->reset_work);
|
||||
}
|
||||
|
||||
void efx_flush_reset_workqueue(struct efx_nic *efx)
|
||||
{
|
||||
cancel_work_sync(&efx->reset_work);
|
||||
}
|
||||
|
||||
void efx_destroy_reset_workqueue(void)
|
||||
{
|
||||
if (reset_workqueue) {
|
||||
destroy_workqueue(reset_workqueue);
|
||||
reset_workqueue = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/* We assume that efx->type->reconfigure_mac will always try to sync RX
|
||||
* filters and therefore needs to read-lock the filter table against freeing
|
||||
*/
|
||||
void efx_mac_reconfigure(struct efx_nic *efx)
|
||||
{
|
||||
down_read(&efx->filter_sem);
|
||||
efx->type->reconfigure_mac(efx);
|
||||
up_read(&efx->filter_sem);
|
||||
}
|
||||
|
||||
/* Asynchronous work item for changing MAC promiscuity and multicast
|
||||
* hash. Avoid a drain/rx_ingress enable by reconfiguring the current
|
||||
* MAC directly.
|
||||
*/
|
||||
static void efx_mac_work(struct work_struct *data)
|
||||
{
|
||||
struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
|
||||
|
||||
mutex_lock(&efx->mac_lock);
|
||||
if (efx->port_enabled)
|
||||
efx_mac_reconfigure(efx);
|
||||
mutex_unlock(&efx->mac_lock);
|
||||
}
|
||||
|
||||
/* This ensures that the kernel is kept informed (via
|
||||
* netif_carrier_on/off) of the link status, and also maintains the
|
||||
* link status's stop on the port's TX queue.
|
||||
*/
|
||||
void efx_link_status_changed(struct efx_nic *efx)
|
||||
{
|
||||
struct efx_link_state *link_state = &efx->link_state;
|
||||
|
||||
/* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
|
||||
* that no events are triggered between unregister_netdev() and the
|
||||
* driver unloading. A more general condition is that NETDEV_CHANGE
|
||||
* can only be generated between NETDEV_UP and NETDEV_DOWN
|
||||
*/
|
||||
if (!netif_running(efx->net_dev))
|
||||
return;
|
||||
|
||||
if (link_state->up != netif_carrier_ok(efx->net_dev)) {
|
||||
efx->n_link_state_changes++;
|
||||
|
||||
if (link_state->up)
|
||||
netif_carrier_on(efx->net_dev);
|
||||
else
|
||||
netif_carrier_off(efx->net_dev);
|
||||
}
|
||||
|
||||
/* Status message for kernel log */
|
||||
if (link_state->up)
|
||||
netif_info(efx, link, efx->net_dev,
|
||||
"link up at %uMbps %s-duplex (MTU %d)\n",
|
||||
link_state->speed, link_state->fd ? "full" : "half",
|
||||
efx->net_dev->mtu);
|
||||
else
|
||||
netif_info(efx, link, efx->net_dev, "link down\n");
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* Hardware monitor
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
/* Run periodically off the general workqueue */
|
||||
static void efx_monitor(struct work_struct *data)
|
||||
{
|
||||
struct efx_nic *efx = container_of(data, struct efx_nic,
|
||||
monitor_work.work);
|
||||
|
||||
netif_vdbg(efx, timer, efx->net_dev,
|
||||
"hardware monitor executing on CPU %d\n",
|
||||
raw_smp_processor_id());
|
||||
BUG_ON(efx->type->monitor == NULL);
|
||||
|
||||
/* If the mac_lock is already held then it is likely a port
|
||||
* reconfiguration is already in place, which will likely do
|
||||
* most of the work of monitor() anyway.
|
||||
*/
|
||||
if (mutex_trylock(&efx->mac_lock)) {
|
||||
if (efx->port_enabled && efx->type->monitor)
|
||||
efx->type->monitor(efx);
|
||||
mutex_unlock(&efx->mac_lock);
|
||||
}
|
||||
|
||||
efx_start_monitor(efx);
|
||||
}
|
||||
|
||||
void efx_start_monitor(struct efx_nic *efx)
|
||||
{
|
||||
if (efx->type->monitor)
|
||||
queue_delayed_work(efx->workqueue, &efx->monitor_work,
|
||||
efx_monitor_interval);
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* Event queue processing
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
/* Channels are shutdown and reinitialised whilst the NIC is running
|
||||
* to propagate configuration changes (mtu, checksum offload), or
|
||||
* to clear hardware error conditions
|
||||
*/
|
||||
static void efx_start_datapath(struct efx_nic *efx)
|
||||
{
|
||||
netdev_features_t old_features = efx->net_dev->features;
|
||||
bool old_rx_scatter = efx->rx_scatter;
|
||||
size_t rx_buf_len;
|
||||
|
||||
/* Calculate the rx buffer allocation parameters required to
|
||||
* support the current MTU, including padding for header
|
||||
* alignment and overruns.
|
||||
*/
|
||||
efx->rx_dma_len = (efx->rx_prefix_size +
|
||||
EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
|
||||
efx->type->rx_buffer_padding);
|
||||
rx_buf_len = (sizeof(struct efx_rx_page_state) + XDP_PACKET_HEADROOM +
|
||||
efx->rx_ip_align + efx->rx_dma_len);
|
||||
if (rx_buf_len <= PAGE_SIZE) {
|
||||
efx->rx_scatter = efx->type->always_rx_scatter;
|
||||
efx->rx_buffer_order = 0;
|
||||
} else if (efx->type->can_rx_scatter) {
|
||||
BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
|
||||
BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
|
||||
2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
|
||||
EFX_RX_BUF_ALIGNMENT) >
|
||||
PAGE_SIZE);
|
||||
efx->rx_scatter = true;
|
||||
efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
|
||||
efx->rx_buffer_order = 0;
|
||||
} else {
|
||||
efx->rx_scatter = false;
|
||||
efx->rx_buffer_order = get_order(rx_buf_len);
|
||||
}
|
||||
|
||||
efx_rx_config_page_split(efx);
|
||||
if (efx->rx_buffer_order)
|
||||
netif_dbg(efx, drv, efx->net_dev,
|
||||
"RX buf len=%u; page order=%u batch=%u\n",
|
||||
efx->rx_dma_len, efx->rx_buffer_order,
|
||||
efx->rx_pages_per_batch);
|
||||
else
|
||||
netif_dbg(efx, drv, efx->net_dev,
|
||||
"RX buf len=%u step=%u bpp=%u; page batch=%u\n",
|
||||
efx->rx_dma_len, efx->rx_page_buf_step,
|
||||
efx->rx_bufs_per_page, efx->rx_pages_per_batch);
|
||||
|
||||
/* Restore previously fixed features in hw_features and remove
|
||||
* features which are fixed now
|
||||
*/
|
||||
efx->net_dev->hw_features |= efx->net_dev->features;
|
||||
efx->net_dev->hw_features &= ~efx->fixed_features;
|
||||
efx->net_dev->features |= efx->fixed_features;
|
||||
if (efx->net_dev->features != old_features)
|
||||
netdev_features_change(efx->net_dev);
|
||||
|
||||
/* RX filters may also have scatter-enabled flags */
|
||||
if (efx->rx_scatter != old_rx_scatter)
|
||||
efx->type->filter_update_rx_scatter(efx);
|
||||
|
||||
/* We must keep at least one descriptor in a TX ring empty.
|
||||
* We could avoid this when the queue size does not exactly
|
||||
* match the hardware ring size, but it's not that important.
|
||||
* Therefore we stop the queue when one more skb might fill
|
||||
* the ring completely. We wake it when half way back to
|
||||
* empty.
|
||||
*/
|
||||
efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
|
||||
efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
|
||||
|
||||
/* Initialise the channels */
|
||||
efx_start_channels(efx);
|
||||
|
||||
efx_ptp_start_datapath(efx);
|
||||
|
||||
if (netif_device_present(efx->net_dev))
|
||||
netif_tx_wake_all_queues(efx->net_dev);
|
||||
}
|
||||
|
||||
static void efx_stop_datapath(struct efx_nic *efx)
|
||||
{
|
||||
EFX_ASSERT_RESET_SERIALISED(efx);
|
||||
BUG_ON(efx->port_enabled);
|
||||
|
||||
efx_ptp_stop_datapath(efx);
|
||||
|
||||
efx_stop_channels(efx);
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* Port handling
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
static void efx_start_port(struct efx_nic *efx)
|
||||
{
|
||||
netif_dbg(efx, ifup, efx->net_dev, "start port\n");
|
||||
BUG_ON(efx->port_enabled);
|
||||
|
||||
mutex_lock(&efx->mac_lock);
|
||||
efx->port_enabled = true;
|
||||
|
||||
/* Ensure MAC ingress/egress is enabled */
|
||||
efx_mac_reconfigure(efx);
|
||||
|
||||
mutex_unlock(&efx->mac_lock);
|
||||
}
|
||||
|
||||
/* Cancel work for MAC reconfiguration, periodic hardware monitoring
|
||||
* and the async self-test, wait for them to finish and prevent them
|
||||
* being scheduled again. This doesn't cover online resets, which
|
||||
* should only be cancelled when removing the device.
|
||||
*/
|
||||
static void efx_stop_port(struct efx_nic *efx)
|
||||
{
|
||||
netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
|
||||
|
||||
EFX_ASSERT_RESET_SERIALISED(efx);
|
||||
|
||||
mutex_lock(&efx->mac_lock);
|
||||
efx->port_enabled = false;
|
||||
mutex_unlock(&efx->mac_lock);
|
||||
|
||||
/* Serialise against efx_set_multicast_list() */
|
||||
netif_addr_lock_bh(efx->net_dev);
|
||||
netif_addr_unlock_bh(efx->net_dev);
|
||||
|
||||
cancel_delayed_work_sync(&efx->monitor_work);
|
||||
efx_selftest_async_cancel(efx);
|
||||
cancel_work_sync(&efx->mac_work);
|
||||
}
|
||||
|
||||
/* If the interface is supposed to be running but is not, start
|
||||
* the hardware and software data path, regular activity for the port
|
||||
* (MAC statistics, link polling, etc.) and schedule the port to be
|
||||
* reconfigured. Interrupts must already be enabled. This function
|
||||
* is safe to call multiple times, so long as the NIC is not disabled.
|
||||
* Requires the RTNL lock.
|
||||
*/
|
||||
void efx_start_all(struct efx_nic *efx)
|
||||
{
|
||||
EFX_ASSERT_RESET_SERIALISED(efx);
|
||||
BUG_ON(efx->state == STATE_DISABLED);
|
||||
|
||||
/* Check that it is appropriate to restart the interface. All
|
||||
* of these flags are safe to read under just the rtnl lock
|
||||
*/
|
||||
if (efx->port_enabled || !netif_running(efx->net_dev) ||
|
||||
efx->reset_pending)
|
||||
return;
|
||||
|
||||
efx_start_port(efx);
|
||||
efx_start_datapath(efx);
|
||||
|
||||
/* Start the hardware monitor if there is one */
|
||||
efx_start_monitor(efx);
|
||||
|
||||
/* Link state detection is normally event-driven; we have
|
||||
* to poll now because we could have missed a change
|
||||
*/
|
||||
mutex_lock(&efx->mac_lock);
|
||||
if (efx->phy_op->poll(efx))
|
||||
efx_link_status_changed(efx);
|
||||
mutex_unlock(&efx->mac_lock);
|
||||
|
||||
efx->type->start_stats(efx);
|
||||
efx->type->pull_stats(efx);
|
||||
spin_lock_bh(&efx->stats_lock);
|
||||
efx->type->update_stats(efx, NULL, NULL);
|
||||
spin_unlock_bh(&efx->stats_lock);
|
||||
}
|
||||
|
||||
/* Quiesce the hardware and software data path, and regular activity
|
||||
* for the port without bringing the link down. Safe to call multiple
|
||||
* times with the NIC in almost any state, but interrupts should be
|
||||
* enabled. Requires the RTNL lock.
|
||||
*/
|
||||
void efx_stop_all(struct efx_nic *efx)
|
||||
{
|
||||
EFX_ASSERT_RESET_SERIALISED(efx);
|
||||
|
||||
/* port_enabled can be read safely under the rtnl lock */
|
||||
if (!efx->port_enabled)
|
||||
return;
|
||||
|
||||
/* update stats before we go down so we can accurately count
|
||||
* rx_nodesc_drops
|
||||
*/
|
||||
efx->type->pull_stats(efx);
|
||||
spin_lock_bh(&efx->stats_lock);
|
||||
efx->type->update_stats(efx, NULL, NULL);
|
||||
spin_unlock_bh(&efx->stats_lock);
|
||||
efx->type->stop_stats(efx);
|
||||
efx_stop_port(efx);
|
||||
|
||||
/* Stop the kernel transmit interface. This is only valid if
|
||||
* the device is stopped or detached; otherwise the watchdog
|
||||
* may fire immediately.
|
||||
*/
|
||||
WARN_ON(netif_running(efx->net_dev) &&
|
||||
netif_device_present(efx->net_dev));
|
||||
netif_tx_disable(efx->net_dev);
|
||||
|
||||
efx_stop_datapath(efx);
|
||||
}
|
||||
|
||||
/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
|
||||
* the MAC appropriately. All other PHY configuration changes are pushed
|
||||
* through phy_op->set_settings(), and pushed asynchronously to the MAC
|
||||
* through efx_monitor().
|
||||
*
|
||||
* Callers must hold the mac_lock
|
||||
*/
|
||||
int __efx_reconfigure_port(struct efx_nic *efx)
|
||||
{
|
||||
enum efx_phy_mode phy_mode;
|
||||
int rc;
|
||||
|
||||
WARN_ON(!mutex_is_locked(&efx->mac_lock));
|
||||
|
||||
/* Disable PHY transmit in mac level loopbacks */
|
||||
phy_mode = efx->phy_mode;
|
||||
if (LOOPBACK_INTERNAL(efx))
|
||||
efx->phy_mode |= PHY_MODE_TX_DISABLED;
|
||||
else
|
||||
efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
|
||||
|
||||
rc = efx->type->reconfigure_port(efx);
|
||||
|
||||
if (rc)
|
||||
efx->phy_mode = phy_mode;
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Reinitialise the MAC to pick up new PHY settings, even if the port is
|
||||
* disabled.
|
||||
*/
|
||||
int efx_reconfigure_port(struct efx_nic *efx)
|
||||
{
|
||||
int rc;
|
||||
|
||||
EFX_ASSERT_RESET_SERIALISED(efx);
|
||||
|
||||
mutex_lock(&efx->mac_lock);
|
||||
rc = __efx_reconfigure_port(efx);
|
||||
mutex_unlock(&efx->mac_lock);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* Device reset and suspend
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
static void efx_wait_for_bist_end(struct efx_nic *efx)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) {
|
||||
if (efx_mcdi_poll_reboot(efx))
|
||||
goto out;
|
||||
msleep(BIST_WAIT_DELAY_MS);
|
||||
}
|
||||
|
||||
netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n");
|
||||
out:
|
||||
/* Either way unset the BIST flag. If we found no reboot we probably
|
||||
* won't recover, but we should try.
|
||||
*/
|
||||
efx->mc_bist_for_other_fn = false;
|
||||
}
|
||||
|
||||
/* Try recovery mechanisms.
|
||||
* For now only EEH is supported.
|
||||
* Returns 0 if the recovery mechanisms are unsuccessful.
|
||||
* Returns a non-zero value otherwise.
|
||||
*/
|
||||
int efx_try_recovery(struct efx_nic *efx)
|
||||
{
|
||||
#ifdef CONFIG_EEH
|
||||
/* A PCI error can occur and not be seen by EEH because nothing
|
||||
* happens on the PCI bus. In this case the driver may fail and
|
||||
* schedule a 'recover or reset', leading to this recovery handler.
|
||||
* Manually call the eeh failure check function.
|
||||
*/
|
||||
struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
|
||||
if (eeh_dev_check_failure(eehdev)) {
|
||||
/* The EEH mechanisms will handle the error and reset the
|
||||
* device if necessary.
|
||||
*/
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Tears down the entire software state and most of the hardware state
|
||||
* before reset.
|
||||
*/
|
||||
void efx_reset_down(struct efx_nic *efx, enum reset_type method)
|
||||
{
|
||||
EFX_ASSERT_RESET_SERIALISED(efx);
|
||||
|
||||
if (method == RESET_TYPE_MCDI_TIMEOUT)
|
||||
efx->type->prepare_flr(efx);
|
||||
|
||||
efx_stop_all(efx);
|
||||
efx_disable_interrupts(efx);
|
||||
|
||||
mutex_lock(&efx->mac_lock);
|
||||
down_write(&efx->filter_sem);
|
||||
mutex_lock(&efx->rss_lock);
|
||||
if (efx->port_initialized && method != RESET_TYPE_INVISIBLE &&
|
||||
method != RESET_TYPE_DATAPATH)
|
||||
efx->phy_op->fini(efx);
|
||||
efx->type->fini(efx);
|
||||
}
|
||||
|
||||
/* This function will always ensure that the locks acquired in
|
||||
* efx_reset_down() are released. A failure return code indicates
|
||||
* that we were unable to reinitialise the hardware, and the
|
||||
* driver should be disabled. If ok is false, then the rx and tx
|
||||
* engines are not restarted, pending a RESET_DISABLE.
|
||||
*/
|
||||
int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
|
||||
{
|
||||
int rc;
|
||||
|
||||
EFX_ASSERT_RESET_SERIALISED(efx);
|
||||
|
||||
if (method == RESET_TYPE_MCDI_TIMEOUT)
|
||||
efx->type->finish_flr(efx);
|
||||
|
||||
/* Ensure that SRAM is initialised even if we're disabling the device */
|
||||
rc = efx->type->init(efx);
|
||||
if (rc) {
|
||||
netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (!ok)
|
||||
goto fail;
|
||||
|
||||
if (efx->port_initialized && method != RESET_TYPE_INVISIBLE &&
|
||||
method != RESET_TYPE_DATAPATH) {
|
||||
rc = efx->phy_op->init(efx);
|
||||
if (rc)
|
||||
goto fail;
|
||||
rc = efx->phy_op->reconfigure(efx);
|
||||
if (rc && rc != -EPERM)
|
||||
netif_err(efx, drv, efx->net_dev,
|
||||
"could not restore PHY settings\n");
|
||||
}
|
||||
|
||||
rc = efx_enable_interrupts(efx);
|
||||
if (rc)
|
||||
goto fail;
|
||||
|
||||
#ifdef CONFIG_SFC_SRIOV
|
||||
rc = efx->type->vswitching_restore(efx);
|
||||
if (rc) /* not fatal; the PF will still work fine */
|
||||
netif_warn(efx, probe, efx->net_dev,
|
||||
"failed to restore vswitching rc=%d;"
|
||||
" VFs may not function\n", rc);
|
||||
#endif
|
||||
|
||||
if (efx->type->rx_restore_rss_contexts)
|
||||
efx->type->rx_restore_rss_contexts(efx);
|
||||
mutex_unlock(&efx->rss_lock);
|
||||
efx->type->filter_table_restore(efx);
|
||||
up_write(&efx->filter_sem);
|
||||
if (efx->type->sriov_reset)
|
||||
efx->type->sriov_reset(efx);
|
||||
|
||||
mutex_unlock(&efx->mac_lock);
|
||||
|
||||
efx_start_all(efx);
|
||||
|
||||
if (efx->type->udp_tnl_push_ports)
|
||||
efx->type->udp_tnl_push_ports(efx);
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
efx->port_initialized = false;
|
||||
|
||||
mutex_unlock(&efx->rss_lock);
|
||||
up_write(&efx->filter_sem);
|
||||
mutex_unlock(&efx->mac_lock);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Reset the NIC using the specified method. Note that the reset may
|
||||
* fail, in which case the card will be left in an unusable state.
|
||||
*
|
||||
* Caller must hold the rtnl_lock.
|
||||
*/
|
||||
int efx_reset(struct efx_nic *efx, enum reset_type method)
|
||||
{
|
||||
bool disabled;
|
||||
int rc, rc2;
|
||||
|
||||
netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
|
||||
RESET_TYPE(method));
|
||||
|
||||
efx_device_detach_sync(efx);
|
||||
efx_reset_down(efx, method);
|
||||
|
||||
rc = efx->type->reset(efx, method);
|
||||
if (rc) {
|
||||
netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Clear flags for the scopes we covered. We assume the NIC and
|
||||
* driver are now quiescent so that there is no race here.
|
||||
*/
|
||||
if (method < RESET_TYPE_MAX_METHOD)
|
||||
efx->reset_pending &= -(1 << (method + 1));
|
||||
else /* it doesn't fit into the well-ordered scope hierarchy */
|
||||
__clear_bit(method, &efx->reset_pending);
|
||||
|
||||
/* Reinitialise bus-mastering, which may have been turned off before
|
||||
* the reset was scheduled. This is still appropriate, even in the
|
||||
* RESET_TYPE_DISABLE since this driver generally assumes the hardware
|
||||
* can respond to requests.
|
||||
*/
|
||||
pci_set_master(efx->pci_dev);
|
||||
|
||||
out:
|
||||
/* Leave device stopped if necessary */
|
||||
disabled = rc ||
|
||||
method == RESET_TYPE_DISABLE ||
|
||||
method == RESET_TYPE_RECOVER_OR_DISABLE;
|
||||
rc2 = efx_reset_up(efx, method, !disabled);
|
||||
if (rc2) {
|
||||
disabled = true;
|
||||
if (!rc)
|
||||
rc = rc2;
|
||||
}
|
||||
|
||||
if (disabled) {
|
||||
dev_close(efx->net_dev);
|
||||
netif_err(efx, drv, efx->net_dev, "has been disabled\n");
|
||||
efx->state = STATE_DISABLED;
|
||||
} else {
|
||||
netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
|
||||
efx_device_attach_if_not_resetting(efx);
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* The worker thread exists so that code that cannot sleep can
|
||||
* schedule a reset for later.
|
||||
*/
|
||||
static void efx_reset_work(struct work_struct *data)
|
||||
{
|
||||
struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
|
||||
unsigned long pending;
|
||||
enum reset_type method;
|
||||
|
||||
pending = READ_ONCE(efx->reset_pending);
|
||||
method = fls(pending) - 1;
|
||||
|
||||
if (method == RESET_TYPE_MC_BIST)
|
||||
efx_wait_for_bist_end(efx);
|
||||
|
||||
if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
|
||||
method == RESET_TYPE_RECOVER_OR_ALL) &&
|
||||
efx_try_recovery(efx))
|
||||
return;
|
||||
|
||||
if (!pending)
|
||||
return;
|
||||
|
||||
rtnl_lock();
|
||||
|
||||
/* We checked the state in efx_schedule_reset() but it may
|
||||
* have changed by now. Now that we have the RTNL lock,
|
||||
* it cannot change again.
|
||||
*/
|
||||
if (efx->state == STATE_READY)
|
||||
(void)efx_reset(efx, method);
|
||||
|
||||
rtnl_unlock();
|
||||
}
|
||||
|
||||
void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
|
||||
{
|
||||
enum reset_type method;
|
||||
|
||||
if (efx->state == STATE_RECOVERY) {
|
||||
netif_dbg(efx, drv, efx->net_dev,
|
||||
"recovering: skip scheduling %s reset\n",
|
||||
RESET_TYPE(type));
|
||||
return;
|
||||
}
|
||||
|
||||
switch (type) {
|
||||
case RESET_TYPE_INVISIBLE:
|
||||
case RESET_TYPE_ALL:
|
||||
case RESET_TYPE_RECOVER_OR_ALL:
|
||||
case RESET_TYPE_WORLD:
|
||||
case RESET_TYPE_DISABLE:
|
||||
case RESET_TYPE_RECOVER_OR_DISABLE:
|
||||
case RESET_TYPE_DATAPATH:
|
||||
case RESET_TYPE_MC_BIST:
|
||||
case RESET_TYPE_MCDI_TIMEOUT:
|
||||
method = type;
|
||||
netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
|
||||
RESET_TYPE(method));
|
||||
break;
|
||||
default:
|
||||
method = efx->type->map_reset_reason(type);
|
||||
netif_dbg(efx, drv, efx->net_dev,
|
||||
"scheduling %s reset for %s\n",
|
||||
RESET_TYPE(method), RESET_TYPE(type));
|
||||
break;
|
||||
}
|
||||
|
||||
set_bit(method, &efx->reset_pending);
|
||||
smp_mb(); /* ensure we change reset_pending before checking state */
|
||||
|
||||
/* If we're not READY then just leave the flags set as the cue
|
||||
* to abort probing or reschedule the reset later.
|
||||
*/
|
||||
if (READ_ONCE(efx->state) != STATE_READY)
|
||||
return;
|
||||
|
||||
/* efx_process_channel() will no longer read events once a
|
||||
* reset is scheduled. So switch back to poll'd MCDI completions.
|
||||
*/
|
||||
efx_mcdi_mode_poll(efx);
|
||||
|
||||
efx_queue_reset_work(efx);
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* Dummy PHY/MAC operations
|
||||
*
|
||||
* Can be used for some unimplemented operations
|
||||
* Needed so all function pointers are valid and do not have to be tested
|
||||
* before use
|
||||
*
|
||||
**************************************************************************/
|
||||
int efx_port_dummy_op_int(struct efx_nic *efx)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
void efx_port_dummy_op_void(struct efx_nic *efx) {}
|
||||
|
||||
static bool efx_port_dummy_op_poll(struct efx_nic *efx)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static const struct efx_phy_operations efx_dummy_phy_operations = {
|
||||
.init = efx_port_dummy_op_int,
|
||||
.reconfigure = efx_port_dummy_op_int,
|
||||
.poll = efx_port_dummy_op_poll,
|
||||
.fini = efx_port_dummy_op_void,
|
||||
};
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* Data housekeeping
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
/* This zeroes out and then fills in the invariants in a struct
|
||||
* efx_nic (including all sub-structures).
|
||||
*/
|
||||
int efx_init_struct(struct efx_nic *efx,
|
||||
struct pci_dev *pci_dev, struct net_device *net_dev)
|
||||
{
|
||||
int rc = -ENOMEM;
|
||||
|
||||
/* Initialise common structures */
|
||||
INIT_LIST_HEAD(&efx->node);
|
||||
INIT_LIST_HEAD(&efx->secondary_list);
|
||||
spin_lock_init(&efx->biu_lock);
|
||||
#ifdef CONFIG_SFC_MTD
|
||||
INIT_LIST_HEAD(&efx->mtd_list);
|
||||
#endif
|
||||
INIT_WORK(&efx->reset_work, efx_reset_work);
|
||||
INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
|
||||
INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
|
||||
efx->pci_dev = pci_dev;
|
||||
efx->msg_enable = debug;
|
||||
efx->state = STATE_UNINIT;
|
||||
strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
|
||||
|
||||
efx->net_dev = net_dev;
|
||||
efx->rx_prefix_size = efx->type->rx_prefix_size;
|
||||
efx->rx_ip_align =
|
||||
NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0;
|
||||
efx->rx_packet_hash_offset =
|
||||
efx->type->rx_hash_offset - efx->type->rx_prefix_size;
|
||||
efx->rx_packet_ts_offset =
|
||||
efx->type->rx_ts_offset - efx->type->rx_prefix_size;
|
||||
INIT_LIST_HEAD(&efx->rss_context.list);
|
||||
mutex_init(&efx->rss_lock);
|
||||
spin_lock_init(&efx->stats_lock);
|
||||
efx->vi_stride = EFX_DEFAULT_VI_STRIDE;
|
||||
efx->num_mac_stats = MC_CMD_MAC_NSTATS;
|
||||
BUILD_BUG_ON(MC_CMD_MAC_NSTATS - 1 != MC_CMD_MAC_GENERATION_END);
|
||||
mutex_init(&efx->mac_lock);
|
||||
#ifdef CONFIG_RFS_ACCEL
|
||||
mutex_init(&efx->rps_mutex);
|
||||
spin_lock_init(&efx->rps_hash_lock);
|
||||
/* Failure to allocate is not fatal, but may degrade ARFS performance */
|
||||
efx->rps_hash_table = kcalloc(EFX_ARFS_HASH_TABLE_SIZE,
|
||||
sizeof(*efx->rps_hash_table), GFP_KERNEL);
|
||||
#endif
|
||||
efx->phy_op = &efx_dummy_phy_operations;
|
||||
efx->mdio.dev = net_dev;
|
||||
INIT_WORK(&efx->mac_work, efx_mac_work);
|
||||
init_waitqueue_head(&efx->flush_wq);
|
||||
|
||||
rc = efx_init_channels(efx);
|
||||
if (rc)
|
||||
goto fail;
|
||||
|
||||
/* Would be good to use the net_dev name, but we're too early */
|
||||
snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
|
||||
pci_name(pci_dev));
|
||||
efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
|
||||
if (!efx->workqueue) {
|
||||
rc = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
efx_fini_struct(efx);
|
||||
return rc;
|
||||
}
|
||||
|
||||
void efx_fini_struct(struct efx_nic *efx)
|
||||
{
|
||||
#ifdef CONFIG_RFS_ACCEL
|
||||
kfree(efx->rps_hash_table);
|
||||
#endif
|
||||
|
||||
efx_fini_channels(efx);
|
||||
|
||||
kfree(efx->vpd_sn);
|
||||
|
||||
if (efx->workqueue) {
|
||||
destroy_workqueue(efx->workqueue);
|
||||
efx->workqueue = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/* This configures the PCI device to enable I/O and DMA. */
|
||||
int efx_init_io(struct efx_nic *efx, int bar, dma_addr_t dma_mask,
|
||||
unsigned int mem_map_size)
|
||||
{
|
||||
struct pci_dev *pci_dev = efx->pci_dev;
|
||||
int rc;
|
||||
|
||||
netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
|
||||
|
||||
rc = pci_enable_device(pci_dev);
|
||||
if (rc) {
|
||||
netif_err(efx, probe, efx->net_dev,
|
||||
"failed to enable PCI device\n");
|
||||
goto fail1;
|
||||
}
|
||||
|
||||
pci_set_master(pci_dev);
|
||||
|
||||
/* Set the PCI DMA mask. Try all possibilities from our
|
||||
* genuine mask down to 32 bits, because some architectures
|
||||
* (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
|
||||
* masks event though they reject 46 bit masks.
|
||||
*/
|
||||
while (dma_mask > 0x7fffffffUL) {
|
||||
rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask);
|
||||
if (rc == 0)
|
||||
break;
|
||||
dma_mask >>= 1;
|
||||
}
|
||||
if (rc) {
|
||||
netif_err(efx, probe, efx->net_dev,
|
||||
"could not find a suitable DMA mask\n");
|
||||
goto fail2;
|
||||
}
|
||||
netif_dbg(efx, probe, efx->net_dev,
|
||||
"using DMA mask %llx\n", (unsigned long long)dma_mask);
|
||||
|
||||
efx->membase_phys = pci_resource_start(efx->pci_dev, bar);
|
||||
if (!efx->membase_phys) {
|
||||
netif_err(efx, probe, efx->net_dev,
|
||||
"ERROR: No BAR%d mapping from the BIOS. "
|
||||
"Try pci=realloc on the kernel command line\n", bar);
|
||||
rc = -ENODEV;
|
||||
goto fail3;
|
||||
}
|
||||
|
||||
rc = pci_request_region(pci_dev, bar, "sfc");
|
||||
if (rc) {
|
||||
netif_err(efx, probe, efx->net_dev,
|
||||
"request for memory BAR failed\n");
|
||||
rc = -EIO;
|
||||
goto fail3;
|
||||
}
|
||||
|
||||
efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size);
|
||||
if (!efx->membase) {
|
||||
netif_err(efx, probe, efx->net_dev,
|
||||
"could not map memory BAR at %llx+%x\n",
|
||||
(unsigned long long)efx->membase_phys, mem_map_size);
|
||||
rc = -ENOMEM;
|
||||
goto fail4;
|
||||
}
|
||||
netif_dbg(efx, probe, efx->net_dev,
|
||||
"memory BAR at %llx+%x (virtual %p)\n",
|
||||
(unsigned long long)efx->membase_phys, mem_map_size,
|
||||
efx->membase);
|
||||
|
||||
return 0;
|
||||
|
||||
fail4:
|
||||
pci_release_region(efx->pci_dev, bar);
|
||||
fail3:
|
||||
efx->membase_phys = 0;
|
||||
fail2:
|
||||
pci_disable_device(efx->pci_dev);
|
||||
fail1:
|
||||
return rc;
|
||||
}
|
||||
|
||||
void efx_fini_io(struct efx_nic *efx, int bar)
|
||||
{
|
||||
netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
|
||||
|
||||
if (efx->membase) {
|
||||
iounmap(efx->membase);
|
||||
efx->membase = NULL;
|
||||
}
|
||||
|
||||
if (efx->membase_phys) {
|
||||
pci_release_region(efx->pci_dev, bar);
|
||||
efx->membase_phys = 0;
|
||||
}
|
||||
|
||||
/* Don't disable bus-mastering if VFs are assigned */
|
||||
if (!pci_vfs_assigned(efx->pci_dev))
|
||||
pci_disable_device(efx->pci_dev);
|
||||
}
|
61
drivers/net/ethernet/sfc/efx_common.h
Normal file
61
drivers/net/ethernet/sfc/efx_common.h
Normal file
@ -0,0 +1,61 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/****************************************************************************
|
||||
* Driver for Solarflare network controllers and boards
|
||||
* Copyright 2018 Solarflare Communications Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation, incorporated herein by reference.
|
||||
*/
|
||||
|
||||
#ifndef EFX_COMMON_H
|
||||
#define EFX_COMMON_H
|
||||
|
||||
int efx_init_io(struct efx_nic *efx, int bar, dma_addr_t dma_mask,
|
||||
unsigned int mem_map_size);
|
||||
void efx_fini_io(struct efx_nic *efx, int bar);
|
||||
int efx_init_struct(struct efx_nic *efx, struct pci_dev *pci_dev,
|
||||
struct net_device *net_dev);
|
||||
void efx_fini_struct(struct efx_nic *efx);
|
||||
|
||||
void efx_start_all(struct efx_nic *efx);
|
||||
void efx_stop_all(struct efx_nic *efx);
|
||||
|
||||
int efx_create_reset_workqueue(void);
|
||||
void efx_queue_reset_work(struct efx_nic *efx);
|
||||
void efx_flush_reset_workqueue(struct efx_nic *efx);
|
||||
void efx_destroy_reset_workqueue(void);
|
||||
|
||||
void efx_start_monitor(struct efx_nic *efx);
|
||||
|
||||
int __efx_reconfigure_port(struct efx_nic *efx);
|
||||
int efx_reconfigure_port(struct efx_nic *efx);
|
||||
|
||||
#define EFX_ASSERT_RESET_SERIALISED(efx) \
|
||||
do { \
|
||||
if ((efx->state == STATE_READY) || \
|
||||
(efx->state == STATE_RECOVERY) || \
|
||||
(efx->state == STATE_DISABLED)) \
|
||||
ASSERT_RTNL(); \
|
||||
} while (0)
|
||||
|
||||
int efx_try_recovery(struct efx_nic *efx);
|
||||
void efx_reset_down(struct efx_nic *efx, enum reset_type method);
|
||||
int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok);
|
||||
int efx_reset(struct efx_nic *efx, enum reset_type method);
|
||||
void efx_schedule_reset(struct efx_nic *efx, enum reset_type type);
|
||||
|
||||
static inline int efx_check_disabled(struct efx_nic *efx)
|
||||
{
|
||||
if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) {
|
||||
netif_err(efx, drv, efx->net_dev,
|
||||
"device is disabled due to earlier errors\n");
|
||||
return -EIO;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void efx_mac_reconfigure(struct efx_nic *efx);
|
||||
void efx_link_status_changed(struct efx_nic *efx);
|
||||
|
||||
#endif
|
@ -13,6 +13,9 @@
|
||||
#include "workarounds.h"
|
||||
#include "selftest.h"
|
||||
#include "efx.h"
|
||||
#include "efx_channels.h"
|
||||
#include "rx_common.h"
|
||||
#include "tx_common.h"
|
||||
#include "filter.h"
|
||||
#include "nic.h"
|
||||
|
||||
|
@ -15,6 +15,7 @@
|
||||
#include "net_driver.h"
|
||||
#include "bitfield.h"
|
||||
#include "efx.h"
|
||||
#include "rx_common.h"
|
||||
#include "nic.h"
|
||||
#include "farch_regs.h"
|
||||
#include "sriov.h"
|
||||
|
@ -346,7 +346,6 @@ int efx_mcdi_flush_rxqs(struct efx_nic *efx);
|
||||
int efx_mcdi_port_probe(struct efx_nic *efx);
|
||||
void efx_mcdi_port_remove(struct efx_nic *efx);
|
||||
int efx_mcdi_port_reconfigure(struct efx_nic *efx);
|
||||
int efx_mcdi_port_get_number(struct efx_nic *efx);
|
||||
u32 efx_mcdi_phy_get_caps(struct efx_nic *efx);
|
||||
void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev);
|
||||
int efx_mcdi_set_mac(struct efx_nic *efx);
|
||||
|
30
drivers/net/ethernet/sfc/mcdi_functions.h
Normal file
30
drivers/net/ethernet/sfc/mcdi_functions.h
Normal file
@ -0,0 +1,30 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/****************************************************************************
|
||||
* Driver for Solarflare network controllers and boards
|
||||
* Copyright 2018 Solarflare Communications Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation, incorporated herein by reference.
|
||||
*/
|
||||
#ifndef EFX_MCDI_FUNCTIONS_H
|
||||
#define EFX_MCDI_FUNCTIONS_H
|
||||
|
||||
int efx_mcdi_alloc_vis(struct efx_nic *efx, unsigned int min_vis,
|
||||
unsigned int max_vis, unsigned int *vi_base,
|
||||
unsigned int *allocated_vis);
|
||||
int efx_mcdi_free_vis(struct efx_nic *efx);
|
||||
|
||||
int efx_mcdi_ev_probe(struct efx_channel *channel);
|
||||
int efx_mcdi_ev_init(struct efx_channel *channel, bool v1_cut_thru, bool v2);
|
||||
void efx_mcdi_ev_remove(struct efx_channel *channel);
|
||||
void efx_mcdi_ev_fini(struct efx_channel *channel);
|
||||
int efx_mcdi_tx_init(struct efx_tx_queue *tx_queue, bool tso_v2);
|
||||
void efx_mcdi_tx_remove(struct efx_tx_queue *tx_queue);
|
||||
void efx_mcdi_tx_fini(struct efx_tx_queue *tx_queue);
|
||||
int efx_mcdi_rx_probe(struct efx_rx_queue *rx_queue);
|
||||
int efx_mcdi_rx_init(struct efx_rx_queue *rx_queue, bool want_outer_classes);
|
||||
void efx_mcdi_rx_remove(struct efx_rx_queue *rx_queue);
|
||||
void efx_mcdi_rx_fini(struct efx_rx_queue *rx_queue);
|
||||
|
||||
#endif
|
@ -14,23 +14,9 @@
|
||||
#include "mcdi_pcol.h"
|
||||
#include "nic.h"
|
||||
#include "selftest.h"
|
||||
#include "mcdi_port_common.h"
|
||||
|
||||
struct efx_mcdi_phy_data {
|
||||
u32 flags;
|
||||
u32 type;
|
||||
u32 supported_cap;
|
||||
u32 channel;
|
||||
u32 port;
|
||||
u32 stats_mask;
|
||||
u8 name[20];
|
||||
u32 media;
|
||||
u32 mmd_mask;
|
||||
u8 revision[20];
|
||||
u32 forced_cap;
|
||||
};
|
||||
|
||||
static int
|
||||
efx_mcdi_get_phy_cfg(struct efx_nic *efx, struct efx_mcdi_phy_data *cfg)
|
||||
int efx_mcdi_get_phy_cfg(struct efx_nic *efx, struct efx_mcdi_phy_data *cfg)
|
||||
{
|
||||
MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PHY_CFG_OUT_LEN);
|
||||
size_t outlen;
|
||||
@ -70,9 +56,9 @@ efx_mcdi_get_phy_cfg(struct efx_nic *efx, struct efx_mcdi_phy_data *cfg)
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int efx_mcdi_set_link(struct efx_nic *efx, u32 capabilities,
|
||||
u32 flags, u32 loopback_mode,
|
||||
u32 loopback_speed)
|
||||
int efx_mcdi_set_link(struct efx_nic *efx, u32 capabilities,
|
||||
u32 flags, u32 loopback_mode,
|
||||
u32 loopback_speed)
|
||||
{
|
||||
MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_LINK_IN_LEN);
|
||||
int rc;
|
||||
@ -89,7 +75,7 @@ static int efx_mcdi_set_link(struct efx_nic *efx, u32 capabilities,
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int efx_mcdi_loopback_modes(struct efx_nic *efx, u64 *loopback_modes)
|
||||
int efx_mcdi_loopback_modes(struct efx_nic *efx, u64 *loopback_modes)
|
||||
{
|
||||
MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_LOOPBACK_MODES_OUT_LEN);
|
||||
size_t outlen;
|
||||
@ -168,7 +154,7 @@ static int efx_mcdi_mdio_write(struct net_device *net_dev,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mcdi_to_ethtool_linkset(u32 media, u32 cap, unsigned long *linkset)
|
||||
void mcdi_to_ethtool_linkset(u32 media, u32 cap, unsigned long *linkset)
|
||||
{
|
||||
#define SET_BIT(name) __set_bit(ETHTOOL_LINK_MODE_ ## name ## _BIT, \
|
||||
linkset)
|
||||
@ -232,7 +218,7 @@ static void mcdi_to_ethtool_linkset(u32 media, u32 cap, unsigned long *linkset)
|
||||
#undef SET_BIT
|
||||
}
|
||||
|
||||
static u32 ethtool_linkset_to_mcdi_cap(const unsigned long *linkset)
|
||||
u32 ethtool_linkset_to_mcdi_cap(const unsigned long *linkset)
|
||||
{
|
||||
u32 result = 0;
|
||||
|
||||
@ -273,7 +259,7 @@ static u32 ethtool_linkset_to_mcdi_cap(const unsigned long *linkset)
|
||||
return result;
|
||||
}
|
||||
|
||||
static u32 efx_get_mcdi_phy_flags(struct efx_nic *efx)
|
||||
u32 efx_get_mcdi_phy_flags(struct efx_nic *efx)
|
||||
{
|
||||
struct efx_mcdi_phy_data *phy_cfg = efx->phy_data;
|
||||
enum efx_phy_mode mode, supported;
|
||||
@ -301,7 +287,7 @@ static u32 efx_get_mcdi_phy_flags(struct efx_nic *efx)
|
||||
return flags;
|
||||
}
|
||||
|
||||
static u8 mcdi_to_ethtool_media(u32 media)
|
||||
u8 mcdi_to_ethtool_media(u32 media)
|
||||
{
|
||||
switch (media) {
|
||||
case MC_CMD_MEDIA_XAUI:
|
||||
@ -322,7 +308,7 @@ static u8 mcdi_to_ethtool_media(u32 media)
|
||||
}
|
||||
}
|
||||
|
||||
static void efx_mcdi_phy_decode_link(struct efx_nic *efx,
|
||||
void efx_mcdi_phy_decode_link(struct efx_nic *efx,
|
||||
struct efx_link_state *link_state,
|
||||
u32 speed, u32 flags, u32 fcntl)
|
||||
{
|
||||
@ -365,7 +351,7 @@ static void efx_mcdi_phy_decode_link(struct efx_nic *efx,
|
||||
* Both RS and BASER (whether AUTO or not) means use FEC if cable and link
|
||||
* partner support it, preferring RS to BASER.
|
||||
*/
|
||||
static u32 ethtool_fec_caps_to_mcdi(u32 ethtool_cap)
|
||||
u32 ethtool_fec_caps_to_mcdi(u32 ethtool_cap)
|
||||
{
|
||||
u32 ret = 0;
|
||||
|
||||
@ -392,7 +378,7 @@ static u32 ethtool_fec_caps_to_mcdi(u32 ethtool_cap)
|
||||
* maps both of those to AUTO. This should never matter, and it's not clear
|
||||
* what a better mapping would be anyway.
|
||||
*/
|
||||
static u32 mcdi_fec_caps_to_ethtool(u32 caps, bool is_25g)
|
||||
u32 mcdi_fec_caps_to_ethtool(u32 caps, bool is_25g)
|
||||
{
|
||||
bool rs = caps & (1 << MC_CMD_PHY_CAP_RS_FEC_LBN),
|
||||
rs_req = caps & (1 << MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN),
|
||||
@ -530,7 +516,7 @@ int efx_mcdi_port_reconfigure(struct efx_nic *efx)
|
||||
/* Verify that the forced flow control settings (!EFX_FC_AUTO) are
|
||||
* supported by the link partner. Warn the user if this isn't the case
|
||||
*/
|
||||
static void efx_mcdi_phy_check_fcntl(struct efx_nic *efx, u32 lpa)
|
||||
void efx_mcdi_phy_check_fcntl(struct efx_nic *efx, u32 lpa)
|
||||
{
|
||||
struct efx_mcdi_phy_data *phy_cfg = efx->phy_data;
|
||||
u32 rmtadv;
|
||||
@ -555,7 +541,7 @@ static void efx_mcdi_phy_check_fcntl(struct efx_nic *efx, u32 lpa)
|
||||
"warning: link partner doesn't support pause frames");
|
||||
}
|
||||
|
||||
static bool efx_mcdi_phy_poll(struct efx_nic *efx)
|
||||
bool efx_mcdi_phy_poll(struct efx_nic *efx)
|
||||
{
|
||||
struct efx_link_state old_state = efx->link_state;
|
||||
MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_LINK_OUT_LEN);
|
||||
@ -666,8 +652,8 @@ efx_mcdi_phy_set_link_ksettings(struct efx_nic *efx,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int efx_mcdi_phy_get_fecparam(struct efx_nic *efx,
|
||||
struct ethtool_fecparam *fec)
|
||||
int efx_mcdi_phy_get_fecparam(struct efx_nic *efx,
|
||||
struct ethtool_fecparam *fec)
|
||||
{
|
||||
MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_LINK_OUT_V2_LEN);
|
||||
u32 caps, active, speed; /* MCDI format */
|
||||
@ -745,7 +731,7 @@ static int efx_mcdi_phy_set_fecparam(struct efx_nic *efx,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int efx_mcdi_phy_test_alive(struct efx_nic *efx)
|
||||
int efx_mcdi_phy_test_alive(struct efx_nic *efx)
|
||||
{
|
||||
MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PHY_STATE_OUT_LEN);
|
||||
size_t outlen;
|
||||
|
53
drivers/net/ethernet/sfc/mcdi_port_common.h
Normal file
53
drivers/net/ethernet/sfc/mcdi_port_common.h
Normal file
@ -0,0 +1,53 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/****************************************************************************
|
||||
* Driver for Solarflare network controllers and boards
|
||||
* Copyright 2018 Solarflare Communications Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation, incorporated herein by reference.
|
||||
*/
|
||||
#ifndef EFX_MCDI_PORT_COMMON_H
|
||||
#define EFX_MCDI_PORT_COMMON_H
|
||||
|
||||
#include "net_driver.h"
|
||||
#include "mcdi.h"
|
||||
#include "mcdi_pcol.h"
|
||||
|
||||
struct efx_mcdi_phy_data {
|
||||
u32 flags;
|
||||
u32 type;
|
||||
u32 supported_cap;
|
||||
u32 channel;
|
||||
u32 port;
|
||||
u32 stats_mask;
|
||||
u8 name[20];
|
||||
u32 media;
|
||||
u32 mmd_mask;
|
||||
u8 revision[20];
|
||||
u32 forced_cap;
|
||||
};
|
||||
|
||||
int efx_mcdi_get_phy_cfg(struct efx_nic *efx, struct efx_mcdi_phy_data *cfg);
|
||||
void efx_link_set_advertising(struct efx_nic *efx,
|
||||
const unsigned long *advertising);
|
||||
int efx_mcdi_set_link(struct efx_nic *efx, u32 capabilities,
|
||||
u32 flags, u32 loopback_mode, u32 loopback_speed);
|
||||
int efx_mcdi_loopback_modes(struct efx_nic *efx, u64 *loopback_modes);
|
||||
void mcdi_to_ethtool_linkset(u32 media, u32 cap, unsigned long *linkset);
|
||||
u32 ethtool_linkset_to_mcdi_cap(const unsigned long *linkset);
|
||||
u32 efx_get_mcdi_phy_flags(struct efx_nic *efx);
|
||||
u8 mcdi_to_ethtool_media(u32 media);
|
||||
void efx_mcdi_phy_decode_link(struct efx_nic *efx,
|
||||
struct efx_link_state *link_state,
|
||||
u32 speed, u32 flags, u32 fcntl);
|
||||
u32 ethtool_fec_caps_to_mcdi(u32 ethtool_cap);
|
||||
u32 mcdi_fec_caps_to_ethtool(u32 caps, bool is_25g);
|
||||
void efx_mcdi_phy_check_fcntl(struct efx_nic *efx, u32 lpa);
|
||||
bool efx_mcdi_phy_poll(struct efx_nic *efx);
|
||||
int efx_mcdi_phy_get_fecparam(struct efx_nic *efx,
|
||||
struct ethtool_fecparam *fec);
|
||||
int efx_mcdi_phy_test_alive(struct efx_nic *efx);
|
||||
int efx_mcdi_port_get_number(struct efx_nic *efx);
|
||||
|
||||
#endif
|
@ -138,6 +138,8 @@ struct efx_special_buffer {
|
||||
* freed when descriptor completes
|
||||
* @xdpf: When @flags & %EFX_TX_BUF_XDP, the XDP frame information; its @data
|
||||
* member is the associated buffer to drop a page reference on.
|
||||
* @option: When @flags & %EFX_TX_BUF_OPTION, an EF10-specific option
|
||||
* descriptor.
|
||||
* @dma_addr: DMA address of the fragment.
|
||||
* @flags: Flags for allocation and DMA mapping type
|
||||
* @len: Length of this fragment.
|
||||
@ -152,7 +154,7 @@ struct efx_tx_buffer {
|
||||
struct xdp_frame *xdpf;
|
||||
};
|
||||
union {
|
||||
efx_qword_t option;
|
||||
efx_qword_t option; /* EF10 */
|
||||
dma_addr_t dma_addr;
|
||||
};
|
||||
unsigned short flags;
|
||||
@ -1610,6 +1612,15 @@ static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
|
||||
return &rx_queue->buffer[index];
|
||||
}
|
||||
|
||||
static inline struct efx_rx_buffer *
|
||||
efx_rx_buf_next(struct efx_rx_queue *rx_queue, struct efx_rx_buffer *rx_buf)
|
||||
{
|
||||
if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))
|
||||
return efx_rx_buffer(rx_queue, 0);
|
||||
else
|
||||
return rx_buf + 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* EFX_MAX_FRAME_LEN - calculate maximum frame length
|
||||
*
|
||||
|
@ -11,6 +11,7 @@
|
||||
#include <linux/net_tstamp.h>
|
||||
#include "net_driver.h"
|
||||
#include "efx.h"
|
||||
#include "efx_common.h"
|
||||
#include "mcdi.h"
|
||||
|
||||
enum {
|
||||
@ -505,6 +506,9 @@ static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
|
||||
tx_queue->efx->type->tx_write(tx_queue);
|
||||
}
|
||||
|
||||
int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
|
||||
bool *data_mapped);
|
||||
|
||||
/* RX data path */
|
||||
static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
|
||||
{
|
||||
@ -553,6 +557,7 @@ static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
|
||||
{
|
||||
channel->efx->type->ev_read_ack(channel);
|
||||
}
|
||||
|
||||
void efx_nic_event_test_start(struct efx_channel *channel);
|
||||
|
||||
/* Falcon/Siena queue operations */
|
||||
@ -670,6 +675,7 @@ struct efx_farch_register_test {
|
||||
unsigned address;
|
||||
efx_oword_t mask;
|
||||
};
|
||||
|
||||
int efx_farch_test_registers(struct efx_nic *efx,
|
||||
const struct efx_farch_register_test *regs,
|
||||
size_t n_regs);
|
||||
|
@ -21,6 +21,7 @@
|
||||
#include <linux/bpf_trace.h>
|
||||
#include "net_driver.h"
|
||||
#include "efx.h"
|
||||
#include "rx_common.h"
|
||||
#include "filter.h"
|
||||
#include "nic.h"
|
||||
#include "selftest.h"
|
||||
@ -42,23 +43,10 @@
|
||||
/* Size of buffer allocated for skb header area. */
|
||||
#define EFX_SKB_HEADERS 128u
|
||||
|
||||
/* This is the percentage fill level below which new RX descriptors
|
||||
* will be added to the RX descriptor ring.
|
||||
*/
|
||||
static unsigned int rx_refill_threshold;
|
||||
|
||||
/* Each packet can consume up to ceil(max_frame_len / buffer_size) buffers */
|
||||
#define EFX_RX_MAX_FRAGS DIV_ROUND_UP(EFX_MAX_FRAME_LEN(EFX_MAX_MTU), \
|
||||
EFX_RX_USR_BUF_SIZE)
|
||||
|
||||
/*
|
||||
* RX maximum head room required.
|
||||
*
|
||||
* This must be at least 1 to prevent overflow, plus one packet-worth
|
||||
* to allow pipelined receives.
|
||||
*/
|
||||
#define EFX_RXD_HEAD_ROOM (1 + EFX_RX_MAX_FRAGS)
|
||||
|
||||
static inline u8 *efx_rx_buf_va(struct efx_rx_buffer *buf)
|
||||
{
|
||||
return page_address(buf->page) + buf->page_offset;
|
||||
@ -77,15 +65,6 @@ static inline u32 efx_rx_buf_hash(struct efx_nic *efx, const u8 *eh)
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline struct efx_rx_buffer *
|
||||
efx_rx_buf_next(struct efx_rx_queue *rx_queue, struct efx_rx_buffer *rx_buf)
|
||||
{
|
||||
if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))
|
||||
return efx_rx_buffer(rx_queue, 0);
|
||||
else
|
||||
return rx_buf + 1;
|
||||
}
|
||||
|
||||
static inline void efx_sync_rx_buffer(struct efx_nic *efx,
|
||||
struct efx_rx_buffer *rx_buf,
|
||||
unsigned int len)
|
||||
@ -94,22 +73,8 @@ static inline void efx_sync_rx_buffer(struct efx_nic *efx,
|
||||
DMA_FROM_DEVICE);
|
||||
}
|
||||
|
||||
void efx_rx_config_page_split(struct efx_nic *efx)
|
||||
{
|
||||
efx->rx_page_buf_step = ALIGN(efx->rx_dma_len + efx->rx_ip_align +
|
||||
XDP_PACKET_HEADROOM,
|
||||
EFX_RX_BUF_ALIGNMENT);
|
||||
efx->rx_bufs_per_page = efx->rx_buffer_order ? 1 :
|
||||
((PAGE_SIZE - sizeof(struct efx_rx_page_state)) /
|
||||
efx->rx_page_buf_step);
|
||||
efx->rx_buffer_truesize = (PAGE_SIZE << efx->rx_buffer_order) /
|
||||
efx->rx_bufs_per_page;
|
||||
efx->rx_pages_per_batch = DIV_ROUND_UP(EFX_RX_PREFERRED_BATCH,
|
||||
efx->rx_bufs_per_page);
|
||||
}
|
||||
|
||||
/* Check the RX page recycle ring for a page that can be reused. */
|
||||
static struct page *efx_reuse_page(struct efx_rx_queue *rx_queue)
|
||||
struct page *efx_reuse_page(struct efx_rx_queue *rx_queue)
|
||||
{
|
||||
struct efx_nic *efx = rx_queue->efx;
|
||||
struct page *page;
|
||||
@ -142,106 +107,6 @@ static struct page *efx_reuse_page(struct efx_rx_queue *rx_queue)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* efx_init_rx_buffers - create EFX_RX_BATCH page-based RX buffers
|
||||
*
|
||||
* @rx_queue: Efx RX queue
|
||||
*
|
||||
* This allocates a batch of pages, maps them for DMA, and populates
|
||||
* struct efx_rx_buffers for each one. Return a negative error code or
|
||||
* 0 on success. If a single page can be used for multiple buffers,
|
||||
* then the page will either be inserted fully, or not at all.
|
||||
*/
|
||||
static int efx_init_rx_buffers(struct efx_rx_queue *rx_queue, bool atomic)
|
||||
{
|
||||
struct efx_nic *efx = rx_queue->efx;
|
||||
struct efx_rx_buffer *rx_buf;
|
||||
struct page *page;
|
||||
unsigned int page_offset;
|
||||
struct efx_rx_page_state *state;
|
||||
dma_addr_t dma_addr;
|
||||
unsigned index, count;
|
||||
|
||||
count = 0;
|
||||
do {
|
||||
page = efx_reuse_page(rx_queue);
|
||||
if (page == NULL) {
|
||||
page = alloc_pages(__GFP_COMP |
|
||||
(atomic ? GFP_ATOMIC : GFP_KERNEL),
|
||||
efx->rx_buffer_order);
|
||||
if (unlikely(page == NULL))
|
||||
return -ENOMEM;
|
||||
dma_addr =
|
||||
dma_map_page(&efx->pci_dev->dev, page, 0,
|
||||
PAGE_SIZE << efx->rx_buffer_order,
|
||||
DMA_FROM_DEVICE);
|
||||
if (unlikely(dma_mapping_error(&efx->pci_dev->dev,
|
||||
dma_addr))) {
|
||||
__free_pages(page, efx->rx_buffer_order);
|
||||
return -EIO;
|
||||
}
|
||||
state = page_address(page);
|
||||
state->dma_addr = dma_addr;
|
||||
} else {
|
||||
state = page_address(page);
|
||||
dma_addr = state->dma_addr;
|
||||
}
|
||||
|
||||
dma_addr += sizeof(struct efx_rx_page_state);
|
||||
page_offset = sizeof(struct efx_rx_page_state);
|
||||
|
||||
do {
|
||||
index = rx_queue->added_count & rx_queue->ptr_mask;
|
||||
rx_buf = efx_rx_buffer(rx_queue, index);
|
||||
rx_buf->dma_addr = dma_addr + efx->rx_ip_align +
|
||||
XDP_PACKET_HEADROOM;
|
||||
rx_buf->page = page;
|
||||
rx_buf->page_offset = page_offset + efx->rx_ip_align +
|
||||
XDP_PACKET_HEADROOM;
|
||||
rx_buf->len = efx->rx_dma_len;
|
||||
rx_buf->flags = 0;
|
||||
++rx_queue->added_count;
|
||||
get_page(page);
|
||||
dma_addr += efx->rx_page_buf_step;
|
||||
page_offset += efx->rx_page_buf_step;
|
||||
} while (page_offset + efx->rx_page_buf_step <= PAGE_SIZE);
|
||||
|
||||
rx_buf->flags = EFX_RX_BUF_LAST_IN_PAGE;
|
||||
} while (++count < efx->rx_pages_per_batch);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Unmap a DMA-mapped page. This function is only called for the final RX
|
||||
* buffer in a page.
|
||||
*/
|
||||
static void efx_unmap_rx_buffer(struct efx_nic *efx,
|
||||
struct efx_rx_buffer *rx_buf)
|
||||
{
|
||||
struct page *page = rx_buf->page;
|
||||
|
||||
if (page) {
|
||||
struct efx_rx_page_state *state = page_address(page);
|
||||
dma_unmap_page(&efx->pci_dev->dev,
|
||||
state->dma_addr,
|
||||
PAGE_SIZE << efx->rx_buffer_order,
|
||||
DMA_FROM_DEVICE);
|
||||
}
|
||||
}
|
||||
|
||||
static void efx_free_rx_buffers(struct efx_rx_queue *rx_queue,
|
||||
struct efx_rx_buffer *rx_buf,
|
||||
unsigned int num_bufs)
|
||||
{
|
||||
do {
|
||||
if (rx_buf->page) {
|
||||
put_page(rx_buf->page);
|
||||
rx_buf->page = NULL;
|
||||
}
|
||||
rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
|
||||
} while (--num_bufs);
|
||||
}
|
||||
|
||||
/* Attempt to recycle the page if there is an RX recycle ring; the page can
|
||||
* only be added if this is the final RX buffer, to prevent pages being used in
|
||||
* the descriptor ring and appearing in the recycle ring simultaneously.
|
||||
@ -278,21 +143,6 @@ static void efx_recycle_rx_page(struct efx_channel *channel,
|
||||
put_page(rx_buf->page);
|
||||
}
|
||||
|
||||
static void efx_fini_rx_buffer(struct efx_rx_queue *rx_queue,
|
||||
struct efx_rx_buffer *rx_buf)
|
||||
{
|
||||
/* Release the page reference we hold for the buffer. */
|
||||
if (rx_buf->page)
|
||||
put_page(rx_buf->page);
|
||||
|
||||
/* If this is the last buffer in a page, unmap and free it. */
|
||||
if (rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE) {
|
||||
efx_unmap_rx_buffer(rx_queue->efx, rx_buf);
|
||||
efx_free_rx_buffers(rx_queue, rx_buf, 1);
|
||||
}
|
||||
rx_buf->page = NULL;
|
||||
}
|
||||
|
||||
/* Recycle the pages that are used by buffers that have just been received. */
|
||||
static void efx_recycle_rx_pages(struct efx_channel *channel,
|
||||
struct efx_rx_buffer *rx_buf,
|
||||
@ -317,78 +167,6 @@ static void efx_discard_rx_packet(struct efx_channel *channel,
|
||||
efx_free_rx_buffers(rx_queue, rx_buf, n_frags);
|
||||
}
|
||||
|
||||
/**
|
||||
* efx_fast_push_rx_descriptors - push new RX descriptors quickly
|
||||
* @rx_queue: RX descriptor queue
|
||||
*
|
||||
* This will aim to fill the RX descriptor queue up to
|
||||
* @rx_queue->@max_fill. If there is insufficient atomic
|
||||
* memory to do so, a slow fill will be scheduled.
|
||||
*
|
||||
* The caller must provide serialisation (none is used here). In practise,
|
||||
* this means this function must run from the NAPI handler, or be called
|
||||
* when NAPI is disabled.
|
||||
*/
|
||||
void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue, bool atomic)
|
||||
{
|
||||
struct efx_nic *efx = rx_queue->efx;
|
||||
unsigned int fill_level, batch_size;
|
||||
int space, rc = 0;
|
||||
|
||||
if (!rx_queue->refill_enabled)
|
||||
return;
|
||||
|
||||
/* Calculate current fill level, and exit if we don't need to fill */
|
||||
fill_level = (rx_queue->added_count - rx_queue->removed_count);
|
||||
EFX_WARN_ON_ONCE_PARANOID(fill_level > rx_queue->efx->rxq_entries);
|
||||
if (fill_level >= rx_queue->fast_fill_trigger)
|
||||
goto out;
|
||||
|
||||
/* Record minimum fill level */
|
||||
if (unlikely(fill_level < rx_queue->min_fill)) {
|
||||
if (fill_level)
|
||||
rx_queue->min_fill = fill_level;
|
||||
}
|
||||
|
||||
batch_size = efx->rx_pages_per_batch * efx->rx_bufs_per_page;
|
||||
space = rx_queue->max_fill - fill_level;
|
||||
EFX_WARN_ON_ONCE_PARANOID(space < batch_size);
|
||||
|
||||
netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
|
||||
"RX queue %d fast-filling descriptor ring from"
|
||||
" level %d to level %d\n",
|
||||
efx_rx_queue_index(rx_queue), fill_level,
|
||||
rx_queue->max_fill);
|
||||
|
||||
|
||||
do {
|
||||
rc = efx_init_rx_buffers(rx_queue, atomic);
|
||||
if (unlikely(rc)) {
|
||||
/* Ensure that we don't leave the rx queue empty */
|
||||
efx_schedule_slow_fill(rx_queue);
|
||||
goto out;
|
||||
}
|
||||
} while ((space -= batch_size) >= batch_size);
|
||||
|
||||
netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
|
||||
"RX queue %d fast-filled descriptor ring "
|
||||
"to level %d\n", efx_rx_queue_index(rx_queue),
|
||||
rx_queue->added_count - rx_queue->removed_count);
|
||||
|
||||
out:
|
||||
if (rx_queue->notified_count != rx_queue->added_count)
|
||||
efx_nic_notify_rx_desc(rx_queue);
|
||||
}
|
||||
|
||||
void efx_rx_slow_fill(struct timer_list *t)
|
||||
{
|
||||
struct efx_rx_queue *rx_queue = from_timer(rx_queue, t, slow_fill);
|
||||
|
||||
/* Post an event to cause NAPI to run and refill the queue */
|
||||
efx_nic_generate_fill_event(rx_queue);
|
||||
++rx_queue->slow_fill_count;
|
||||
}
|
||||
|
||||
static void efx_rx_packet__check_len(struct efx_rx_queue *rx_queue,
|
||||
struct efx_rx_buffer *rx_buf,
|
||||
int len)
|
||||
@ -805,41 +583,10 @@ void __efx_rx_packet(struct efx_channel *channel)
|
||||
channel->rx_pkt_n_frags = 0;
|
||||
}
|
||||
|
||||
int efx_probe_rx_queue(struct efx_rx_queue *rx_queue)
|
||||
{
|
||||
struct efx_nic *efx = rx_queue->efx;
|
||||
unsigned int entries;
|
||||
int rc;
|
||||
|
||||
/* Create the smallest power-of-two aligned ring */
|
||||
entries = max(roundup_pow_of_two(efx->rxq_entries), EFX_MIN_DMAQ_SIZE);
|
||||
EFX_WARN_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
|
||||
rx_queue->ptr_mask = entries - 1;
|
||||
|
||||
netif_dbg(efx, probe, efx->net_dev,
|
||||
"creating RX queue %d size %#x mask %#x\n",
|
||||
efx_rx_queue_index(rx_queue), efx->rxq_entries,
|
||||
rx_queue->ptr_mask);
|
||||
|
||||
/* Allocate RX buffers */
|
||||
rx_queue->buffer = kcalloc(entries, sizeof(*rx_queue->buffer),
|
||||
GFP_KERNEL);
|
||||
if (!rx_queue->buffer)
|
||||
return -ENOMEM;
|
||||
|
||||
rc = efx_nic_probe_rx(rx_queue);
|
||||
if (rc) {
|
||||
kfree(rx_queue->buffer);
|
||||
rx_queue->buffer = NULL;
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void efx_init_rx_recycle_ring(struct efx_nic *efx,
|
||||
struct efx_rx_queue *rx_queue)
|
||||
void efx_init_rx_recycle_ring(struct efx_rx_queue *rx_queue)
|
||||
{
|
||||
unsigned int bufs_in_recycle_ring, page_ring_size;
|
||||
struct efx_nic *efx = rx_queue->efx;
|
||||
|
||||
/* Set the RX recycle ring size */
|
||||
#ifdef CONFIG_PPC64
|
||||
@ -858,121 +605,6 @@ static void efx_init_rx_recycle_ring(struct efx_nic *efx,
|
||||
rx_queue->page_ptr_mask = page_ring_size - 1;
|
||||
}
|
||||
|
||||
void efx_init_rx_queue(struct efx_rx_queue *rx_queue)
|
||||
{
|
||||
struct efx_nic *efx = rx_queue->efx;
|
||||
unsigned int max_fill, trigger, max_trigger;
|
||||
int rc = 0;
|
||||
|
||||
netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
|
||||
"initialising RX queue %d\n", efx_rx_queue_index(rx_queue));
|
||||
|
||||
/* Initialise ptr fields */
|
||||
rx_queue->added_count = 0;
|
||||
rx_queue->notified_count = 0;
|
||||
rx_queue->removed_count = 0;
|
||||
rx_queue->min_fill = -1U;
|
||||
efx_init_rx_recycle_ring(efx, rx_queue);
|
||||
|
||||
rx_queue->page_remove = 0;
|
||||
rx_queue->page_add = rx_queue->page_ptr_mask + 1;
|
||||
rx_queue->page_recycle_count = 0;
|
||||
rx_queue->page_recycle_failed = 0;
|
||||
rx_queue->page_recycle_full = 0;
|
||||
|
||||
/* Initialise limit fields */
|
||||
max_fill = efx->rxq_entries - EFX_RXD_HEAD_ROOM;
|
||||
max_trigger =
|
||||
max_fill - efx->rx_pages_per_batch * efx->rx_bufs_per_page;
|
||||
if (rx_refill_threshold != 0) {
|
||||
trigger = max_fill * min(rx_refill_threshold, 100U) / 100U;
|
||||
if (trigger > max_trigger)
|
||||
trigger = max_trigger;
|
||||
} else {
|
||||
trigger = max_trigger;
|
||||
}
|
||||
|
||||
rx_queue->max_fill = max_fill;
|
||||
rx_queue->fast_fill_trigger = trigger;
|
||||
rx_queue->refill_enabled = true;
|
||||
|
||||
/* Initialise XDP queue information */
|
||||
rc = xdp_rxq_info_reg(&rx_queue->xdp_rxq_info, efx->net_dev,
|
||||
rx_queue->core_index);
|
||||
|
||||
if (rc) {
|
||||
netif_err(efx, rx_err, efx->net_dev,
|
||||
"Failure to initialise XDP queue information rc=%d\n",
|
||||
rc);
|
||||
efx->xdp_rxq_info_failed = true;
|
||||
} else {
|
||||
rx_queue->xdp_rxq_info_valid = true;
|
||||
}
|
||||
|
||||
/* Set up RX descriptor ring */
|
||||
efx_nic_init_rx(rx_queue);
|
||||
}
|
||||
|
||||
void efx_fini_rx_queue(struct efx_rx_queue *rx_queue)
|
||||
{
|
||||
int i;
|
||||
struct efx_nic *efx = rx_queue->efx;
|
||||
struct efx_rx_buffer *rx_buf;
|
||||
|
||||
netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
|
||||
"shutting down RX queue %d\n", efx_rx_queue_index(rx_queue));
|
||||
|
||||
del_timer_sync(&rx_queue->slow_fill);
|
||||
|
||||
/* Release RX buffers from the current read ptr to the write ptr */
|
||||
if (rx_queue->buffer) {
|
||||
for (i = rx_queue->removed_count; i < rx_queue->added_count;
|
||||
i++) {
|
||||
unsigned index = i & rx_queue->ptr_mask;
|
||||
rx_buf = efx_rx_buffer(rx_queue, index);
|
||||
efx_fini_rx_buffer(rx_queue, rx_buf);
|
||||
}
|
||||
}
|
||||
|
||||
/* Unmap and release the pages in the recycle ring. Remove the ring. */
|
||||
for (i = 0; i <= rx_queue->page_ptr_mask; i++) {
|
||||
struct page *page = rx_queue->page_ring[i];
|
||||
struct efx_rx_page_state *state;
|
||||
|
||||
if (page == NULL)
|
||||
continue;
|
||||
|
||||
state = page_address(page);
|
||||
dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
|
||||
PAGE_SIZE << efx->rx_buffer_order,
|
||||
DMA_FROM_DEVICE);
|
||||
put_page(page);
|
||||
}
|
||||
kfree(rx_queue->page_ring);
|
||||
rx_queue->page_ring = NULL;
|
||||
|
||||
if (rx_queue->xdp_rxq_info_valid)
|
||||
xdp_rxq_info_unreg(&rx_queue->xdp_rxq_info);
|
||||
|
||||
rx_queue->xdp_rxq_info_valid = false;
|
||||
}
|
||||
|
||||
void efx_remove_rx_queue(struct efx_rx_queue *rx_queue)
|
||||
{
|
||||
netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
|
||||
"destroying RX queue %d\n", efx_rx_queue_index(rx_queue));
|
||||
|
||||
efx_nic_remove_rx(rx_queue);
|
||||
|
||||
kfree(rx_queue->buffer);
|
||||
rx_queue->buffer = NULL;
|
||||
}
|
||||
|
||||
|
||||
module_param(rx_refill_threshold, uint, 0444);
|
||||
MODULE_PARM_DESC(rx_refill_threshold,
|
||||
"RX descriptor ring refill threshold (%)");
|
||||
|
||||
#ifdef CONFIG_RFS_ACCEL
|
||||
|
||||
static void efx_filter_rfs_work(struct work_struct *data)
|
||||
|
375
drivers/net/ethernet/sfc/rx_common.c
Normal file
375
drivers/net/ethernet/sfc/rx_common.c
Normal file
@ -0,0 +1,375 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/****************************************************************************
|
||||
* Driver for Solarflare network controllers and boards
|
||||
* Copyright 2018 Solarflare Communications Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation, incorporated herein by reference.
|
||||
*/
|
||||
|
||||
#include "net_driver.h"
|
||||
#include <linux/module.h>
|
||||
#include "efx.h"
|
||||
#include "nic.h"
|
||||
#include "rx_common.h"
|
||||
|
||||
/* This is the percentage fill level below which new RX descriptors
|
||||
* will be added to the RX descriptor ring.
|
||||
*/
|
||||
static unsigned int rx_refill_threshold;
|
||||
module_param(rx_refill_threshold, uint, 0444);
|
||||
MODULE_PARM_DESC(rx_refill_threshold,
|
||||
"RX descriptor ring refill threshold (%)");
|
||||
|
||||
/* RX maximum head room required.
|
||||
*
|
||||
* This must be at least 1 to prevent overflow, plus one packet-worth
|
||||
* to allow pipelined receives.
|
||||
*/
|
||||
#define EFX_RXD_HEAD_ROOM (1 + EFX_RX_MAX_FRAGS)
|
||||
|
||||
static void efx_fini_rx_buffer(struct efx_rx_queue *rx_queue,
|
||||
struct efx_rx_buffer *rx_buf)
|
||||
{
|
||||
/* Release the page reference we hold for the buffer. */
|
||||
if (rx_buf->page)
|
||||
put_page(rx_buf->page);
|
||||
|
||||
/* If this is the last buffer in a page, unmap and free it. */
|
||||
if (rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE) {
|
||||
efx_unmap_rx_buffer(rx_queue->efx, rx_buf);
|
||||
efx_free_rx_buffers(rx_queue, rx_buf, 1);
|
||||
}
|
||||
rx_buf->page = NULL;
|
||||
}
|
||||
|
||||
int efx_probe_rx_queue(struct efx_rx_queue *rx_queue)
|
||||
{
|
||||
struct efx_nic *efx = rx_queue->efx;
|
||||
unsigned int entries;
|
||||
int rc;
|
||||
|
||||
/* Create the smallest power-of-two aligned ring */
|
||||
entries = max(roundup_pow_of_two(efx->rxq_entries), EFX_MIN_DMAQ_SIZE);
|
||||
EFX_WARN_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
|
||||
rx_queue->ptr_mask = entries - 1;
|
||||
|
||||
netif_dbg(efx, probe, efx->net_dev,
|
||||
"creating RX queue %d size %#x mask %#x\n",
|
||||
efx_rx_queue_index(rx_queue), efx->rxq_entries,
|
||||
rx_queue->ptr_mask);
|
||||
|
||||
/* Allocate RX buffers */
|
||||
rx_queue->buffer = kcalloc(entries, sizeof(*rx_queue->buffer),
|
||||
GFP_KERNEL);
|
||||
if (!rx_queue->buffer)
|
||||
return -ENOMEM;
|
||||
|
||||
rc = efx_nic_probe_rx(rx_queue);
|
||||
if (rc) {
|
||||
kfree(rx_queue->buffer);
|
||||
rx_queue->buffer = NULL;
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
void efx_init_rx_queue(struct efx_rx_queue *rx_queue)
|
||||
{
|
||||
unsigned int max_fill, trigger, max_trigger;
|
||||
struct efx_nic *efx = rx_queue->efx;
|
||||
int rc = 0;
|
||||
|
||||
netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
|
||||
"initialising RX queue %d\n", efx_rx_queue_index(rx_queue));
|
||||
|
||||
/* Initialise ptr fields */
|
||||
rx_queue->added_count = 0;
|
||||
rx_queue->notified_count = 0;
|
||||
rx_queue->removed_count = 0;
|
||||
rx_queue->min_fill = -1U;
|
||||
efx_init_rx_recycle_ring(rx_queue);
|
||||
|
||||
rx_queue->page_remove = 0;
|
||||
rx_queue->page_add = rx_queue->page_ptr_mask + 1;
|
||||
rx_queue->page_recycle_count = 0;
|
||||
rx_queue->page_recycle_failed = 0;
|
||||
rx_queue->page_recycle_full = 0;
|
||||
|
||||
/* Initialise limit fields */
|
||||
max_fill = efx->rxq_entries - EFX_RXD_HEAD_ROOM;
|
||||
max_trigger =
|
||||
max_fill - efx->rx_pages_per_batch * efx->rx_bufs_per_page;
|
||||
if (rx_refill_threshold != 0) {
|
||||
trigger = max_fill * min(rx_refill_threshold, 100U) / 100U;
|
||||
if (trigger > max_trigger)
|
||||
trigger = max_trigger;
|
||||
} else {
|
||||
trigger = max_trigger;
|
||||
}
|
||||
|
||||
rx_queue->max_fill = max_fill;
|
||||
rx_queue->fast_fill_trigger = trigger;
|
||||
rx_queue->refill_enabled = true;
|
||||
|
||||
/* Initialise XDP queue information */
|
||||
rc = xdp_rxq_info_reg(&rx_queue->xdp_rxq_info, efx->net_dev,
|
||||
rx_queue->core_index);
|
||||
|
||||
if (rc) {
|
||||
netif_err(efx, rx_err, efx->net_dev,
|
||||
"Failure to initialise XDP queue information rc=%d\n",
|
||||
rc);
|
||||
efx->xdp_rxq_info_failed = true;
|
||||
} else {
|
||||
rx_queue->xdp_rxq_info_valid = true;
|
||||
}
|
||||
|
||||
/* Set up RX descriptor ring */
|
||||
efx_nic_init_rx(rx_queue);
|
||||
}
|
||||
|
||||
void efx_fini_rx_queue(struct efx_rx_queue *rx_queue)
|
||||
{
|
||||
struct efx_nic *efx = rx_queue->efx;
|
||||
struct efx_rx_buffer *rx_buf;
|
||||
int i;
|
||||
|
||||
netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
|
||||
"shutting down RX queue %d\n", efx_rx_queue_index(rx_queue));
|
||||
|
||||
del_timer_sync(&rx_queue->slow_fill);
|
||||
|
||||
/* Release RX buffers from the current read ptr to the write ptr */
|
||||
if (rx_queue->buffer) {
|
||||
for (i = rx_queue->removed_count; i < rx_queue->added_count;
|
||||
i++) {
|
||||
unsigned int index = i & rx_queue->ptr_mask;
|
||||
|
||||
rx_buf = efx_rx_buffer(rx_queue, index);
|
||||
efx_fini_rx_buffer(rx_queue, rx_buf);
|
||||
}
|
||||
}
|
||||
|
||||
/* Unmap and release the pages in the recycle ring. Remove the ring. */
|
||||
for (i = 0; i <= rx_queue->page_ptr_mask; i++) {
|
||||
struct page *page = rx_queue->page_ring[i];
|
||||
struct efx_rx_page_state *state;
|
||||
|
||||
if (page == NULL)
|
||||
continue;
|
||||
|
||||
state = page_address(page);
|
||||
dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
|
||||
PAGE_SIZE << efx->rx_buffer_order,
|
||||
DMA_FROM_DEVICE);
|
||||
put_page(page);
|
||||
}
|
||||
kfree(rx_queue->page_ring);
|
||||
rx_queue->page_ring = NULL;
|
||||
|
||||
if (rx_queue->xdp_rxq_info_valid)
|
||||
xdp_rxq_info_unreg(&rx_queue->xdp_rxq_info);
|
||||
|
||||
rx_queue->xdp_rxq_info_valid = false;
|
||||
}
|
||||
|
||||
void efx_remove_rx_queue(struct efx_rx_queue *rx_queue)
|
||||
{
|
||||
netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
|
||||
"destroying RX queue %d\n", efx_rx_queue_index(rx_queue));
|
||||
|
||||
efx_nic_remove_rx(rx_queue);
|
||||
|
||||
kfree(rx_queue->buffer);
|
||||
rx_queue->buffer = NULL;
|
||||
}
|
||||
|
||||
/* Unmap a DMA-mapped page. This function is only called for the final RX
|
||||
* buffer in a page.
|
||||
*/
|
||||
void efx_unmap_rx_buffer(struct efx_nic *efx,
|
||||
struct efx_rx_buffer *rx_buf)
|
||||
{
|
||||
struct page *page = rx_buf->page;
|
||||
|
||||
if (page) {
|
||||
struct efx_rx_page_state *state = page_address(page);
|
||||
|
||||
dma_unmap_page(&efx->pci_dev->dev,
|
||||
state->dma_addr,
|
||||
PAGE_SIZE << efx->rx_buffer_order,
|
||||
DMA_FROM_DEVICE);
|
||||
}
|
||||
}
|
||||
|
||||
void efx_free_rx_buffers(struct efx_rx_queue *rx_queue,
|
||||
struct efx_rx_buffer *rx_buf,
|
||||
unsigned int num_bufs)
|
||||
{
|
||||
do {
|
||||
if (rx_buf->page) {
|
||||
put_page(rx_buf->page);
|
||||
rx_buf->page = NULL;
|
||||
}
|
||||
rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
|
||||
} while (--num_bufs);
|
||||
}
|
||||
|
||||
void efx_rx_slow_fill(struct timer_list *t)
|
||||
{
|
||||
struct efx_rx_queue *rx_queue = from_timer(rx_queue, t, slow_fill);
|
||||
|
||||
/* Post an event to cause NAPI to run and refill the queue */
|
||||
efx_nic_generate_fill_event(rx_queue);
|
||||
++rx_queue->slow_fill_count;
|
||||
}
|
||||
|
||||
void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
|
||||
{
|
||||
mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(10));
|
||||
}
|
||||
|
||||
/* efx_init_rx_buffers - create EFX_RX_BATCH page-based RX buffers
|
||||
*
|
||||
* @rx_queue: Efx RX queue
|
||||
*
|
||||
* This allocates a batch of pages, maps them for DMA, and populates
|
||||
* struct efx_rx_buffers for each one. Return a negative error code or
|
||||
* 0 on success. If a single page can be used for multiple buffers,
|
||||
* then the page will either be inserted fully, or not at all.
|
||||
*/
|
||||
static int efx_init_rx_buffers(struct efx_rx_queue *rx_queue, bool atomic)
|
||||
{
|
||||
unsigned int page_offset, index, count;
|
||||
struct efx_nic *efx = rx_queue->efx;
|
||||
struct efx_rx_page_state *state;
|
||||
struct efx_rx_buffer *rx_buf;
|
||||
dma_addr_t dma_addr;
|
||||
struct page *page;
|
||||
|
||||
count = 0;
|
||||
do {
|
||||
page = efx_reuse_page(rx_queue);
|
||||
if (page == NULL) {
|
||||
page = alloc_pages(__GFP_COMP |
|
||||
(atomic ? GFP_ATOMIC : GFP_KERNEL),
|
||||
efx->rx_buffer_order);
|
||||
if (unlikely(page == NULL))
|
||||
return -ENOMEM;
|
||||
dma_addr =
|
||||
dma_map_page(&efx->pci_dev->dev, page, 0,
|
||||
PAGE_SIZE << efx->rx_buffer_order,
|
||||
DMA_FROM_DEVICE);
|
||||
if (unlikely(dma_mapping_error(&efx->pci_dev->dev,
|
||||
dma_addr))) {
|
||||
__free_pages(page, efx->rx_buffer_order);
|
||||
return -EIO;
|
||||
}
|
||||
state = page_address(page);
|
||||
state->dma_addr = dma_addr;
|
||||
} else {
|
||||
state = page_address(page);
|
||||
dma_addr = state->dma_addr;
|
||||
}
|
||||
|
||||
dma_addr += sizeof(struct efx_rx_page_state);
|
||||
page_offset = sizeof(struct efx_rx_page_state);
|
||||
|
||||
do {
|
||||
index = rx_queue->added_count & rx_queue->ptr_mask;
|
||||
rx_buf = efx_rx_buffer(rx_queue, index);
|
||||
rx_buf->dma_addr = dma_addr + efx->rx_ip_align +
|
||||
XDP_PACKET_HEADROOM;
|
||||
rx_buf->page = page;
|
||||
rx_buf->page_offset = page_offset + efx->rx_ip_align +
|
||||
XDP_PACKET_HEADROOM;
|
||||
rx_buf->len = efx->rx_dma_len;
|
||||
rx_buf->flags = 0;
|
||||
++rx_queue->added_count;
|
||||
get_page(page);
|
||||
dma_addr += efx->rx_page_buf_step;
|
||||
page_offset += efx->rx_page_buf_step;
|
||||
} while (page_offset + efx->rx_page_buf_step <= PAGE_SIZE);
|
||||
|
||||
rx_buf->flags = EFX_RX_BUF_LAST_IN_PAGE;
|
||||
} while (++count < efx->rx_pages_per_batch);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void efx_rx_config_page_split(struct efx_nic *efx)
|
||||
{
|
||||
efx->rx_page_buf_step = ALIGN(efx->rx_dma_len + efx->rx_ip_align +
|
||||
XDP_PACKET_HEADROOM,
|
||||
EFX_RX_BUF_ALIGNMENT);
|
||||
efx->rx_bufs_per_page = efx->rx_buffer_order ? 1 :
|
||||
((PAGE_SIZE - sizeof(struct efx_rx_page_state)) /
|
||||
efx->rx_page_buf_step);
|
||||
efx->rx_buffer_truesize = (PAGE_SIZE << efx->rx_buffer_order) /
|
||||
efx->rx_bufs_per_page;
|
||||
efx->rx_pages_per_batch = DIV_ROUND_UP(EFX_RX_PREFERRED_BATCH,
|
||||
efx->rx_bufs_per_page);
|
||||
}
|
||||
|
||||
/* efx_fast_push_rx_descriptors - push new RX descriptors quickly
|
||||
* @rx_queue: RX descriptor queue
|
||||
*
|
||||
* This will aim to fill the RX descriptor queue up to
|
||||
* @rx_queue->@max_fill. If there is insufficient atomic
|
||||
* memory to do so, a slow fill will be scheduled.
|
||||
*
|
||||
* The caller must provide serialisation (none is used here). In practise,
|
||||
* this means this function must run from the NAPI handler, or be called
|
||||
* when NAPI is disabled.
|
||||
*/
|
||||
void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue, bool atomic)
|
||||
{
|
||||
struct efx_nic *efx = rx_queue->efx;
|
||||
unsigned int fill_level, batch_size;
|
||||
int space, rc = 0;
|
||||
|
||||
if (!rx_queue->refill_enabled)
|
||||
return;
|
||||
|
||||
/* Calculate current fill level, and exit if we don't need to fill */
|
||||
fill_level = (rx_queue->added_count - rx_queue->removed_count);
|
||||
EFX_WARN_ON_ONCE_PARANOID(fill_level > rx_queue->efx->rxq_entries);
|
||||
if (fill_level >= rx_queue->fast_fill_trigger)
|
||||
goto out;
|
||||
|
||||
/* Record minimum fill level */
|
||||
if (unlikely(fill_level < rx_queue->min_fill)) {
|
||||
if (fill_level)
|
||||
rx_queue->min_fill = fill_level;
|
||||
}
|
||||
|
||||
batch_size = efx->rx_pages_per_batch * efx->rx_bufs_per_page;
|
||||
space = rx_queue->max_fill - fill_level;
|
||||
EFX_WARN_ON_ONCE_PARANOID(space < batch_size);
|
||||
|
||||
netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
|
||||
"RX queue %d fast-filling descriptor ring from"
|
||||
" level %d to level %d\n",
|
||||
efx_rx_queue_index(rx_queue), fill_level,
|
||||
rx_queue->max_fill);
|
||||
|
||||
do {
|
||||
rc = efx_init_rx_buffers(rx_queue, atomic);
|
||||
if (unlikely(rc)) {
|
||||
/* Ensure that we don't leave the rx queue empty */
|
||||
efx_schedule_slow_fill(rx_queue);
|
||||
goto out;
|
||||
}
|
||||
} while ((space -= batch_size) >= batch_size);
|
||||
|
||||
netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
|
||||
"RX queue %d fast-filled descriptor ring "
|
||||
"to level %d\n", efx_rx_queue_index(rx_queue),
|
||||
rx_queue->added_count - rx_queue->removed_count);
|
||||
|
||||
out:
|
||||
if (rx_queue->notified_count != rx_queue->added_count)
|
||||
efx_nic_notify_rx_desc(rx_queue);
|
||||
}
|
42
drivers/net/ethernet/sfc/rx_common.h
Normal file
42
drivers/net/ethernet/sfc/rx_common.h
Normal file
@ -0,0 +1,42 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/****************************************************************************
|
||||
* Driver for Solarflare network controllers and boards
|
||||
* Copyright 2018 Solarflare Communications Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation, incorporated herein by reference.
|
||||
*/
|
||||
|
||||
#ifndef EFX_RX_COMMON_H
|
||||
#define EFX_RX_COMMON_H
|
||||
|
||||
/* Preferred number of descriptors to fill at once */
|
||||
#define EFX_RX_PREFERRED_BATCH 8U
|
||||
|
||||
/* Each packet can consume up to ceil(max_frame_len / buffer_size) buffers */
|
||||
#define EFX_RX_MAX_FRAGS DIV_ROUND_UP(EFX_MAX_FRAME_LEN(EFX_MAX_MTU), \
|
||||
EFX_RX_USR_BUF_SIZE)
|
||||
|
||||
void efx_rx_slow_fill(struct timer_list *t);
|
||||
|
||||
int efx_probe_rx_queue(struct efx_rx_queue *rx_queue);
|
||||
void efx_init_rx_queue(struct efx_rx_queue *rx_queue);
|
||||
void efx_fini_rx_queue(struct efx_rx_queue *rx_queue);
|
||||
void efx_remove_rx_queue(struct efx_rx_queue *rx_queue);
|
||||
void efx_destroy_rx_queue(struct efx_rx_queue *rx_queue);
|
||||
|
||||
void efx_init_rx_buffer(struct efx_rx_queue *rx_queue,
|
||||
struct page *page,
|
||||
unsigned int page_offset,
|
||||
u16 flags);
|
||||
void efx_unmap_rx_buffer(struct efx_nic *efx, struct efx_rx_buffer *rx_buf);
|
||||
void efx_free_rx_buffers(struct efx_rx_queue *rx_queue,
|
||||
struct efx_rx_buffer *rx_buf,
|
||||
unsigned int num_bufs);
|
||||
|
||||
void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue);
|
||||
void efx_rx_config_page_split(struct efx_nic *efx);
|
||||
void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue, bool atomic);
|
||||
|
||||
#endif
|
@ -18,6 +18,8 @@
|
||||
#include <linux/slab.h>
|
||||
#include "net_driver.h"
|
||||
#include "efx.h"
|
||||
#include "efx_common.h"
|
||||
#include "efx_channels.h"
|
||||
#include "nic.h"
|
||||
#include "selftest.h"
|
||||
#include "workarounds.h"
|
||||
|
@ -14,6 +14,7 @@
|
||||
#include "net_driver.h"
|
||||
#include "bitfield.h"
|
||||
#include "efx.h"
|
||||
#include "efx_common.h"
|
||||
#include "nic.h"
|
||||
#include "farch_regs.h"
|
||||
#include "io.h"
|
||||
|
@ -7,6 +7,7 @@
|
||||
#include <linux/module.h>
|
||||
#include "net_driver.h"
|
||||
#include "efx.h"
|
||||
#include "efx_channels.h"
|
||||
#include "nic.h"
|
||||
#include "io.h"
|
||||
#include "mcdi.h"
|
||||
|
@ -20,6 +20,7 @@
|
||||
#include "io.h"
|
||||
#include "nic.h"
|
||||
#include "tx.h"
|
||||
#include "tx_common.h"
|
||||
#include "workarounds.h"
|
||||
#include "ef10_regs.h"
|
||||
|
||||
@ -56,72 +57,6 @@ u8 *efx_tx_get_copy_buffer_limited(struct efx_tx_queue *tx_queue,
|
||||
return efx_tx_get_copy_buffer(tx_queue, buffer);
|
||||
}
|
||||
|
||||
static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
|
||||
struct efx_tx_buffer *buffer,
|
||||
unsigned int *pkts_compl,
|
||||
unsigned int *bytes_compl)
|
||||
{
|
||||
if (buffer->unmap_len) {
|
||||
struct device *dma_dev = &tx_queue->efx->pci_dev->dev;
|
||||
dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset;
|
||||
if (buffer->flags & EFX_TX_BUF_MAP_SINGLE)
|
||||
dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len,
|
||||
DMA_TO_DEVICE);
|
||||
else
|
||||
dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len,
|
||||
DMA_TO_DEVICE);
|
||||
buffer->unmap_len = 0;
|
||||
}
|
||||
|
||||
if (buffer->flags & EFX_TX_BUF_SKB) {
|
||||
struct sk_buff *skb = (struct sk_buff *)buffer->skb;
|
||||
|
||||
EFX_WARN_ON_PARANOID(!pkts_compl || !bytes_compl);
|
||||
(*pkts_compl)++;
|
||||
(*bytes_compl) += skb->len;
|
||||
if (tx_queue->timestamping &&
|
||||
(tx_queue->completed_timestamp_major ||
|
||||
tx_queue->completed_timestamp_minor)) {
|
||||
struct skb_shared_hwtstamps hwtstamp;
|
||||
|
||||
hwtstamp.hwtstamp =
|
||||
efx_ptp_nic_to_kernel_time(tx_queue);
|
||||
skb_tstamp_tx(skb, &hwtstamp);
|
||||
|
||||
tx_queue->completed_timestamp_major = 0;
|
||||
tx_queue->completed_timestamp_minor = 0;
|
||||
}
|
||||
dev_consume_skb_any((struct sk_buff *)buffer->skb);
|
||||
netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
|
||||
"TX queue %d transmission id %x complete\n",
|
||||
tx_queue->queue, tx_queue->read_count);
|
||||
} else if (buffer->flags & EFX_TX_BUF_XDP) {
|
||||
xdp_return_frame_rx_napi(buffer->xdpf);
|
||||
}
|
||||
|
||||
buffer->len = 0;
|
||||
buffer->flags = 0;
|
||||
}
|
||||
|
||||
unsigned int efx_tx_max_skb_descs(struct efx_nic *efx)
|
||||
{
|
||||
/* Header and payload descriptor for each output segment, plus
|
||||
* one for every input fragment boundary within a segment
|
||||
*/
|
||||
unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS;
|
||||
|
||||
/* Possibly one more per segment for option descriptors */
|
||||
if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
|
||||
max_descs += EFX_TSO_MAX_SEGS;
|
||||
|
||||
/* Possibly more for PCIe page boundaries within input fragments */
|
||||
if (PAGE_SIZE > EFX_PAGE_SIZE)
|
||||
max_descs += max_t(unsigned int, MAX_SKB_FRAGS,
|
||||
DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE));
|
||||
|
||||
return max_descs;
|
||||
}
|
||||
|
||||
static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1)
|
||||
{
|
||||
/* We need to consider both queues that the net core sees as one */
|
||||
@ -333,107 +268,6 @@ static int efx_enqueue_skb_pio(struct efx_tx_queue *tx_queue,
|
||||
}
|
||||
#endif /* EFX_USE_PIO */
|
||||
|
||||
static struct efx_tx_buffer *efx_tx_map_chunk(struct efx_tx_queue *tx_queue,
|
||||
dma_addr_t dma_addr,
|
||||
size_t len)
|
||||
{
|
||||
const struct efx_nic_type *nic_type = tx_queue->efx->type;
|
||||
struct efx_tx_buffer *buffer;
|
||||
unsigned int dma_len;
|
||||
|
||||
/* Map the fragment taking account of NIC-dependent DMA limits. */
|
||||
do {
|
||||
buffer = efx_tx_queue_get_insert_buffer(tx_queue);
|
||||
dma_len = nic_type->tx_limit_len(tx_queue, dma_addr, len);
|
||||
|
||||
buffer->len = dma_len;
|
||||
buffer->dma_addr = dma_addr;
|
||||
buffer->flags = EFX_TX_BUF_CONT;
|
||||
len -= dma_len;
|
||||
dma_addr += dma_len;
|
||||
++tx_queue->insert_count;
|
||||
} while (len);
|
||||
|
||||
return buffer;
|
||||
}
|
||||
|
||||
/* Map all data from an SKB for DMA and create descriptors on the queue.
|
||||
*/
|
||||
static int efx_tx_map_data(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
|
||||
unsigned int segment_count)
|
||||
{
|
||||
struct efx_nic *efx = tx_queue->efx;
|
||||
struct device *dma_dev = &efx->pci_dev->dev;
|
||||
unsigned int frag_index, nr_frags;
|
||||
dma_addr_t dma_addr, unmap_addr;
|
||||
unsigned short dma_flags;
|
||||
size_t len, unmap_len;
|
||||
|
||||
nr_frags = skb_shinfo(skb)->nr_frags;
|
||||
frag_index = 0;
|
||||
|
||||
/* Map header data. */
|
||||
len = skb_headlen(skb);
|
||||
dma_addr = dma_map_single(dma_dev, skb->data, len, DMA_TO_DEVICE);
|
||||
dma_flags = EFX_TX_BUF_MAP_SINGLE;
|
||||
unmap_len = len;
|
||||
unmap_addr = dma_addr;
|
||||
|
||||
if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
|
||||
return -EIO;
|
||||
|
||||
if (segment_count) {
|
||||
/* For TSO we need to put the header in to a separate
|
||||
* descriptor. Map this separately if necessary.
|
||||
*/
|
||||
size_t header_len = skb_transport_header(skb) - skb->data +
|
||||
(tcp_hdr(skb)->doff << 2u);
|
||||
|
||||
if (header_len != len) {
|
||||
tx_queue->tso_long_headers++;
|
||||
efx_tx_map_chunk(tx_queue, dma_addr, header_len);
|
||||
len -= header_len;
|
||||
dma_addr += header_len;
|
||||
}
|
||||
}
|
||||
|
||||
/* Add descriptors for each fragment. */
|
||||
do {
|
||||
struct efx_tx_buffer *buffer;
|
||||
skb_frag_t *fragment;
|
||||
|
||||
buffer = efx_tx_map_chunk(tx_queue, dma_addr, len);
|
||||
|
||||
/* The final descriptor for a fragment is responsible for
|
||||
* unmapping the whole fragment.
|
||||
*/
|
||||
buffer->flags = EFX_TX_BUF_CONT | dma_flags;
|
||||
buffer->unmap_len = unmap_len;
|
||||
buffer->dma_offset = buffer->dma_addr - unmap_addr;
|
||||
|
||||
if (frag_index >= nr_frags) {
|
||||
/* Store SKB details with the final buffer for
|
||||
* the completion.
|
||||
*/
|
||||
buffer->skb = skb;
|
||||
buffer->flags = EFX_TX_BUF_SKB | dma_flags;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Move on to the next fragment. */
|
||||
fragment = &skb_shinfo(skb)->frags[frag_index++];
|
||||
len = skb_frag_size(fragment);
|
||||
dma_addr = skb_frag_dma_map(dma_dev, fragment,
|
||||
0, len, DMA_TO_DEVICE);
|
||||
dma_flags = 0;
|
||||
unmap_len = len;
|
||||
unmap_addr = dma_addr;
|
||||
|
||||
if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
|
||||
return -EIO;
|
||||
} while (1);
|
||||
}
|
||||
|
||||
/* Remove buffers put into a tx_queue for the current packet.
|
||||
* None of the buffers must have an skb attached.
|
||||
*/
|
||||
@ -876,131 +710,3 @@ void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int efx_tx_cb_page_count(struct efx_tx_queue *tx_queue)
|
||||
{
|
||||
return DIV_ROUND_UP(tx_queue->ptr_mask + 1, PAGE_SIZE >> EFX_TX_CB_ORDER);
|
||||
}
|
||||
|
||||
int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
|
||||
{
|
||||
struct efx_nic *efx = tx_queue->efx;
|
||||
unsigned int entries;
|
||||
int rc;
|
||||
|
||||
/* Create the smallest power-of-two aligned ring */
|
||||
entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
|
||||
EFX_WARN_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
|
||||
tx_queue->ptr_mask = entries - 1;
|
||||
|
||||
netif_dbg(efx, probe, efx->net_dev,
|
||||
"creating TX queue %d size %#x mask %#x\n",
|
||||
tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
|
||||
|
||||
/* Allocate software ring */
|
||||
tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer),
|
||||
GFP_KERNEL);
|
||||
if (!tx_queue->buffer)
|
||||
return -ENOMEM;
|
||||
|
||||
tx_queue->cb_page = kcalloc(efx_tx_cb_page_count(tx_queue),
|
||||
sizeof(tx_queue->cb_page[0]), GFP_KERNEL);
|
||||
if (!tx_queue->cb_page) {
|
||||
rc = -ENOMEM;
|
||||
goto fail1;
|
||||
}
|
||||
|
||||
/* Allocate hardware ring */
|
||||
rc = efx_nic_probe_tx(tx_queue);
|
||||
if (rc)
|
||||
goto fail2;
|
||||
|
||||
return 0;
|
||||
|
||||
fail2:
|
||||
kfree(tx_queue->cb_page);
|
||||
tx_queue->cb_page = NULL;
|
||||
fail1:
|
||||
kfree(tx_queue->buffer);
|
||||
tx_queue->buffer = NULL;
|
||||
return rc;
|
||||
}
|
||||
|
||||
void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
|
||||
{
|
||||
struct efx_nic *efx = tx_queue->efx;
|
||||
|
||||
netif_dbg(efx, drv, efx->net_dev,
|
||||
"initialising TX queue %d\n", tx_queue->queue);
|
||||
|
||||
tx_queue->insert_count = 0;
|
||||
tx_queue->write_count = 0;
|
||||
tx_queue->packet_write_count = 0;
|
||||
tx_queue->old_write_count = 0;
|
||||
tx_queue->read_count = 0;
|
||||
tx_queue->old_read_count = 0;
|
||||
tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
|
||||
tx_queue->xmit_more_available = false;
|
||||
tx_queue->timestamping = (efx_ptp_use_mac_tx_timestamps(efx) &&
|
||||
tx_queue->channel == efx_ptp_channel(efx));
|
||||
tx_queue->completed_desc_ptr = tx_queue->ptr_mask;
|
||||
tx_queue->completed_timestamp_major = 0;
|
||||
tx_queue->completed_timestamp_minor = 0;
|
||||
|
||||
tx_queue->xdp_tx = efx_channel_is_xdp_tx(tx_queue->channel);
|
||||
|
||||
/* Set up default function pointers. These may get replaced by
|
||||
* efx_nic_init_tx() based off NIC/queue capabilities.
|
||||
*/
|
||||
tx_queue->handle_tso = efx_enqueue_skb_tso;
|
||||
|
||||
/* Set up TX descriptor ring */
|
||||
efx_nic_init_tx(tx_queue);
|
||||
|
||||
tx_queue->initialised = true;
|
||||
}
|
||||
|
||||
void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
|
||||
{
|
||||
struct efx_tx_buffer *buffer;
|
||||
|
||||
netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
|
||||
"shutting down TX queue %d\n", tx_queue->queue);
|
||||
|
||||
if (!tx_queue->buffer)
|
||||
return;
|
||||
|
||||
/* Free any buffers left in the ring */
|
||||
while (tx_queue->read_count != tx_queue->write_count) {
|
||||
unsigned int pkts_compl = 0, bytes_compl = 0;
|
||||
buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
|
||||
efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
|
||||
|
||||
++tx_queue->read_count;
|
||||
}
|
||||
tx_queue->xmit_more_available = false;
|
||||
netdev_tx_reset_queue(tx_queue->core_txq);
|
||||
}
|
||||
|
||||
void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (!tx_queue->buffer)
|
||||
return;
|
||||
|
||||
netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
|
||||
"destroying TX queue %d\n", tx_queue->queue);
|
||||
efx_nic_remove_tx(tx_queue);
|
||||
|
||||
if (tx_queue->cb_page) {
|
||||
for (i = 0; i < efx_tx_cb_page_count(tx_queue); i++)
|
||||
efx_nic_free_buffer(tx_queue->efx,
|
||||
&tx_queue->cb_page[i]);
|
||||
kfree(tx_queue->cb_page);
|
||||
tx_queue->cb_page = NULL;
|
||||
}
|
||||
|
||||
kfree(tx_queue->buffer);
|
||||
tx_queue->buffer = NULL;
|
||||
}
|
||||
|
310
drivers/net/ethernet/sfc/tx_common.c
Normal file
310
drivers/net/ethernet/sfc/tx_common.c
Normal file
@ -0,0 +1,310 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/****************************************************************************
|
||||
* Driver for Solarflare network controllers and boards
|
||||
* Copyright 2018 Solarflare Communications Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation, incorporated herein by reference.
|
||||
*/
|
||||
|
||||
#include "net_driver.h"
|
||||
#include "efx.h"
|
||||
#include "nic.h"
|
||||
#include "tx_common.h"
|
||||
|
||||
static unsigned int efx_tx_cb_page_count(struct efx_tx_queue *tx_queue)
|
||||
{
|
||||
return DIV_ROUND_UP(tx_queue->ptr_mask + 1,
|
||||
PAGE_SIZE >> EFX_TX_CB_ORDER);
|
||||
}
|
||||
|
||||
int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
|
||||
{
|
||||
struct efx_nic *efx = tx_queue->efx;
|
||||
unsigned int entries;
|
||||
int rc;
|
||||
|
||||
/* Create the smallest power-of-two aligned ring */
|
||||
entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
|
||||
EFX_WARN_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
|
||||
tx_queue->ptr_mask = entries - 1;
|
||||
|
||||
netif_dbg(efx, probe, efx->net_dev,
|
||||
"creating TX queue %d size %#x mask %#x\n",
|
||||
tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
|
||||
|
||||
/* Allocate software ring */
|
||||
tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer),
|
||||
GFP_KERNEL);
|
||||
if (!tx_queue->buffer)
|
||||
return -ENOMEM;
|
||||
|
||||
tx_queue->cb_page = kcalloc(efx_tx_cb_page_count(tx_queue),
|
||||
sizeof(tx_queue->cb_page[0]), GFP_KERNEL);
|
||||
if (!tx_queue->cb_page) {
|
||||
rc = -ENOMEM;
|
||||
goto fail1;
|
||||
}
|
||||
|
||||
/* Allocate hardware ring */
|
||||
rc = efx_nic_probe_tx(tx_queue);
|
||||
if (rc)
|
||||
goto fail2;
|
||||
|
||||
return 0;
|
||||
|
||||
fail2:
|
||||
kfree(tx_queue->cb_page);
|
||||
tx_queue->cb_page = NULL;
|
||||
fail1:
|
||||
kfree(tx_queue->buffer);
|
||||
tx_queue->buffer = NULL;
|
||||
return rc;
|
||||
}
|
||||
|
||||
void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
|
||||
{
|
||||
struct efx_nic *efx = tx_queue->efx;
|
||||
|
||||
netif_dbg(efx, drv, efx->net_dev,
|
||||
"initialising TX queue %d\n", tx_queue->queue);
|
||||
|
||||
tx_queue->insert_count = 0;
|
||||
tx_queue->write_count = 0;
|
||||
tx_queue->packet_write_count = 0;
|
||||
tx_queue->old_write_count = 0;
|
||||
tx_queue->read_count = 0;
|
||||
tx_queue->old_read_count = 0;
|
||||
tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
|
||||
tx_queue->xmit_more_available = false;
|
||||
tx_queue->timestamping = (efx_ptp_use_mac_tx_timestamps(efx) &&
|
||||
tx_queue->channel == efx_ptp_channel(efx));
|
||||
tx_queue->completed_desc_ptr = tx_queue->ptr_mask;
|
||||
tx_queue->completed_timestamp_major = 0;
|
||||
tx_queue->completed_timestamp_minor = 0;
|
||||
|
||||
tx_queue->xdp_tx = efx_channel_is_xdp_tx(tx_queue->channel);
|
||||
|
||||
/* Set up default function pointers. These may get replaced by
|
||||
* efx_nic_init_tx() based off NIC/queue capabilities.
|
||||
*/
|
||||
tx_queue->handle_tso = efx_enqueue_skb_tso;
|
||||
|
||||
/* Set up TX descriptor ring */
|
||||
efx_nic_init_tx(tx_queue);
|
||||
|
||||
tx_queue->initialised = true;
|
||||
}
|
||||
|
||||
void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
|
||||
{
|
||||
struct efx_tx_buffer *buffer;
|
||||
|
||||
netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
|
||||
"shutting down TX queue %d\n", tx_queue->queue);
|
||||
|
||||
if (!tx_queue->buffer)
|
||||
return;
|
||||
|
||||
/* Free any buffers left in the ring */
|
||||
while (tx_queue->read_count != tx_queue->write_count) {
|
||||
unsigned int pkts_compl = 0, bytes_compl = 0;
|
||||
|
||||
buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
|
||||
efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
|
||||
|
||||
++tx_queue->read_count;
|
||||
}
|
||||
tx_queue->xmit_more_available = false;
|
||||
netdev_tx_reset_queue(tx_queue->core_txq);
|
||||
}
|
||||
|
||||
void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (!tx_queue->buffer)
|
||||
return;
|
||||
|
||||
netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
|
||||
"destroying TX queue %d\n", tx_queue->queue);
|
||||
efx_nic_remove_tx(tx_queue);
|
||||
|
||||
if (tx_queue->cb_page) {
|
||||
for (i = 0; i < efx_tx_cb_page_count(tx_queue); i++)
|
||||
efx_nic_free_buffer(tx_queue->efx,
|
||||
&tx_queue->cb_page[i]);
|
||||
kfree(tx_queue->cb_page);
|
||||
tx_queue->cb_page = NULL;
|
||||
}
|
||||
|
||||
kfree(tx_queue->buffer);
|
||||
tx_queue->buffer = NULL;
|
||||
}
|
||||
|
||||
void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
|
||||
struct efx_tx_buffer *buffer,
|
||||
unsigned int *pkts_compl,
|
||||
unsigned int *bytes_compl)
|
||||
{
|
||||
if (buffer->unmap_len) {
|
||||
struct device *dma_dev = &tx_queue->efx->pci_dev->dev;
|
||||
dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset;
|
||||
|
||||
if (buffer->flags & EFX_TX_BUF_MAP_SINGLE)
|
||||
dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len,
|
||||
DMA_TO_DEVICE);
|
||||
else
|
||||
dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len,
|
||||
DMA_TO_DEVICE);
|
||||
buffer->unmap_len = 0;
|
||||
}
|
||||
|
||||
if (buffer->flags & EFX_TX_BUF_SKB) {
|
||||
struct sk_buff *skb = (struct sk_buff *)buffer->skb;
|
||||
|
||||
EFX_WARN_ON_PARANOID(!pkts_compl || !bytes_compl);
|
||||
(*pkts_compl)++;
|
||||
(*bytes_compl) += skb->len;
|
||||
if (tx_queue->timestamping &&
|
||||
(tx_queue->completed_timestamp_major ||
|
||||
tx_queue->completed_timestamp_minor)) {
|
||||
struct skb_shared_hwtstamps hwtstamp;
|
||||
|
||||
hwtstamp.hwtstamp =
|
||||
efx_ptp_nic_to_kernel_time(tx_queue);
|
||||
skb_tstamp_tx(skb, &hwtstamp);
|
||||
|
||||
tx_queue->completed_timestamp_major = 0;
|
||||
tx_queue->completed_timestamp_minor = 0;
|
||||
}
|
||||
dev_consume_skb_any((struct sk_buff *)buffer->skb);
|
||||
netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
|
||||
"TX queue %d transmission id %x complete\n",
|
||||
tx_queue->queue, tx_queue->read_count);
|
||||
} else if (buffer->flags & EFX_TX_BUF_XDP) {
|
||||
xdp_return_frame_rx_napi(buffer->xdpf);
|
||||
}
|
||||
|
||||
buffer->len = 0;
|
||||
buffer->flags = 0;
|
||||
}
|
||||
|
||||
struct efx_tx_buffer *efx_tx_map_chunk(struct efx_tx_queue *tx_queue,
|
||||
dma_addr_t dma_addr, size_t len)
|
||||
{
|
||||
const struct efx_nic_type *nic_type = tx_queue->efx->type;
|
||||
struct efx_tx_buffer *buffer;
|
||||
unsigned int dma_len;
|
||||
|
||||
/* Map the fragment taking account of NIC-dependent DMA limits. */
|
||||
do {
|
||||
buffer = efx_tx_queue_get_insert_buffer(tx_queue);
|
||||
dma_len = nic_type->tx_limit_len(tx_queue, dma_addr, len);
|
||||
|
||||
buffer->len = dma_len;
|
||||
buffer->dma_addr = dma_addr;
|
||||
buffer->flags = EFX_TX_BUF_CONT;
|
||||
len -= dma_len;
|
||||
dma_addr += dma_len;
|
||||
++tx_queue->insert_count;
|
||||
} while (len);
|
||||
|
||||
return buffer;
|
||||
}
|
||||
|
||||
/* Map all data from an SKB for DMA and create descriptors on the queue. */
|
||||
int efx_tx_map_data(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
|
||||
unsigned int segment_count)
|
||||
{
|
||||
struct efx_nic *efx = tx_queue->efx;
|
||||
struct device *dma_dev = &efx->pci_dev->dev;
|
||||
unsigned int frag_index, nr_frags;
|
||||
dma_addr_t dma_addr, unmap_addr;
|
||||
unsigned short dma_flags;
|
||||
size_t len, unmap_len;
|
||||
|
||||
nr_frags = skb_shinfo(skb)->nr_frags;
|
||||
frag_index = 0;
|
||||
|
||||
/* Map header data. */
|
||||
len = skb_headlen(skb);
|
||||
dma_addr = dma_map_single(dma_dev, skb->data, len, DMA_TO_DEVICE);
|
||||
dma_flags = EFX_TX_BUF_MAP_SINGLE;
|
||||
unmap_len = len;
|
||||
unmap_addr = dma_addr;
|
||||
|
||||
if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
|
||||
return -EIO;
|
||||
|
||||
if (segment_count) {
|
||||
/* For TSO we need to put the header in to a separate
|
||||
* descriptor. Map this separately if necessary.
|
||||
*/
|
||||
size_t header_len = skb_transport_header(skb) - skb->data +
|
||||
(tcp_hdr(skb)->doff << 2u);
|
||||
|
||||
if (header_len != len) {
|
||||
tx_queue->tso_long_headers++;
|
||||
efx_tx_map_chunk(tx_queue, dma_addr, header_len);
|
||||
len -= header_len;
|
||||
dma_addr += header_len;
|
||||
}
|
||||
}
|
||||
|
||||
/* Add descriptors for each fragment. */
|
||||
do {
|
||||
struct efx_tx_buffer *buffer;
|
||||
skb_frag_t *fragment;
|
||||
|
||||
buffer = efx_tx_map_chunk(tx_queue, dma_addr, len);
|
||||
|
||||
/* The final descriptor for a fragment is responsible for
|
||||
* unmapping the whole fragment.
|
||||
*/
|
||||
buffer->flags = EFX_TX_BUF_CONT | dma_flags;
|
||||
buffer->unmap_len = unmap_len;
|
||||
buffer->dma_offset = buffer->dma_addr - unmap_addr;
|
||||
|
||||
if (frag_index >= nr_frags) {
|
||||
/* Store SKB details with the final buffer for
|
||||
* the completion.
|
||||
*/
|
||||
buffer->skb = skb;
|
||||
buffer->flags = EFX_TX_BUF_SKB | dma_flags;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Move on to the next fragment. */
|
||||
fragment = &skb_shinfo(skb)->frags[frag_index++];
|
||||
len = skb_frag_size(fragment);
|
||||
dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len,
|
||||
DMA_TO_DEVICE);
|
||||
dma_flags = 0;
|
||||
unmap_len = len;
|
||||
unmap_addr = dma_addr;
|
||||
|
||||
if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
|
||||
return -EIO;
|
||||
} while (1);
|
||||
}
|
||||
|
||||
unsigned int efx_tx_max_skb_descs(struct efx_nic *efx)
|
||||
{
|
||||
/* Header and payload descriptor for each output segment, plus
|
||||
* one for every input fragment boundary within a segment
|
||||
*/
|
||||
unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS;
|
||||
|
||||
/* Possibly one more per segment for option descriptors */
|
||||
if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
|
||||
max_descs += EFX_TSO_MAX_SEGS;
|
||||
|
||||
/* Possibly more for PCIe page boundaries within input fragments */
|
||||
if (PAGE_SIZE > EFX_PAGE_SIZE)
|
||||
max_descs += max_t(unsigned int, MAX_SKB_FRAGS,
|
||||
DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE));
|
||||
|
||||
return max_descs;
|
||||
}
|
31
drivers/net/ethernet/sfc/tx_common.h
Normal file
31
drivers/net/ethernet/sfc/tx_common.h
Normal file
@ -0,0 +1,31 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/****************************************************************************
|
||||
* Driver for Solarflare network controllers and boards
|
||||
* Copyright 2018 Solarflare Communications Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation, incorporated herein by reference.
|
||||
*/
|
||||
|
||||
#ifndef EFX_TX_COMMON_H
|
||||
#define EFX_TX_COMMON_H
|
||||
|
||||
int efx_probe_tx_queue(struct efx_tx_queue *tx_queue);
|
||||
void efx_init_tx_queue(struct efx_tx_queue *tx_queue);
|
||||
void efx_fini_tx_queue(struct efx_tx_queue *tx_queue);
|
||||
void efx_remove_tx_queue(struct efx_tx_queue *tx_queue);
|
||||
|
||||
void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
|
||||
struct efx_tx_buffer *buffer,
|
||||
unsigned int *pkts_compl,
|
||||
unsigned int *bytes_compl);
|
||||
|
||||
struct efx_tx_buffer *efx_tx_map_chunk(struct efx_tx_queue *tx_queue,
|
||||
dma_addr_t dma_addr, size_t len);
|
||||
int efx_tx_map_data(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
|
||||
unsigned int segment_count);
|
||||
|
||||
unsigned int efx_tx_max_skb_descs(struct efx_nic *efx);
|
||||
|
||||
#endif
|
Loading…
Reference in New Issue
Block a user