mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 10:37:53 +07:00
Ux500 device tree patches for v3.14, take one:
- Fix up tc3589x bindings so this chip works again. - Remove SSP platform devices, as we now boot from device tree exclusively. - Delete surplus AB8500/DB8500 platform data, not obtained from the device tree. - Add DMA config for the MSP devices. - A series of 21 patches moving pin control config for the on-chip Nomadik pin controller from the board file to the device tree, step by step. - Two patches to the STE DMA40 driver regarding the high-prio DMA channel so this can be moved to the device tree. Both have Vinod's ACK. - Decommission of the non-device tree boot path for the timer initialization code. - Deletion of the non-devicetree probe path from the MTU timer driver, as all platforms using it are now using device tree. This has Daniel Lezcano's ACK. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.15 (GNU/Linux) iQIcBAABAgAGBQJSlQIFAAoJEEEQszewGV1zaaoP/iUClda7fps7dhBZMHOaDr48 DAe9yBaUoGBgyjOd0QUUP4/P5PxsXQVCM13gdaITt+R4eg8XYxG3jLNxopMfGKYV bifbXqEd4wf0t8yUYCzhdfAeWchzSph3W2C7I2hW09b9nhJ+RWgXdzcO061E9Tbj BbZ4aS7IR3HfXzQ/zdMBtlbNXkWtn++HXCjC5Z0t0FKqSL7X8LKZrr3GEHZ6vfnB sI5/bTK3AfXt7h2wsu4z/IZK89Ttt9AATNhxajW2Pptkuggc+/KfRRDyYeZFBT70 9KIRsF3NXSsOhOYcRNbWjNU2S8OtC7UyKMB5+y07cYU53ehaiEH8tUMait1cphlc kFJAqKXY87I85E6WTEgv1s4Q8H3rQzVc/IjT3LODFbuM3MeTrsrnbKDeFCOqqpJC 4Ggq6VBXhn7G2srcM5KBYZcZhmq86qhmo0/vUOqaYcdmgdD7KJyewLNafYf5W+DX JxVlnzpdWsAhihUV3oBeJybM0YGvE1wa855ZqbsAZ8nrLTBoTD+zi30mIhXrQwQp v54ywGa0JtjpTLY6EZG2Rptq4qOUVUbkuNSv+3BYgVTqxCcCqXOu+tuzGk2O1jTh 8/2biKCCrdbSWCmbMZDi7jlkO5ywqcn2Brav5KyZ+bCwITRybfoxeOv6f8DCT741 bwx00XNaYVO/H+Vptd+h =w9pg -----END PGP SIGNATURE----- Merge tag 'ux500-devicetree-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt From Linus Walleij: Ux500 device tree patches for v3.14, take one: - Fix up tc3589x bindings so this chip works again. - Remove SSP platform devices, as we now boot from device tree exclusively. - Delete surplus AB8500/DB8500 platform data, not obtained from the device tree. - Add DMA config for the MSP devices. - A series of 21 patches moving pin control config for the on-chip Nomadik pin controller from the board file to the device tree, step by step. - Two patches to the STE DMA40 driver regarding the high-prio DMA channel so this can be moved to the device tree. Both have Vinod's ACK. - Decommission of the non-device tree boot path for the timer initialization code. - Deletion of the non-devicetree probe path from the MTU timer driver, as all platforms using it are now using device tree. This has Daniel Lezcano's ACK. * tag 'ux500-devicetree-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: (39 commits) ARM: ux500: decomission custom SMP TWD timer init clksrc: delete nomadik MTU non-DT boot path ARM: ux500: decomission the non-DT MTU init sequence dma: ste_dma40: Parse flags property for new 'high priority channel' request dma: ste_dma40: Expand DT binding to accept 'high-priority channel' flag ARM: ux500: Remove checking for DT during timer init ARM: ux500: Clean-up legacy extern prototype ARM: ux500: Remove unused call to register AMBA devices ARM: ux500: Clean-up non-DT IRQ initialisation pinctrl: nomadik: decomission non-DT boot path pinctrl: nomadik: move platform data handling into driver ARM: ux500: get rid of unused header ARM: ux500: delete Nomadik pinctrl AUXDATA ARM: ux500: delete remnant pin config macros ARM: ux500: move snowball pin configs to device tree ARM: ux500: move snowball LED pin control to device tree ARM: ux500: convert Snowball SPI pin reference ARM: ux500: move snowball ethernet config to device tree ARM: ux500: move HREFv60plus pin configs to device tree ARM: ux500: move final HREFv60 LCD pins to device tree ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
dab719392a
@ -50,6 +50,9 @@ Each dmas request consists of 4 cells:
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0x00000008: Use fixed channel:
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Use automatic channel selection when unset
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Use DMA request line number when set
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0x00000010: Set channel as high priority:
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Normal priority when unset
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High priority when set
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Example:
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@ -913,6 +913,10 @@ msp0: msp@80123000 {
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interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
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v-ape-supply = <&db8500_vape_reg>;
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dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
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<&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
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dma-names = "rx", "tx";
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clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
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clock-names = "msp", "apb_pclk";
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@ -925,6 +929,9 @@ msp1: msp@80124000 {
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interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
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v-ape-supply = <&db8500_vape_reg>;
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dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
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dma-names = "tx";
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clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
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clock-names = "msp", "apb_pclk";
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@ -938,6 +945,11 @@ msp2: msp@80117000 {
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interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
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v-ape-supply = <&db8500_vape_reg>;
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dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
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<&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
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HighPrio - Fixed */
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dma-names = "rx", "tx";
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clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
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clock-names = "msp", "apb_pclk";
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@ -950,6 +962,9 @@ msp3: msp@80125000 {
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interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
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v-ape-supply = <&db8500_vape_reg>;
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dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
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dma-names = "rx";
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clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
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clock-names = "msp", "apb_pclk";
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@ -987,6 +1002,23 @@ vmmci: regulator-gpio {
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status = "disabled";
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};
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mcde@a0350000 {
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compatible = "stericsson,mcde";
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reg = <0xa0350000 0x1000>, /* MCDE */
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<0xa0351000 0x1000>, /* DSI link 1 */
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<0xa0352000 0x1000>, /* DSI link 2 */
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<0xa0353000 0x1000>; /* DSI link 3 */
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interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
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<&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
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<&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
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<&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
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<&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
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<&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
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<&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
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<&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
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};
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cryp@a03cb000 {
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compatible = "stericsson,ux500-cryp";
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reg = <0xa03cb000 0x1000>;
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745
arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
Normal file
745
arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
Normal file
@ -0,0 +1,745 @@
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/*
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* Copyright 2013 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "ste-nomadik-pinctrl.dtsi"
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/ {
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soc {
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pinctrl {
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/* Settings for all UART default and sleep states */
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uart0 {
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uart0_default_mode: uart0_default {
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default_mux {
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ste,function = "u0";
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ste,pins = "u0_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
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ste,config = <&out_hi>;
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};
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};
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uart0_sleep_mode: uart0_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO1_AJ3"; /* RTS */
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ste,config = <&slpm_out_hi_wkup_pdis>;
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};
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sleep_cfg3 {
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ste,pins = "GPIO3_AH3"; /* TXD */
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ste,config = <&slpm_out_wkup_pdis>;
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};
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};
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};
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uart1 {
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uart1_default_mode: uart1_default {
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default_mux {
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ste,function = "u1";
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ste,pins = "u1rxtx_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO4_AH6"; /* RXD */
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO5_AG6"; /* TXD */
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ste,config = <&out_hi>;
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};
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};
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uart1_sleep_mode: uart1_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO4_AH6"; /* RXD */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO5_AG6"; /* TXD */
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ste,config = <&slpm_out_wkup_pdis>;
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};
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};
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};
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uart2 {
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uart2_default_mode: uart2_default {
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default_mux {
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ste,function = "u2";
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ste,pins = "u2rxtx_c_1";
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};
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default_cfg1 {
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ste,pins = "GPIO29_W2"; /* RXD */
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO30_W3"; /* TXD */
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ste,config = <&out_hi>;
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};
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};
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uart2_sleep_mode: uart2_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO29_W2"; /* RXD */
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ste,config = <&in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO30_W3"; /* TXD */
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ste,config = <&out_wkup_pdis>;
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};
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};
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};
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/* Settings for all I2C default and sleep states */
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i2c0 {
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i2c0_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c0";
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ste,pins = "i2c0_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c0_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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i2c1 {
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i2c1_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c1";
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ste,pins = "i2c1_b_2";
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};
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default_cfg1 {
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ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c1_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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i2c2 {
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i2c2_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c2";
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ste,pins = "i2c2_b_2";
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};
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default_cfg1 {
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ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c2_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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i2c3 {
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i2c3_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c3";
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ste,pins = "i2c3_c_2";
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};
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default_cfg1 {
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ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c3_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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/*
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* Activating I2C4 will conflict with UART1 about the same pins so do not
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* enable I2C4 and UART1 at the same time.
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*/
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i2c4 {
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i2c4_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c4";
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ste,pins = "i2c4_b_1";
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};
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default_cfg1 {
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ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c4_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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/* Settings for all SPI default and sleep states */
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spi2 {
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spi2_default_mode: spi_default {
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default_mux {
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ste,function = "spi2";
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ste,pins = "spi2_oc1_2";
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};
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default_cfg1 {
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ste,pins = "GPIO216_AG12"; /* FRM */
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ste,config = <&gpio_out_hi>;
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};
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default_cfg2 {
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ste,pins = "GPIO218_AH11"; /* RXD */
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ste,config = <&in_pd>;
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};
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default_cfg3 {
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ste,pins =
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"GPIO215_AH13", /* TXD */
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"GPIO217_AH12"; /* CLK */
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ste,config = <&out_lo>;
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};
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};
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spi2_idle_mode: spi_idle {
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/*
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* The idle mode is basically sleep mode sans wakeups. Also
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* note that we have muxes the pins off the function here
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* as we do not state any muxing.
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*/
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idle_cfg1 {
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ste,pins = "GPIO218_AH11"; /* RXD */
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ste,config = <&slpm_in_pdis>;
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};
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idle_cfg2 {
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ste,pins = "GPIO215_AH13"; /* TXD */
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ste,config = <&slpm_out_lo_pdis>;
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};
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idle_cfg3 {
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ste,pins = "GPIO217_AH12"; /* CLK */
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ste,config = <&slpm_pdis>;
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};
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};
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spi2_sleep_mode: spi_sleep {
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sleep_cfg1 {
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ste,pins =
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"GPIO216_AG12", /* FRM */
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"GPIO218_AH11"; /* RXD */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO215_AH13"; /* TXD */
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ste,config = <&slpm_out_lo_wkup_pdis>;
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};
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sleep_cfg3 {
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ste,pins = "GPIO217_AH12"; /* CLK */
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ste,config = <&slpm_wkup_pdis>;
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};
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};
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};
|
||||
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/* Settings for all MMC/SD/SDIO default and sleep states */
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sdi0 {
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/* This is the external SD card slot, 4 bits wide */
|
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sdi0_default_mode: sdi0_default {
|
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default_mux {
|
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ste,function = "mc0";
|
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ste,pins = "mc0_a_1";
|
||||
};
|
||||
default_cfg1 {
|
||||
ste,pins =
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"GPIO18_AC2", /* CMDDIR */
|
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"GPIO19_AC1", /* DAT0DIR */
|
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"GPIO20_AB4"; /* DAT2DIR */
|
||||
ste,config = <&out_hi>;
|
||||
};
|
||||
default_cfg2 {
|
||||
ste,pins = "GPIO22_AA3"; /* FBCLK */
|
||||
ste,config = <&in_nopull>;
|
||||
};
|
||||
default_cfg3 {
|
||||
ste,pins = "GPIO23_AA4"; /* CLK */
|
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ste,config = <&out_lo>;
|
||||
};
|
||||
default_cfg4 {
|
||||
ste,pins =
|
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"GPIO24_AB2", /* CMD */
|
||||
"GPIO25_Y4", /* DAT0 */
|
||||
"GPIO26_Y2", /* DAT1 */
|
||||
"GPIO27_AA2", /* DAT2 */
|
||||
"GPIO28_AA1"; /* DAT3 */
|
||||
ste,config = <&in_pu>;
|
||||
};
|
||||
};
|
||||
|
||||
sdi0_sleep_mode: sdi0_sleep {
|
||||
sleep_cfg1 {
|
||||
ste,pins =
|
||||
"GPIO18_AC2", /* CMDDIR */
|
||||
"GPIO19_AC1", /* DAT0DIR */
|
||||
"GPIO20_AB4"; /* DAT2DIR */
|
||||
ste,config = <&slpm_out_hi_wkup_pdis>;
|
||||
};
|
||||
sleep_cfg2 {
|
||||
ste,pins =
|
||||
"GPIO22_AA3", /* FBCLK */
|
||||
"GPIO24_AB2", /* CMD */
|
||||
"GPIO25_Y4", /* DAT0 */
|
||||
"GPIO26_Y2", /* DAT1 */
|
||||
"GPIO27_AA2", /* DAT2 */
|
||||
"GPIO28_AA1"; /* DAT3 */
|
||||
ste,config = <&slpm_in_wkup_pdis>;
|
||||
};
|
||||
sleep_cfg3 {
|
||||
ste,pins = "GPIO23_AA4"; /* CLK */
|
||||
ste,config = <&slpm_out_lo_wkup_pdis>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdi1 {
|
||||
/* This is the WLAN SDIO 4 bits wide */
|
||||
sdi1_default_mode: sdi1_default {
|
||||
default_mux {
|
||||
ste,function = "mc1";
|
||||
ste,pins = "mc1_a_1";
|
||||
};
|
||||
default_cfg1 {
|
||||
ste,pins = "GPIO208_AH16"; /* CLK */
|
||||
ste,config = <&out_lo>;
|
||||
};
|
||||
default_cfg2 {
|
||||
ste,pins = "GPIO209_AG15"; /* FBCLK */
|
||||
ste,config = <&in_nopull>;
|
||||
};
|
||||
default_cfg3 {
|
||||
ste,pins =
|
||||
"GPIO210_AJ15", /* CMD */
|
||||
"GPIO211_AG14", /* DAT0 */
|
||||
"GPIO212_AF13", /* DAT1 */
|
||||
"GPIO213_AG13", /* DAT2 */
|
||||
"GPIO214_AH15"; /* DAT3 */
|
||||
ste,config = <&in_pu>;
|
||||
};
|
||||
};
|
||||
|
||||
sdi1_sleep_mode: sdi1_sleep {
|
||||
sleep_cfg1 {
|
||||
ste,pins = "GPIO208_AH16"; /* CLK */
|
||||
ste,config = <&slpm_out_lo_wkup_pdis>;
|
||||
};
|
||||
sleep_cfg2 {
|
||||
ste,pins =
|
||||
"GPIO209_AG15", /* FBCLK */
|
||||
"GPIO210_AJ15", /* CMD */
|
||||
"GPIO211_AG14", /* DAT0 */
|
||||
"GPIO212_AF13", /* DAT1 */
|
||||
"GPIO213_AG13", /* DAT2 */
|
||||
"GPIO214_AH15"; /* DAT3 */
|
||||
ste,config = <&slpm_in_wkup_pdis>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdi2 {
|
||||
/* This is the eMMC 8 bits wide, usually PoP eMMC */
|
||||
sdi2_default_mode: sdi2_default {
|
||||
default_mux {
|
||||
ste,function = "mc2";
|
||||
ste,pins = "mc2_a_1";
|
||||
};
|
||||
default_cfg1 {
|
||||
ste,pins = "GPIO128_A5"; /* CLK */
|
||||
ste,config = <&out_lo>;
|
||||
};
|
||||
default_cfg2 {
|
||||
ste,pins = "GPIO130_C8"; /* FBCLK */
|
||||
ste,config = <&in_nopull>;
|
||||
};
|
||||
default_cfg3 {
|
||||
ste,pins =
|
||||
"GPIO129_B4", /* CMD */
|
||||
"GPIO131_A12", /* DAT0 */
|
||||
"GPIO132_C10", /* DAT1 */
|
||||
"GPIO133_B10", /* DAT2 */
|
||||
"GPIO134_B9", /* DAT3 */
|
||||
"GPIO135_A9", /* DAT4 */
|
||||
"GPIO136_C7", /* DAT5 */
|
||||
"GPIO137_A7", /* DAT6 */
|
||||
"GPIO138_C5"; /* DAT7 */
|
||||
ste,config = <&in_pu>;
|
||||
};
|
||||
};
|
||||
|
||||
sdi2_sleep_mode: sdi2_sleep {
|
||||
sleep_cfg1 {
|
||||
ste,pins = "GPIO128_A5"; /* CLK */
|
||||
ste,config = <&out_lo_wkup_pdis>;
|
||||
};
|
||||
sleep_cfg2 {
|
||||
ste,pins =
|
||||
"GPIO130_C8", /* FBCLK */
|
||||
"GPIO129_B4"; /* CMD */
|
||||
ste,config = <&in_wkup_pdis_en>;
|
||||
};
|
||||
sleep_cfg3 {
|
||||
ste,pins =
|
||||
"GPIO131_A12", /* DAT0 */
|
||||
"GPIO132_C10", /* DAT1 */
|
||||
"GPIO133_B10", /* DAT2 */
|
||||
"GPIO134_B9", /* DAT3 */
|
||||
"GPIO135_A9", /* DAT4 */
|
||||
"GPIO136_C7", /* DAT5 */
|
||||
"GPIO137_A7", /* DAT6 */
|
||||
"GPIO138_C5"; /* DAT7 */
|
||||
ste,config = <&in_wkup_pdis>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdi4 {
|
||||
/* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
|
||||
sdi4_default_mode: sdi4_default {
|
||||
default_mux {
|
||||
ste,function = "mc4";
|
||||
ste,pins = "mc4_a_1";
|
||||
};
|
||||
default_cfg1 {
|
||||
ste,pins = "GPIO203_AE23"; /* CLK */
|
||||
ste,config = <&out_lo>;
|
||||
};
|
||||
default_cfg2 {
|
||||
ste,pins = "GPIO202_AF25"; /* FBCLK */
|
||||
ste,config = <&in_nopull>;
|
||||
};
|
||||
default_cfg3 {
|
||||
ste,pins =
|
||||
"GPIO201_AF24", /* CMD */
|
||||
"GPIO200_AH26", /* DAT0 */
|
||||
"GPIO199_AH23", /* DAT1 */
|
||||
"GPIO198_AG25", /* DAT2 */
|
||||
"GPIO197_AH24", /* DAT3 */
|
||||
"GPIO207_AJ23", /* DAT4 */
|
||||
"GPIO206_AG24", /* DAT5 */
|
||||
"GPIO205_AG23", /* DAT6 */
|
||||
"GPIO204_AF23"; /* DAT7 */
|
||||
ste,config = <&in_pu>;
|
||||
};
|
||||
};
|
||||
|
||||
sdi4_sleep_mode: sdi4_sleep {
|
||||
sleep_cfg1 {
|
||||
ste,pins = "GPIO203_AE23"; /* CLK */
|
||||
ste,config = <&out_lo_wkup_pdis>;
|
||||
};
|
||||
sleep_cfg2 {
|
||||
ste,pins =
|
||||
"GPIO202_AF25", /* FBCLK */
|
||||
"GPIO201_AF24", /* CMD */
|
||||
"GPIO200_AH26", /* DAT0 */
|
||||
"GPIO199_AH23", /* DAT1 */
|
||||
"GPIO198_AG25", /* DAT2 */
|
||||
"GPIO197_AH24", /* DAT3 */
|
||||
"GPIO207_AJ23", /* DAT4 */
|
||||
"GPIO206_AG24", /* DAT5 */
|
||||
"GPIO205_AG23", /* DAT6 */
|
||||
"GPIO204_AF23"; /* DAT7 */
|
||||
ste,config = <&slpm_in_wkup_pdis>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Multi-rate serial ports (MSPs) - MSP3 output is internal and
|
||||
* cannot be muxed onto any pins.
|
||||
*/
|
||||
msp0 {
|
||||
msp0_default_mode: msp0_default {
|
||||
default_msp0_mux {
|
||||
ste,function = "msp0";
|
||||
ste,pins = "msp0txrx_a_1", "msp0tfstck_a_1";
|
||||
};
|
||||
default_msp0_cfg {
|
||||
ste,pins =
|
||||
"GPIO12_AC4", /* TXD */
|
||||
"GPIO15_AC3", /* RXD */
|
||||
"GPIO13_AF3", /* TFS */
|
||||
"GPIO14_AE3"; /* TCK */
|
||||
ste,config = <&in_nopull>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
msp1 {
|
||||
msp1_default_mode: msp1_default {
|
||||
default_mux {
|
||||
ste,function = "msp1";
|
||||
ste,pins = "msp1txrx_a_1", "msp1_a_1";
|
||||
};
|
||||
default_cfg1 {
|
||||
ste,pins = "GPIO33_AF2";
|
||||
ste,config = <&out_lo>;
|
||||
};
|
||||
default_cfg2 {
|
||||
ste,pins =
|
||||
"GPIO34_AE1",
|
||||
"GPIO35_AE2",
|
||||
"GPIO36_AG2";
|
||||
ste,config = <&in_nopull>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
msp2 {
|
||||
msp2_default_mode: msp2_default {
|
||||
/* MSP2 usually used for HDMI audio */
|
||||
default_mux {
|
||||
ste,function = "msp2";
|
||||
ste,pins = "msp2_a_1";
|
||||
};
|
||||
default_cfg1 {
|
||||
ste,pins =
|
||||
"GPIO193_AH27", /* TXD */
|
||||
"GPIO194_AF27", /* TCK */
|
||||
"GPIO195_AG28"; /* TFS */
|
||||
ste,config = <&in_pd>;
|
||||
};
|
||||
default_cfg2 {
|
||||
ste,pins = "GPIO196_AG26"; /* RXD */
|
||||
ste,config = <&out_lo>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
musb {
|
||||
musb_default_mode: musb_default {
|
||||
default_mux {
|
||||
ste,function = "usb";
|
||||
ste,pins = "usb_a_1";
|
||||
};
|
||||
default_cfg1 {
|
||||
ste,pins =
|
||||
"GPIO256_AF28", /* NXT */
|
||||
"GPIO258_AD29", /* XCLK */
|
||||
"GPIO259_AC29", /* DIR */
|
||||
"GPIO260_AD28", /* DAT7 */
|
||||
"GPIO261_AD26", /* DAT6 */
|
||||
"GPIO262_AE26", /* DAT5 */
|
||||
"GPIO263_AG29", /* DAT4 */
|
||||
"GPIO264_AE27", /* DAT3 */
|
||||
"GPIO265_AD27", /* DAT2 */
|
||||
"GPIO266_AC28", /* DAT1 */
|
||||
"GPIO267_AC27"; /* DAT0 */
|
||||
ste,config = <&in_nopull>;
|
||||
};
|
||||
default_cfg2 {
|
||||
ste,pins = "GPIO257_AE29"; /* STP */
|
||||
ste,config = <&out_hi>;
|
||||
};
|
||||
};
|
||||
|
||||
musb_sleep_mode: musb_sleep {
|
||||
sleep_cfg1 {
|
||||
ste,pins =
|
||||
"GPIO256_AF28", /* NXT */
|
||||
"GPIO258_AD29", /* XCLK */
|
||||
"GPIO259_AC29"; /* DIR */
|
||||
ste,config = <&slpm_wkup_pdis_en>;
|
||||
};
|
||||
sleep_cfg2 {
|
||||
ste,pins = "GPIO257_AE29"; /* STP */
|
||||
ste,config = <&slpm_out_hi_wkup_pdis>;
|
||||
};
|
||||
sleep_cfg3 {
|
||||
ste,pins =
|
||||
"GPIO260_AD28", /* DAT7 */
|
||||
"GPIO261_AD26", /* DAT6 */
|
||||
"GPIO262_AE26", /* DAT5 */
|
||||
"GPIO263_AG29", /* DAT4 */
|
||||
"GPIO264_AE27", /* DAT3 */
|
||||
"GPIO265_AD27", /* DAT2 */
|
||||
"GPIO266_AC28", /* DAT1 */
|
||||
"GPIO267_AC27"; /* DAT0 */
|
||||
ste,config = <&slpm_in_wkup_pdis_en>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mcde {
|
||||
lcd_default_mode: lcd_default {
|
||||
default_mux {
|
||||
/* Mux in VSI0 and all the data lines */
|
||||
ste,function = "lcd";
|
||||
ste,pins =
|
||||
"lcdvsi0_a_1", /* VSI0 for LCD */
|
||||
"lcd_d0_d7_a_1", /* Data lines */
|
||||
"lcd_d8_d11_a_1", /* TV-out */
|
||||
"lcdaclk_b_1", /* Clock line for TV-out */
|
||||
"lcdvsi1_a_1"; /* VSI1 for HDMI */
|
||||
};
|
||||
default_cfg1 {
|
||||
ste,pins =
|
||||
"GPIO68_E1", /* VSI0 */
|
||||
"GPIO69_E2"; /* VSI1 */
|
||||
ste,config = <&in_pu>;
|
||||
};
|
||||
};
|
||||
lcd_sleep_mode: lcd_sleep {
|
||||
sleep_cfg1 {
|
||||
ste,pins = "GPIO69_E2"; /* VSI1 */
|
||||
ste,config = <&slpm_in_wkup_pdis>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ske {
|
||||
/* SKE keys on position 2 in an 8x8 matrix */
|
||||
ske_kpa2_default_mode: ske_kpa2_default {
|
||||
default_mux {
|
||||
ste,function = "kp";
|
||||
ste,pins = "kp_a_2";
|
||||
};
|
||||
default_cfg1 {
|
||||
ste,pins =
|
||||
"GPIO153_B17", /* I7 */
|
||||
"GPIO154_C16", /* I6 */
|
||||
"GPIO155_C19", /* I5 */
|
||||
"GPIO156_C17", /* I4 */
|
||||
"GPIO161_D21", /* I3 */
|
||||
"GPIO162_D20", /* I2 */
|
||||
"GPIO163_C20", /* I1 */
|
||||
"GPIO164_B21"; /* I0 */
|
||||
ste,config = <&in_pd>;
|
||||
};
|
||||
default_cfg2 {
|
||||
ste,pins =
|
||||
"GPIO157_A18", /* O7 */
|
||||
"GPIO158_C18", /* O6 */
|
||||
"GPIO159_B19", /* O5 */
|
||||
"GPIO160_B20", /* O4 */
|
||||
"GPIO165_C21", /* O3 */
|
||||
"GPIO166_A22", /* O2 */
|
||||
"GPIO167_B24", /* O1 */
|
||||
"GPIO168_C22"; /* O0 */
|
||||
ste,config = <&out_lo>;
|
||||
};
|
||||
};
|
||||
ske_kpa2_sleep_mode: ske_kpa2_sleep {
|
||||
sleep_cfg1 {
|
||||
ste,pins =
|
||||
"GPIO153_B17", /* I7 */
|
||||
"GPIO154_C16", /* I6 */
|
||||
"GPIO155_C19", /* I5 */
|
||||
"GPIO156_C17", /* I4 */
|
||||
"GPIO161_D21", /* I3 */
|
||||
"GPIO162_D20", /* I2 */
|
||||
"GPIO163_C20", /* I1 */
|
||||
"GPIO164_B21"; /* I0 */
|
||||
ste,config = <&slpm_in_pu_wkup_pdis_en>;
|
||||
};
|
||||
sleep_cfg2 {
|
||||
ste,pins =
|
||||
"GPIO157_A18", /* O7 */
|
||||
"GPIO158_C18", /* O6 */
|
||||
"GPIO159_B19", /* O5 */
|
||||
"GPIO160_B20", /* O4 */
|
||||
"GPIO165_C21", /* O3 */
|
||||
"GPIO166_A22", /* O2 */
|
||||
"GPIO167_B24", /* O1 */
|
||||
"GPIO168_C22"; /* O0 */
|
||||
ste,config = <&slpm_out_lo_pdis>;
|
||||
};
|
||||
};
|
||||
/*
|
||||
* SKE keys on position 1 and "other C1" combi giving
|
||||
* six rows of six keys.
|
||||
*/
|
||||
ske_kpaoc1_default_mode: ske_kpaoc1_default {
|
||||
default_mux {
|
||||
ste,function = "kp";
|
||||
ste,pins = "kp_a_1", "kp_oc1_1";
|
||||
};
|
||||
default_cfg1 {
|
||||
ste,pins =
|
||||
"GPIO91_B6", /* KP_O0 */
|
||||
"GPIO90_A3", /* KP_O1 */
|
||||
"GPIO87_B3", /* KP_O2 */
|
||||
"GPIO86_C6", /* KP_O3 */
|
||||
"GPIO96_D8", /* KP_O6 */
|
||||
"GPIO94_D7"; /* KP_O7 */
|
||||
ste,config = <&out_lo>;
|
||||
};
|
||||
default_cfg2 {
|
||||
ste,pins =
|
||||
"GPIO93_B7", /* KP_I0 */
|
||||
"GPIO92_D6", /* KP_I1 */
|
||||
"GPIO89_E6", /* KP_I2 */
|
||||
"GPIO88_C4", /* KP_I3 */
|
||||
"GPIO97_D9", /* KP_I6 */
|
||||
"GPIO95_E8"; /* KP_I7 */
|
||||
ste,config = <&in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wlan {
|
||||
wlan_default_mode: wlan_default {
|
||||
/*
|
||||
* Activate this mode with the WLAN chip.
|
||||
* These are plain GPIO pins used by WLAN
|
||||
*/
|
||||
default_cfg1 {
|
||||
ste,pins =
|
||||
"GPIO226_AF8", /* WLAN_PMU_EN */
|
||||
"GPIO85_D5"; /* WLAN_ENA */
|
||||
ste,config = <&gpio_out_lo>;
|
||||
};
|
||||
default_cfg2 {
|
||||
ste,pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -12,6 +12,28 @@
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
vdd-supply = <&ab8500_ldo_aux1_reg>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&prox_stuib_mode>, <&hall_stuib_mode>;
|
||||
|
||||
button@139 {
|
||||
/* Proximity sensor */
|
||||
gpios = <&gpio6 25 0x4>;
|
||||
linux,code = <11>; /* SW_FRONT_PROXIMITY */
|
||||
label = "SFH7741 Proximity Sensor";
|
||||
};
|
||||
button@145 {
|
||||
/* Hall sensor */
|
||||
gpios = <&gpio4 17 0x4>;
|
||||
linux,code = <0>; /* SW_LID */
|
||||
label = "HED54XXU11 Hall Effect Sensor";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
i2c@80004000 {
|
||||
stmpe1601: stmpe1601@40 {
|
||||
@ -74,5 +96,24 @@ bu21013_tp@5d {
|
||||
rohm,flip-y;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
prox {
|
||||
prox_stuib_mode: prox_stuib {
|
||||
stuib_cfg {
|
||||
ste,pins = "GPIO217_AH12";
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
hall {
|
||||
hall_stuib_mode: stuib_tvk {
|
||||
stuib_cfg {
|
||||
ste,pins = "GPIO145_C13";
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -14,27 +14,105 @@
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
vdd-supply = <&ab8500_ldo_aux1_reg>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>;
|
||||
|
||||
button@139 {
|
||||
/* Proximity sensor */
|
||||
gpios = <&gpio6 25 0x4>;
|
||||
linux,code = <11>; /* SW_FRONT_PROXIMITY */
|
||||
label = "SFH7741 Proximity Sensor";
|
||||
};
|
||||
button@145 {
|
||||
/* Hall sensor */
|
||||
gpios = <&gpio4 17 0x4>;
|
||||
linux,code = <0>; /* SW_LID */
|
||||
label = "HED54XXU11 Hall Effect Sensor";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/* Add Synaptics touch screen, TC35892 keypad etc here */
|
||||
/* Add Synaptics touch screen, TC35893 keypad etc here */
|
||||
i2c@80004000 {
|
||||
tc3589x@44 {
|
||||
compatible = "tc3589x";
|
||||
tc35893@44 {
|
||||
compatible = "toshiba,tc35893";
|
||||
reg = <0x44>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <26 IRQ_TYPE_EDGE_RISING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tc35893_tvk_mode>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
tc3589x_gpio {
|
||||
compatible = "tc3589x-gpio";
|
||||
interrupts = <0 IRQ_TYPE_EDGE_RISING>;
|
||||
compatible = "toshiba,tc3589x-gpio";
|
||||
interrupts = <0>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
tc3589x_keypad {
|
||||
compatible = "toshiba,tc3589x-keypad";
|
||||
interrupts = <6>;
|
||||
debounce-delay-ms = <4>;
|
||||
keypad,num-columns = <8>;
|
||||
keypad,num-rows = <8>;
|
||||
linux,no-autorepeat;
|
||||
linux,wakeup;
|
||||
linux,keymap = <0x0301006b
|
||||
0x04010066
|
||||
0x06040072
|
||||
0x040200d7
|
||||
0x0303006a
|
||||
0x0205000e
|
||||
0x0607008b
|
||||
0x0500001c
|
||||
0x0403000b
|
||||
0x03040034
|
||||
0x05020067
|
||||
0x0305006c
|
||||
0x040500e7
|
||||
0x0005009e
|
||||
0x06020073
|
||||
0x01030039
|
||||
0x07060069
|
||||
0x050500d9>;
|
||||
};
|
||||
};
|
||||
};
|
||||
pinctrl {
|
||||
/* Pull up this GPIO pin */
|
||||
tc35893 {
|
||||
tc35893_tvk_mode: tc35893_tvk {
|
||||
tvk_cfg {
|
||||
ste,pins = "GPIO218_AH11";
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
prox {
|
||||
prox_tvk_mode: prox_tvk {
|
||||
tvk_cfg {
|
||||
ste,pins = "GPIO217_AH12";
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
hall {
|
||||
hall_tvk_mode: hall_tvk {
|
||||
tvk_cfg {
|
||||
ste,pins = "GPIO145_C13";
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -11,37 +11,57 @@
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "ste-dbx5x0.dtsi"
|
||||
#include "ste-href-family-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
button@1 {
|
||||
linux,code = <11>;
|
||||
label = "SFH7741 Proximity Sensor";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
usb_per5@a03e0000 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&musb_default_mode>;
|
||||
pinctrl-1 = <&musb_sleep_mode>;
|
||||
};
|
||||
|
||||
uart@80120000 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&uart0_default_mode>;
|
||||
pinctrl-1 = <&uart0_sleep_mode>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart@80121000 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&uart1_default_mode>;
|
||||
pinctrl-1 = <&uart1_sleep_mode>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart@80007000 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&uart2_default_mode>;
|
||||
pinctrl-1 = <&uart2_sleep_mode>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@80004000 {
|
||||
pinctrl-names = "default","sleep";
|
||||
pinctrl-0 = <&i2c0_default_mode>;
|
||||
pinctrl-1 = <&i2c0_sleep_mode>;
|
||||
};
|
||||
|
||||
i2c@80122000 {
|
||||
pinctrl-names = "default","sleep";
|
||||
pinctrl-0 = <&i2c1_default_mode>;
|
||||
pinctrl-1 = <&i2c1_sleep_mode>;
|
||||
};
|
||||
|
||||
i2c@80128000 {
|
||||
pinctrl-names = "default","sleep";
|
||||
pinctrl-0 = <&i2c2_default_mode>;
|
||||
pinctrl-1 = <&i2c2_sleep_mode>;
|
||||
lp5521@33 {
|
||||
compatible = "national,lp5521";
|
||||
reg = <0x33>;
|
||||
@ -85,6 +105,12 @@ bh1780@29 {
|
||||
};
|
||||
};
|
||||
|
||||
i2c@80110000 {
|
||||
pinctrl-names = "default","sleep";
|
||||
pinctrl-0 = <&i2c3_default_mode>;
|
||||
pinctrl-1 = <&i2c3_sleep_mode>;
|
||||
};
|
||||
|
||||
// External Micro SD slot
|
||||
sdi0_per1@80126000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
@ -94,6 +120,9 @@ sdi0_per1@80126000 {
|
||||
mmc-cap-mmc-highspeed;
|
||||
vmmc-supply = <&ab8500_ldo_aux3_reg>;
|
||||
vqmmc-supply = <&vmmci>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdi0_default_mode>;
|
||||
pinctrl-1 = <&sdi0_sleep_mode>;
|
||||
|
||||
cd-gpios = <&tc3589x_gpio 3 0x4>;
|
||||
|
||||
@ -105,6 +134,9 @@ sdi1_per2@80118000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
max-frequency = <100000000>;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdi1_default_mode>;
|
||||
pinctrl-1 = <&sdi1_sleep_mode>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
@ -115,6 +147,9 @@ sdi2_per3@80005000 {
|
||||
max-frequency = <100000000>;
|
||||
bus-width = <8>;
|
||||
mmc-cap-mmc-highspeed;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdi2_default_mode>;
|
||||
pinctrl-1 = <&sdi2_sleep_mode>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
@ -126,6 +161,9 @@ sdi4_per2@80114000 {
|
||||
bus-width = <8>;
|
||||
mmc-cap-mmc-highspeed;
|
||||
vmmc-supply = <&ab8500_ldo_aux2_reg>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdi4_default_mode>;
|
||||
pinctrl-1 = <&sdi4_sleep_mode>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
@ -137,7 +175,21 @@ sound {
|
||||
stericsson,audio-codec = <&codec>;
|
||||
};
|
||||
|
||||
msp0: msp@80123000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&msp0_default_mode>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
msp1: msp@80124000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&msp1_default_mode>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
msp2: msp@80117000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&msp2_default_mode>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -198,5 +250,11 @@ ab8500_ldo_ana_reg: ab8500_ldo_ana {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mcde@a0350000 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&lcd_default_mode>;
|
||||
pinctrl-1 = <&lcd_sleep_mode>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -28,18 +28,20 @@ tps61052@33 {
|
||||
reg = <0x33>;
|
||||
};
|
||||
|
||||
tc3589x@42 {
|
||||
compatible = "tc3589x";
|
||||
tc35892@42 {
|
||||
compatible = "toshiba,tc35892";
|
||||
reg = <0x42>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tc35892_hrefprev60_mode>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
tc3589x_gpio: tc3589x_gpio {
|
||||
compatible = "tc3589x-gpio";
|
||||
interrupts = <0 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <0>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
@ -49,11 +51,74 @@ tc3589x_gpio: tc3589x_gpio {
|
||||
};
|
||||
};
|
||||
|
||||
ssp@80002000 {
|
||||
/*
|
||||
* On the first generation boards, this SSP/SPI port was connected
|
||||
* to the AB8500.
|
||||
*/
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ssp0_hrefprev60_mode>;
|
||||
};
|
||||
|
||||
vmmci: regulator-gpio {
|
||||
gpios = <&tc3589x_gpio 18 0x4>;
|
||||
enable-gpio = <&tc3589x_gpio 17 0x4>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
/* Set this up using hogs */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ipgpio_hrefprev60_mode>;
|
||||
|
||||
ssp0 {
|
||||
ssp0_hrefprev60_mode: ssp0_hrefprev60_default {
|
||||
hrefprev60_mux {
|
||||
ste,function = "ssp0";
|
||||
ste,pins = "ssp0_a_1";
|
||||
};
|
||||
hrefprev60_cfg1 {
|
||||
ste,pins = "GPIO145_C13"; /* RXD */
|
||||
ste,config = <&in_pd>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
sdi0 {
|
||||
/* This additional pin needed on early MOP500 and HREFs previous to v60 */
|
||||
sdi0_default_mode: sdi0_default {
|
||||
hrefprev60_mux {
|
||||
ste,function = "mc0";
|
||||
ste,pins = "mc0dat31dir_a_1";
|
||||
};
|
||||
hrefprev60_cfg1 {
|
||||
ste,pins = "GPIO21_AB3"; /* DAT31DIR */
|
||||
ste,config = <&out_hi>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
tc35892 {
|
||||
tc35892_hrefprev60_mode: tc35892_hrefprev60 {
|
||||
hrefprev60_cfg {
|
||||
ste,pins = "GPIO217_AH12";
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
ipgpio {
|
||||
ipgpio_hrefprev60_mode: ipgpio_hrefprev60 {
|
||||
hrefprev60_mux {
|
||||
ste,function = "ipgpio";
|
||||
ste,pins = "ipgpio0_c_1", "ipgpio1_c_1";
|
||||
};
|
||||
hrefprev60_cfg1 {
|
||||
ste,pins = "GPIO6_AF6", "GPIO7_AG5";
|
||||
ste,config = <&in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -16,12 +16,6 @@ / {
|
||||
model = "ST-Ericsson HREF (v60+) platform with Device Tree";
|
||||
compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
|
||||
|
||||
gpio_keys {
|
||||
button@1 {
|
||||
gpios = <&gpio5 25 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
// External Micro SD slot
|
||||
sdi0_per1@80126000 {
|
||||
@ -66,5 +60,216 @@ sdi4_per2@80114000 {
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
/*
|
||||
* Set this up using hogs, as time goes by and as seems fit, these
|
||||
* can be moved over to being controlled by respective device.
|
||||
*/
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ipgpio_hrefv60_mode>,
|
||||
<&accel_hrefv60_mode>,
|
||||
<&magneto_hrefv60_mode>,
|
||||
<&etm_hrefv60_mode>,
|
||||
<&nahj_hrefv60_mode>,
|
||||
<&nfc_hrefv60_mode>,
|
||||
<&force_hrefv60_mode>,
|
||||
<&dipro_hrefv60_mode>,
|
||||
<&vaudio_hf_hrefv60_mode>,
|
||||
<&gbf_hrefv60_mode>,
|
||||
<&hdtv_hrefv60_mode>,
|
||||
<&touch_hrefv60_mode>;
|
||||
|
||||
sdi0 {
|
||||
/* SD card detect GPIO pin, extend default state */
|
||||
sdi0_default_mode: sdi0_default {
|
||||
default_hrefv60_cfg1 {
|
||||
ste,pins = "GPIO95_E8";
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
ipgpio {
|
||||
/*
|
||||
* XENON Flashgun on image processor GPIO (controlled from image
|
||||
* processor firmware), mux in these image processor GPIO lines 0
|
||||
* (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
|
||||
* LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
|
||||
* from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
|
||||
*/
|
||||
ipgpio_hrefv60_mode: ipgpio_hrefv60 {
|
||||
hrefv60_mux {
|
||||
ste,function = "ipgpio";
|
||||
ste,pins = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
|
||||
};
|
||||
hrefv60_cfg1 {
|
||||
ste,pins = "GPIO6_AF6", "GPIO7_AG5";
|
||||
ste,config = <&in_pu>;
|
||||
};
|
||||
hrefv60_cfg2 {
|
||||
ste,pins = "GPIO21_AB3";
|
||||
ste,config = <&gpio_out_lo>;
|
||||
};
|
||||
hrefv60_cfg3 {
|
||||
ste,pins = "GPIO64_F3";
|
||||
ste,config = <&out_lo>;
|
||||
};
|
||||
};
|
||||
};
|
||||
accelerometer {
|
||||
accel_hrefv60_mode: accel_hrefv60 {
|
||||
/* Accelerometer interrupt lines 1 & 2 */
|
||||
hrefv60_cfg1 {
|
||||
ste,pins = "GPIO82_C1", "GPIO83_D3";
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
magnetometer {
|
||||
magneto_hrefv60_mode: magneto_hrefv60 {
|
||||
/* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
|
||||
hrefv60_cfg1 {
|
||||
ste,pins = "GPIO31_V3";
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
hrefv60_cfg2 {
|
||||
ste,pins = "GPIO32_V2";
|
||||
ste,config = <&gpio_in_pd>;
|
||||
};
|
||||
};
|
||||
};
|
||||
etm {
|
||||
/*
|
||||
* Drive D19-D23 for the ETM PTM trace interface low,
|
||||
* (presumably pins are unconnected therefore grounded here,
|
||||
* the "other alt C1" setting enables these pins)
|
||||
*/
|
||||
etm_hrefv60_mode: etm_hrefv60 {
|
||||
hrefv60_cfg1 {
|
||||
ste,pins =
|
||||
"GPIO70_G5",
|
||||
"GPIO71_G4",
|
||||
"GPIO72_H4",
|
||||
"GPIO73_H3",
|
||||
"GPIO74_J3";
|
||||
ste,config = <&gpio_out_lo>;
|
||||
};
|
||||
};
|
||||
};
|
||||
nahj {
|
||||
nahj_hrefv60_mode: nahj_hrefv60 {
|
||||
/* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */
|
||||
hrefv60_cfg1 {
|
||||
ste,pins = "GPIO76_J2";
|
||||
ste,config = <&gpio_out_lo>;
|
||||
};
|
||||
hrefv60_cfg2 {
|
||||
ste,pins = "GPIO216_AG12";
|
||||
ste,config = <&gpio_out_hi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
nfc {
|
||||
nfc_hrefv60_mode: nfc_hrefv60 {
|
||||
/* NFC ENA and RESET to low, pulldown IRQ line */
|
||||
hrefv60_cfg1 {
|
||||
ste,pins =
|
||||
"GPIO77_H1", /* NFC_ENA */
|
||||
"GPIO142_C11"; /* NFC_RESET */
|
||||
ste,config = <&gpio_out_lo>;
|
||||
};
|
||||
hrefv60_cfg2 {
|
||||
ste,pins = "GPIO144_B13"; /* NFC_IRQ */
|
||||
ste,config = <&gpio_in_pd>;
|
||||
};
|
||||
};
|
||||
};
|
||||
force {
|
||||
force_hrefv60_mode: force_hrefv60 {
|
||||
hrefv60_cfg1 {
|
||||
ste,pins = "GPIO91_B6"; /* FORCE_SENSING_INT */
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
hrefv60_cfg2 {
|
||||
ste,pins =
|
||||
"GPIO92_D6", /* FORCE_SENSING_RST */
|
||||
"GPIO97_D9"; /* FORCE_SENSING_WU */
|
||||
ste,config = <&gpio_out_lo>;
|
||||
};
|
||||
};
|
||||
};
|
||||
dipro {
|
||||
dipro_hrefv60_mode: dipro_hrefv60 {
|
||||
hrefv60_cfg1 {
|
||||
ste,pins = "GPIO139_C9"; /* DIPRO_INT */
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
vaudio_hf {
|
||||
vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 {
|
||||
/* Audio Amplifier HF enable GPIO */
|
||||
hrefv60_cfg1 {
|
||||
ste,pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */
|
||||
ste,config = <&gpio_out_hi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
gbf {
|
||||
gbf_hrefv60_mode: gbf_hrefv60 {
|
||||
/*
|
||||
* GBF (GPS, Bluetooth, FM-radio) interface,
|
||||
* pull low to reset state
|
||||
*/
|
||||
hrefv60_cfg1 {
|
||||
ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */
|
||||
ste,config = <&gpio_out_lo>;
|
||||
};
|
||||
};
|
||||
};
|
||||
hdtv {
|
||||
hdtv_hrefv60_mode: hdtv_hrefv60 {
|
||||
/* MSP : HDTV INTERFACE GPIO line */
|
||||
hrefv60_cfg1 {
|
||||
ste,pins = "GPIO192_AJ27";
|
||||
ste,config = <&gpio_in_pd>;
|
||||
};
|
||||
};
|
||||
};
|
||||
touch {
|
||||
touch_hrefv60_mode: touch_hrefv60 {
|
||||
/*
|
||||
* Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
|
||||
* GPIO 67 for interrupts. Pull-up the IRQ line and drive both
|
||||
* reset signals low.
|
||||
*/
|
||||
hrefv60_cfg1 {
|
||||
ste,pins = "GPIO143_D12", "GPIO146_D13";
|
||||
ste,config = <&gpio_out_lo>;
|
||||
};
|
||||
hrefv60_cfg2 {
|
||||
ste,pins = "GPIO67_G2";
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
mcde {
|
||||
lcd_hrefv60_mode: lcd_hrefv60 {
|
||||
/*
|
||||
* Display Interface 1 uses GPIO 65 for RST (reset).
|
||||
* Display Interface 2 uses GPIO 66 for RST (reset).
|
||||
* Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
|
||||
*/
|
||||
hrefv60_cfg1 {
|
||||
ste,pins ="GPIO65_F1";
|
||||
ste,config = <&gpio_out_hi>;
|
||||
};
|
||||
hrefv60_cfg2 {
|
||||
ste,pins ="GPIO66_G3";
|
||||
ste,config = <&gpio_out_lo>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -31,17 +31,57 @@ out_lo: output_low {
|
||||
ste,output = <OUTPUT_LOW>;
|
||||
};
|
||||
|
||||
gpio_in_pu: gpio_input_pull_up {
|
||||
ste,gpio = <GPIOMODE_ENABLED>;
|
||||
ste,input = <INPUT_PULLUP>;
|
||||
};
|
||||
|
||||
gpio_in_pd: gpio_input_pull_down {
|
||||
ste,gpio = <GPIOMODE_ENABLED>;
|
||||
ste,input = <INPUT_PULLDOWN>;
|
||||
};
|
||||
|
||||
gpio_out_lo: gpio_output_low {
|
||||
ste,gpio = <GPIOMODE_ENABLED>;
|
||||
ste,output = <OUTPUT_LOW>;
|
||||
};
|
||||
|
||||
gpio_out_hi: gpio_output_high {
|
||||
ste,gpio = <GPIOMODE_ENABLED>;
|
||||
ste,output = <OUTPUT_HIGH>;
|
||||
};
|
||||
|
||||
slpm_pdis: slpm_pdis {
|
||||
ste,sleep = <SLPM_ENABLED>;
|
||||
ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>;
|
||||
ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
|
||||
};
|
||||
|
||||
slpm_wkup_pdis: slpm_wkup_pdis {
|
||||
ste,sleep = <SLPM_ENABLED>;
|
||||
ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
|
||||
ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
|
||||
};
|
||||
|
||||
slpm_wkup_pdis_en: slpm_wkup_pdis_en {
|
||||
ste,sleep = <SLPM_ENABLED>;
|
||||
ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
|
||||
ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
|
||||
};
|
||||
|
||||
slpm_in_pu: slpm_in_pu {
|
||||
ste,sleep = <SLPM_ENABLED>;
|
||||
ste,sleep-input = <SLPM_INPUT_PULLUP>;
|
||||
ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
|
||||
};
|
||||
|
||||
slpm_in_pdis: slpm_in_pdis {
|
||||
ste,sleep = <SLPM_ENABLED>;
|
||||
ste,sleep-input = <SLPM_DIR_INPUT>;
|
||||
ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>;
|
||||
ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
|
||||
};
|
||||
|
||||
slpm_in_wkup_pdis: slpm_in_wkup_pdis {
|
||||
ste,sleep = <SLPM_ENABLED>;
|
||||
ste,sleep-input = <SLPM_DIR_INPUT>;
|
||||
@ -49,6 +89,20 @@ slpm_in_wkup_pdis: slpm_in_wkup_pdis {
|
||||
ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
|
||||
};
|
||||
|
||||
slpm_in_wkup_pdis_en: slpm_in_wkup_pdis_en {
|
||||
ste,sleep = <SLPM_ENABLED>;
|
||||
ste,sleep-input = <SLPM_DIR_INPUT>;
|
||||
ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
|
||||
ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
|
||||
};
|
||||
|
||||
slpm_in_pu_wkup_pdis_en: slpm_in_wkup_pdis_en {
|
||||
ste,sleep = <SLPM_ENABLED>;
|
||||
ste,sleep-input = <SLPM_INPUT_PULLUP>;
|
||||
ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
|
||||
ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
|
||||
};
|
||||
|
||||
slpm_out_lo: slpm_out_lo {
|
||||
ste,sleep = <SLPM_ENABLED>;
|
||||
ste,sleep-output = <SLPM_OUTPUT_LOW>;
|
||||
@ -68,6 +122,20 @@ slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis {
|
||||
ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
|
||||
};
|
||||
|
||||
slpm_out_lo_pdis: slpm_out_lo_pdis {
|
||||
ste,sleep = <SLPM_ENABLED>;
|
||||
ste,sleep-output = <SLPM_OUTPUT_LOW>;
|
||||
ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>;
|
||||
ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
|
||||
};
|
||||
|
||||
slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis {
|
||||
ste,sleep = <SLPM_ENABLED>;
|
||||
ste,sleep-output = <SLPM_OUTPUT_LOW>;
|
||||
ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
|
||||
ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
|
||||
};
|
||||
|
||||
slpm_out_wkup_pdis: slpm_out_wkup_pdis {
|
||||
ste,sleep = <SLPM_ENABLED>;
|
||||
ste,sleep-output = <SLPM_DIR_OUTPUT>;
|
||||
@ -81,6 +149,18 @@ in_wkup_pdis: in_wkup_pdis {
|
||||
ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
|
||||
};
|
||||
|
||||
in_wkup_pdis_en: in_wkup_pdis_en {
|
||||
ste,sleep-input = <SLPM_DIR_INPUT>;
|
||||
ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
|
||||
ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
|
||||
};
|
||||
|
||||
out_lo_wkup_pdis: out_lo_wkup_pdis {
|
||||
ste,sleep-output = <SLPM_OUTPUT_LOW>;
|
||||
ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
|
||||
ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
|
||||
};
|
||||
|
||||
out_hi_wkup_pdis: out_hi_wkup_pdis {
|
||||
ste,sleep-output = <SLPM_OUTPUT_HIGH>;
|
||||
ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "ste-dbx5x0.dtsi"
|
||||
#include "ste-href-family-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Calao Systems Snowball platform with device tree";
|
||||
@ -75,6 +76,8 @@ button@5 {
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpioled_snowball_mode>;
|
||||
used-led {
|
||||
label = "user_led";
|
||||
gpios = <&gpio4 14 0x4>;
|
||||
@ -84,6 +87,11 @@ used-led {
|
||||
};
|
||||
|
||||
soc {
|
||||
usb_per5@a03e0000 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&musb_default_mode>;
|
||||
pinctrl-1 = <&musb_sleep_mode>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "stericsson,snd-soc-mop500";
|
||||
@ -92,7 +100,21 @@ sound {
|
||||
stericsson,audio-codec = <&codec>;
|
||||
};
|
||||
|
||||
msp0: msp@80123000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&msp0_default_mode>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
msp1: msp@80124000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&msp1_default_mode>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
msp2: msp@80117000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&msp2_default_mode>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -110,6 +132,8 @@ ethernet@0 {
|
||||
interrupt-parent = <&gpio4>;
|
||||
vdd33a-supply = <&en_3v3_reg>;
|
||||
vddvario-supply = <&db8500_vape_reg>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ð_snowball_mode>;
|
||||
|
||||
reg-shift = <1>;
|
||||
reg-io-width = <2>;
|
||||
@ -136,6 +160,9 @@ sdi0_per1@80126000 {
|
||||
mmc-cap-mmc-highspeed;
|
||||
vmmc-supply = <&ab8500_ldo_aux3_reg>;
|
||||
vqmmc-supply = <&vmmci>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdi0_default_mode>;
|
||||
pinctrl-1 = <&sdi0_sleep_mode>;
|
||||
|
||||
cd-gpios = <&gpio6 26 0x4>; // 218
|
||||
cd-inverted;
|
||||
@ -143,6 +170,27 @@ sdi0_per1@80126000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
// WLAN SDIO channel
|
||||
sdi1_per2@80118000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
max-frequency = <100000000>;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdi1_default_mode>;
|
||||
pinctrl-1 = <&sdi1_sleep_mode>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
// Unused PoP eMMC - register and put it to sleep by default */
|
||||
sdi2_per3@80005000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdi2_sleep_mode>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
// On-board eMMC
|
||||
sdi4_per2@80114000 {
|
||||
arm,primecell-periphid = <0x10480180>;
|
||||
@ -150,22 +198,63 @@ sdi4_per2@80114000 {
|
||||
bus-width = <8>;
|
||||
mmc-cap-mmc-highspeed;
|
||||
vmmc-supply = <&ab8500_ldo_aux2_reg>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdi4_default_mode>;
|
||||
pinctrl-1 = <&sdi4_sleep_mode>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart@80120000 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&uart0_default_mode>;
|
||||
pinctrl-1 = <&uart0_sleep_mode>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart@80121000 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&uart1_default_mode>;
|
||||
pinctrl-1 = <&uart1_sleep_mode>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart@80007000 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&uart2_default_mode>;
|
||||
pinctrl-1 = <&uart2_sleep_mode>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@80004000 {
|
||||
pinctrl-names = "default","sleep";
|
||||
pinctrl-0 = <&i2c0_default_mode>;
|
||||
pinctrl-1 = <&i2c0_sleep_mode>;
|
||||
};
|
||||
|
||||
i2c@80122000 {
|
||||
pinctrl-names = "default","sleep";
|
||||
pinctrl-0 = <&i2c1_default_mode>;
|
||||
pinctrl-1 = <&i2c1_sleep_mode>;
|
||||
};
|
||||
|
||||
i2c@80128000 {
|
||||
pinctrl-names = "default","sleep";
|
||||
pinctrl-0 = <&i2c2_default_mode>;
|
||||
pinctrl-1 = <&i2c2_sleep_mode>;
|
||||
};
|
||||
|
||||
i2c@80110000 {
|
||||
pinctrl-names = "default","sleep";
|
||||
pinctrl-0 = <&i2c3_default_mode>;
|
||||
pinctrl-1 = <&i2c3_sleep_mode>;
|
||||
};
|
||||
|
||||
ssp@80002000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ssp0_snowball_mode>;
|
||||
};
|
||||
|
||||
cpufreq-cooling {
|
||||
status = "okay";
|
||||
};
|
||||
@ -266,5 +355,141 @@ ab8500_ldo_ana_reg: ab8500_ldo_ana {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
/*
|
||||
* Set this up using hogs, as time goes by and as seems fit, these
|
||||
* can be moved over to being controlled by respective device.
|
||||
*/
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&accel_snowball_mode>,
|
||||
<&magneto_snowball_mode>,
|
||||
<&gbf_snowball_mode>,
|
||||
<&wlan_snowball_mode>;
|
||||
|
||||
ethernet {
|
||||
/*
|
||||
* Mux in "SM" which is used for the
|
||||
* SMSC911x Ethernet adapter
|
||||
*/
|
||||
eth_snowball_mode: eth_snowball {
|
||||
snowball_mux {
|
||||
ste,function = "sm";
|
||||
ste,pins = "sm_b_1";
|
||||
};
|
||||
/* LAN IRQ pin */
|
||||
snowball_cfg1 {
|
||||
ste,pins = "GPIO140_B11";
|
||||
ste,config = <&in_nopull>;
|
||||
};
|
||||
/* LAN reset pin */
|
||||
snowball_cfg2 {
|
||||
ste,pins = "GPIO141_C12";
|
||||
ste,config = <&gpio_out_hi>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
sdi0 {
|
||||
sdi0_default_mode: sdi0_default {
|
||||
snowball_mux {
|
||||
ste,function = "mc0";
|
||||
ste,pins = "mc0dat31dir_a_1";
|
||||
};
|
||||
snowball_cfg1 {
|
||||
ste,pins = "GPIO21_AB3"; /* DAT31DIR */
|
||||
ste,config = <&out_hi>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
ssp0 {
|
||||
ssp0_snowball_mode: ssp0_snowball_default {
|
||||
snowball_mux {
|
||||
ste,function = "ssp0";
|
||||
ste,pins = "ssp0_a_1";
|
||||
};
|
||||
snowball_cfg1 {
|
||||
ste,pins = "GPIO144_B13"; /* FRM */
|
||||
ste,config = <&gpio_out_hi>;
|
||||
};
|
||||
snowball_cfg2 {
|
||||
ste,pins = "GPIO145_C13"; /* RXD */
|
||||
ste,config = <&in_pd>;
|
||||
};
|
||||
snowball_cfg3 {
|
||||
ste,pins =
|
||||
"GPIO146_D13", /* TXD */
|
||||
"GPIO143_D12"; /* CLK */
|
||||
ste,config = <&out_lo>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
gpio_led {
|
||||
gpioled_snowball_mode: gpioled_default {
|
||||
snowball_cfg1 {
|
||||
ste,pins = "GPIO142_C11";
|
||||
ste,config = <&gpio_out_hi>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
accelerometer {
|
||||
accel_snowball_mode: accel_snowball {
|
||||
/* Accelerometer lines */
|
||||
snowball_cfg1 {
|
||||
ste,pins =
|
||||
"GPIO163_C20", /* ACCEL_IRQ1 */
|
||||
"GPIO164_B21"; /* ACCEL_IRQ2 */
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
magnetometer {
|
||||
magneto_snowball_mode: magneto_snowball {
|
||||
snowball_cfg1 {
|
||||
ste,pins = "GPIO165_C21"; /* MAG_DRDY */
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
gbf {
|
||||
gbf_snowball_mode: gbf_snowball {
|
||||
/*
|
||||
* GBF (GPS, Bluetooth, FM-radio) interface,
|
||||
* pull low to reset state
|
||||
*/
|
||||
snowball_cfg1 {
|
||||
ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */
|
||||
ste,config = <&gpio_out_lo>;
|
||||
};
|
||||
};
|
||||
};
|
||||
wlan {
|
||||
wlan_snowball_mode: wlan_snowball {
|
||||
/*
|
||||
* Activate this mode with the WLAN chip.
|
||||
* These are plain GPIO pins used by WLAN
|
||||
*/
|
||||
snowball_cfg1 {
|
||||
ste,pins =
|
||||
"GPIO161_D21", /* WLAN_PMU_EN */
|
||||
"GPIO215_AH13"; /* WLAN_ENA */
|
||||
ste,config = <&gpio_out_lo>;
|
||||
};
|
||||
snowball_cfg2 {
|
||||
ste,pins = "GPIO216_AG12"; /* WLAN_IRQ */
|
||||
ste,config = <&gpio_in_pu>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mcde@a0350000 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&lcd_default_mode>;
|
||||
pinctrl-1 = <&lcd_sleep_mode>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -2,10 +2,10 @@
|
||||
# Makefile for the linux kernel, U8500 machine.
|
||||
#
|
||||
|
||||
obj-y := cpu.o devices.o id.o timer.o pm.o
|
||||
obj-y := cpu.o id.o timer.o pm.o
|
||||
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
|
||||
obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
|
||||
obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \
|
||||
obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o
|
||||
obj-$(CONFIG_MACH_MOP500) += board-mop500-sdi.o \
|
||||
board-mop500-regulators.o \
|
||||
board-mop500-pins.o \
|
||||
board-mop500-audio.o
|
||||
|
||||
@ -7,16 +7,13 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_data/pinctrl-nomadik.h>
|
||||
#include <linux/platform_data/dma-ste-dma40.h>
|
||||
|
||||
#include "devices.h"
|
||||
#include "irqs.h"
|
||||
#include <linux/platform_data/asoc-ux500-msp.h>
|
||||
|
||||
#include "ste-dma40-db8500.h"
|
||||
#include "board-mop500.h"
|
||||
#include "devices-db8500.h"
|
||||
|
||||
static struct stedma40_chan_cfg msp0_dma_rx = {
|
||||
.high_priority = true,
|
||||
|
||||
@ -10,94 +10,18 @@
|
||||
#include <linux/string.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/platform_data/pinctrl-nomadik.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include "board-mop500.h"
|
||||
|
||||
enum custom_pin_cfg_t {
|
||||
PINS_FOR_DEFAULT,
|
||||
PINS_FOR_U9500,
|
||||
};
|
||||
|
||||
static enum custom_pin_cfg_t pinsfor;
|
||||
|
||||
/* These simply sets bias for pins */
|
||||
#define BIAS(a,b) static unsigned long a[] = { b }
|
||||
|
||||
BIAS(pd, PIN_PULL_DOWN);
|
||||
BIAS(in_nopull, PIN_INPUT_NOPULL);
|
||||
BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
|
||||
BIAS(in_pu, PIN_INPUT_PULLUP);
|
||||
BIAS(in_pd, PIN_INPUT_PULLDOWN);
|
||||
BIAS(out_hi, PIN_OUTPUT_HIGH);
|
||||
BIAS(out_lo, PIN_OUTPUT_LOW);
|
||||
BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
|
||||
|
||||
BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
|
||||
BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
|
||||
BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
|
||||
|
||||
/* These also force them into GPIO mode */
|
||||
BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
|
||||
BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
|
||||
BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
|
||||
BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
|
||||
BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
|
||||
BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
|
||||
/* Sleep modes */
|
||||
BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
|
||||
PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
|
||||
PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
|
||||
BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
|
||||
PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
|
||||
PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
|
||||
BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
|
||||
PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
|
||||
PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
|
||||
PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|
|
||||
PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
|
||||
PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
|
||||
BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|
|
||||
PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW|
|
||||
PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
|
||||
PIN_SLPM_PDIS_ENABLED);
|
||||
BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
|
||||
PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
|
||||
PIN_SLPM_PDIS_DISABLED);
|
||||
|
||||
/* We use these to define hog settings that are always done on boot */
|
||||
#define DB8500_MUX_HOG(group,func) \
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
|
||||
#define DB8500_PIN_HOG(pin,conf) \
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
|
||||
|
||||
/* These are default states associated with device and changed runtime */
|
||||
#define DB8500_MUX(group,func,dev) \
|
||||
PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
|
||||
#define DB8500_PIN(pin,conf,dev) \
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
|
||||
#define DB8500_PIN_IDLE(pin, conf, dev) \
|
||||
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500", \
|
||||
pin, conf)
|
||||
#define DB8500_PIN_SLEEP(pin, conf, dev) \
|
||||
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
|
||||
pin, conf)
|
||||
#define DB8500_MUX_STATE(group, func, dev, state) \
|
||||
PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
|
||||
#define DB8500_PIN_STATE(pin, conf, dev, state) \
|
||||
PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
|
||||
|
||||
#define AB8500_MUX_HOG(group, func) \
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
|
||||
#define AB8500_PIN_HOG(pin, conf) \
|
||||
@ -344,725 +268,8 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = {
|
||||
AB8505_PIN_HOG("GPIO53_D15", in_pd),
|
||||
};
|
||||
|
||||
/* Pin control settings */
|
||||
static struct pinctrl_map __initdata mop500_family_pinmap[] = {
|
||||
/*
|
||||
* uMSP0, mux in 4 pins, regular placement of RX/TX
|
||||
* explicitly set the pins to no pull
|
||||
*/
|
||||
DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
|
||||
DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
|
||||
DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
|
||||
DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
|
||||
DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
|
||||
DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
|
||||
/* MSP2 for HDMI, pull down TXD, TCK, TFS */
|
||||
DB8500_MUX_HOG("msp2_a_1", "msp2"),
|
||||
DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
|
||||
DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
|
||||
DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
|
||||
DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
|
||||
/*
|
||||
* LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
|
||||
* pull-up
|
||||
* TODO: is this really correct? Snowball doesn't have a LCD.
|
||||
*/
|
||||
DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
|
||||
DB8500_PIN_HOG("GPIO68_E1", in_pu),
|
||||
DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
|
||||
/*
|
||||
* STMPE1601/tc35893 keypad IRQ GPIO 218
|
||||
* TODO: set for snowball and HREF really??
|
||||
*/
|
||||
DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
|
||||
/*
|
||||
* UART0, we do not mux in u0 here.
|
||||
* uart-0 pins gpio configuration should be kept intact to prevent
|
||||
* a glitch in tx line when the tty dev is opened. Later these pins
|
||||
* are configured by uart driver
|
||||
*/
|
||||
DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
|
||||
DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
|
||||
DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
|
||||
DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
|
||||
/*
|
||||
* Mux in UART2 on altfunction C and set pull-ups.
|
||||
* TODO: is this used on U8500 variants and Snowball really?
|
||||
* The setting on GPIO31 conflicts with magnetometer use on hrefv60
|
||||
*/
|
||||
/* default state for UART2 */
|
||||
DB8500_MUX("u2rxtx_c_1", "u2", "uart2"),
|
||||
DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */
|
||||
DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */
|
||||
/* Sleep state for UART2 */
|
||||
DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"),
|
||||
DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"),
|
||||
/*
|
||||
* The following pin sets were known as "runtime pins" before being
|
||||
* converted to the pinctrl model. Here we model them as "default"
|
||||
* states.
|
||||
*/
|
||||
/* Mux in UART0 after initialization */
|
||||
DB8500_MUX("u0_a_1", "u0", "uart0"),
|
||||
DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
|
||||
DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
|
||||
DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
|
||||
DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
|
||||
/* Sleep state for UART0 */
|
||||
DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
|
||||
/* Mux in UART1 after initialization */
|
||||
DB8500_MUX("u1rxtx_a_1", "u1", "uart1"),
|
||||
DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */
|
||||
DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */
|
||||
/* Sleep state for UART1 */
|
||||
DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
|
||||
DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
|
||||
/* MSP1 for ALSA codec */
|
||||
DB8500_MUX_HOG("msp1txrx_a_1", "msp1"),
|
||||
DB8500_MUX_HOG("msp1_a_1", "msp1"),
|
||||
DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup),
|
||||
DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup),
|
||||
DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup),
|
||||
DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup),
|
||||
/* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
|
||||
DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
|
||||
DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
|
||||
/* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
|
||||
DB8500_MUX("lcdvsi1_a_1", "lcd", "0-0070"),
|
||||
DB8500_PIN("GPIO69_E2", in_pu, "0-0070"),
|
||||
/* LCD VSI1 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"),
|
||||
/* Mux in i2c0 block, default state */
|
||||
DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
|
||||
/* i2c0 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
|
||||
DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
|
||||
/* Mux in i2c1 block, default state */
|
||||
DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
|
||||
/* i2c1 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
|
||||
DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
|
||||
/* Mux in i2c2 block, default state */
|
||||
DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
|
||||
/* i2c2 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
|
||||
DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
|
||||
/* Mux in i2c3 block, default state */
|
||||
DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
|
||||
/* i2c3 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
|
||||
DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
|
||||
/* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
|
||||
DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
|
||||
DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
|
||||
DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
|
||||
DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
|
||||
DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
|
||||
DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
|
||||
DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
|
||||
DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
|
||||
DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
|
||||
DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
|
||||
DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
|
||||
/* SDI0 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO18_AC2", slpm_out_hi_wkup_pdis, "sdi0"),
|
||||
DB8500_PIN_SLEEP("GPIO19_AC1", slpm_out_hi_wkup_pdis, "sdi0"),
|
||||
DB8500_PIN_SLEEP("GPIO20_AB4", slpm_out_hi_wkup_pdis, "sdi0"),
|
||||
DB8500_PIN_SLEEP("GPIO22_AA3", slpm_in_wkup_pdis, "sdi0"),
|
||||
DB8500_PIN_SLEEP("GPIO23_AA4", slpm_out_lo_wkup_pdis, "sdi0"),
|
||||
DB8500_PIN_SLEEP("GPIO24_AB2", slpm_in_wkup_pdis, "sdi0"),
|
||||
DB8500_PIN_SLEEP("GPIO25_Y4", slpm_in_wkup_pdis, "sdi0"),
|
||||
DB8500_PIN_SLEEP("GPIO26_Y2", slpm_in_wkup_pdis, "sdi0"),
|
||||
DB8500_PIN_SLEEP("GPIO27_AA2", slpm_in_wkup_pdis, "sdi0"),
|
||||
DB8500_PIN_SLEEP("GPIO28_AA1", slpm_in_wkup_pdis, "sdi0"),
|
||||
|
||||
/* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
|
||||
DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
|
||||
DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
|
||||
DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
|
||||
DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
|
||||
DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
|
||||
DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
|
||||
DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
|
||||
DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
|
||||
/* SDI1 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO208_AH16", slpm_out_lo_wkup_pdis, "sdi1"), /* CLK */
|
||||
DB8500_PIN_SLEEP("GPIO209_AG15", slpm_in_wkup_pdis, "sdi1"), /* FBCLK */
|
||||
DB8500_PIN_SLEEP("GPIO210_AJ15", slpm_in_wkup_pdis, "sdi1"), /* CMD */
|
||||
DB8500_PIN_SLEEP("GPIO211_AG14", slpm_in_wkup_pdis, "sdi1"), /* DAT0 */
|
||||
DB8500_PIN_SLEEP("GPIO212_AF13", slpm_in_wkup_pdis, "sdi1"), /* DAT1 */
|
||||
DB8500_PIN_SLEEP("GPIO213_AG13", slpm_in_wkup_pdis, "sdi1"), /* DAT2 */
|
||||
DB8500_PIN_SLEEP("GPIO214_AH15", slpm_in_wkup_pdis, "sdi1"), /* DAT3 */
|
||||
|
||||
/* Mux in SDI2 (here called MC2) used for for PoP eMMC */
|
||||
DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
|
||||
DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
|
||||
DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
|
||||
DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
|
||||
DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
|
||||
DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
|
||||
DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
|
||||
DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
|
||||
DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
|
||||
DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
|
||||
DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
|
||||
DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
|
||||
/* SDI2 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO128_A5", out_lo_wkup_pdis, "sdi2"), /* CLK */
|
||||
DB8500_PIN_SLEEP("GPIO129_B4", in_wkup_pdis_en, "sdi2"), /* CMD */
|
||||
DB8500_PIN_SLEEP("GPIO130_C8", in_wkup_pdis_en, "sdi2"), /* FBCLK */
|
||||
DB8500_PIN_SLEEP("GPIO131_A12", in_wkup_pdis, "sdi2"), /* DAT0 */
|
||||
DB8500_PIN_SLEEP("GPIO132_C10", in_wkup_pdis, "sdi2"), /* DAT1 */
|
||||
DB8500_PIN_SLEEP("GPIO133_B10", in_wkup_pdis, "sdi2"), /* DAT2 */
|
||||
DB8500_PIN_SLEEP("GPIO134_B9", in_wkup_pdis, "sdi2"), /* DAT3 */
|
||||
DB8500_PIN_SLEEP("GPIO135_A9", in_wkup_pdis, "sdi2"), /* DAT4 */
|
||||
DB8500_PIN_SLEEP("GPIO136_C7", in_wkup_pdis, "sdi2"), /* DAT5 */
|
||||
DB8500_PIN_SLEEP("GPIO137_A7", in_wkup_pdis, "sdi2"), /* DAT6 */
|
||||
DB8500_PIN_SLEEP("GPIO138_C5", in_wkup_pdis, "sdi2"), /* DAT7 */
|
||||
|
||||
/* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
|
||||
DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
|
||||
DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
|
||||
DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
|
||||
DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
|
||||
DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
|
||||
DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
|
||||
DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
|
||||
DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
|
||||
DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
|
||||
DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
|
||||
DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
|
||||
DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
|
||||
/*SDI4 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO197_AH24", slpm_in_wkup_pdis, "sdi4"), /* DAT3 */
|
||||
DB8500_PIN_SLEEP("GPIO198_AG25", slpm_in_wkup_pdis, "sdi4"), /* DAT2 */
|
||||
DB8500_PIN_SLEEP("GPIO199_AH23", slpm_in_wkup_pdis, "sdi4"), /* DAT1 */
|
||||
DB8500_PIN_SLEEP("GPIO200_AH26", slpm_in_wkup_pdis, "sdi4"), /* DAT0 */
|
||||
DB8500_PIN_SLEEP("GPIO201_AF24", slpm_in_wkup_pdis, "sdi4"), /* CMD */
|
||||
DB8500_PIN_SLEEP("GPIO202_AF25", slpm_in_wkup_pdis, "sdi4"), /* FBCLK */
|
||||
DB8500_PIN_SLEEP("GPIO203_AE23", slpm_out_lo_wkup_pdis, "sdi4"), /* CLK */
|
||||
DB8500_PIN_SLEEP("GPIO204_AF23", slpm_in_wkup_pdis, "sdi4"), /* DAT7 */
|
||||
DB8500_PIN_SLEEP("GPIO205_AG23", slpm_in_wkup_pdis, "sdi4"), /* DAT6 */
|
||||
DB8500_PIN_SLEEP("GPIO206_AG24", slpm_in_wkup_pdis, "sdi4"), /* DAT5 */
|
||||
DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
|
||||
|
||||
/* Mux in USB pins, drive STP high */
|
||||
/* USB default state */
|
||||
DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"),
|
||||
DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */
|
||||
/* USB sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */
|
||||
DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */
|
||||
DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */
|
||||
DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */
|
||||
DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */
|
||||
DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */
|
||||
DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */
|
||||
DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */
|
||||
DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */
|
||||
DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */
|
||||
DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */
|
||||
DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */
|
||||
|
||||
/* Mux in SPI2 pins on the "other C1" altfunction */
|
||||
DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
|
||||
DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
|
||||
DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
|
||||
DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
|
||||
DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
|
||||
/* SPI2 idle state */
|
||||
DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
|
||||
DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
|
||||
DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
|
||||
/* SPI2 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
|
||||
DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
|
||||
DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
|
||||
DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
|
||||
|
||||
/* ske default state */
|
||||
DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
|
||||
DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */
|
||||
DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */
|
||||
DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */
|
||||
DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */
|
||||
DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */
|
||||
DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */
|
||||
DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */
|
||||
DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */
|
||||
DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
|
||||
DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
|
||||
DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
|
||||
DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
|
||||
DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
|
||||
DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
|
||||
DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
|
||||
DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
|
||||
/* ske sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
|
||||
DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
|
||||
DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
|
||||
DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
|
||||
DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
|
||||
DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
|
||||
DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
|
||||
DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
|
||||
DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
|
||||
DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
|
||||
DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
|
||||
DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
|
||||
DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
|
||||
DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
|
||||
DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
|
||||
DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
|
||||
|
||||
/* STM APE pins states */
|
||||
DB8500_MUX_STATE("stmape_c_1", "stmape",
|
||||
"stm", "ape_mipi34"),
|
||||
DB8500_PIN_STATE("GPIO70_G5", in_nopull,
|
||||
"stm", "ape_mipi34"), /* clk */
|
||||
DB8500_PIN_STATE("GPIO71_G4", in_nopull,
|
||||
"stm", "ape_mipi34"), /* dat3 */
|
||||
DB8500_PIN_STATE("GPIO72_H4", in_nopull,
|
||||
"stm", "ape_mipi34"), /* dat2 */
|
||||
DB8500_PIN_STATE("GPIO73_H3", in_nopull,
|
||||
"stm", "ape_mipi34"), /* dat1 */
|
||||
DB8500_PIN_STATE("GPIO74_J3", in_nopull,
|
||||
"stm", "ape_mipi34"), /* dat0 */
|
||||
|
||||
DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
|
||||
"stm", "ape_mipi34_sleep"), /* clk */
|
||||
DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
|
||||
"stm", "ape_mipi34_sleep"), /* dat3 */
|
||||
DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
|
||||
"stm", "ape_mipi34_sleep"), /* dat2 */
|
||||
DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
|
||||
"stm", "ape_mipi34_sleep"), /* dat1 */
|
||||
DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
|
||||
"stm", "ape_mipi34_sleep"), /* dat0 */
|
||||
|
||||
DB8500_MUX_STATE("stmape_oc1_1", "stmape",
|
||||
"stm", "ape_microsd"),
|
||||
DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
|
||||
"stm", "ape_microsd"), /* clk */
|
||||
DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
|
||||
"stm", "ape_microsd"), /* dat0 */
|
||||
DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
|
||||
"stm", "ape_microsd"), /* dat1 */
|
||||
DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
|
||||
"stm", "ape_microsd"), /* dat2 */
|
||||
DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
|
||||
"stm", "ape_microsd"), /* dat3 */
|
||||
|
||||
DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
|
||||
"stm", "ape_microsd_sleep"), /* clk */
|
||||
DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
|
||||
"stm", "ape_microsd_sleep"), /* dat0 */
|
||||
DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
|
||||
"stm", "ape_microsd_sleep"), /* dat1 */
|
||||
DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
|
||||
"stm", "ape_microsd_sleep"), /* dat2 */
|
||||
DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
|
||||
"stm", "ape_microsd_sleep"), /* dat3 */
|
||||
|
||||
/* STM Modem pins states */
|
||||
DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
|
||||
"stm", "mod_mipi34"),
|
||||
DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
|
||||
"stm", "mod_mipi34"),
|
||||
DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
|
||||
"stm", "mod_mipi34"),
|
||||
DB8500_PIN_STATE("GPIO70_G5", in_nopull,
|
||||
"stm", "mod_mipi34"), /* clk */
|
||||
DB8500_PIN_STATE("GPIO71_G4", in_nopull,
|
||||
"stm", "mod_mipi34"), /* dat3 */
|
||||
DB8500_PIN_STATE("GPIO72_H4", in_nopull,
|
||||
"stm", "mod_mipi34"), /* dat2 */
|
||||
DB8500_PIN_STATE("GPIO73_H3", in_nopull,
|
||||
"stm", "mod_mipi34"), /* dat1 */
|
||||
DB8500_PIN_STATE("GPIO74_J3", in_nopull,
|
||||
"stm", "mod_mipi34"), /* dat0 */
|
||||
DB8500_PIN_STATE("GPIO75_H2", in_pu,
|
||||
"stm", "mod_mipi34"), /* uartmod rx */
|
||||
DB8500_PIN_STATE("GPIO76_J2", out_lo,
|
||||
"stm", "mod_mipi34"), /* uartmod tx */
|
||||
|
||||
DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
|
||||
"stm", "mod_mipi34_sleep"), /* clk */
|
||||
DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
|
||||
"stm", "mod_mipi34_sleep"), /* dat3 */
|
||||
DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
|
||||
"stm", "mod_mipi34_sleep"), /* dat2 */
|
||||
DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
|
||||
"stm", "mod_mipi34_sleep"), /* dat1 */
|
||||
DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
|
||||
"stm", "mod_mipi34_sleep"), /* dat0 */
|
||||
DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
|
||||
"stm", "mod_mipi34_sleep"), /* uartmod rx */
|
||||
DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
|
||||
"stm", "mod_mipi34_sleep"), /* uartmod tx */
|
||||
|
||||
DB8500_MUX_STATE("stmmod_b_1", "stmmod",
|
||||
"stm", "mod_microsd"),
|
||||
DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
|
||||
"stm", "mod_microsd"),
|
||||
DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
|
||||
"stm", "mod_microsd"),
|
||||
DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
|
||||
"stm", "mod_microsd"), /* clk */
|
||||
DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
|
||||
"stm", "mod_microsd"), /* dat0 */
|
||||
DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
|
||||
"stm", "mod_microsd"), /* dat1 */
|
||||
DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
|
||||
"stm", "mod_microsd"), /* dat2 */
|
||||
DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
|
||||
"stm", "mod_microsd"), /* dat3 */
|
||||
DB8500_PIN_STATE("GPIO75_H2", in_pu,
|
||||
"stm", "mod_microsd"), /* uartmod rx */
|
||||
DB8500_PIN_STATE("GPIO76_J2", out_lo,
|
||||
"stm", "mod_microsd"), /* uartmod tx */
|
||||
|
||||
DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
|
||||
"stm", "mod_microsd_sleep"), /* clk */
|
||||
DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
|
||||
"stm", "mod_microsd_sleep"), /* dat0 */
|
||||
DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
|
||||
"stm", "mod_microsd_sleep"), /* dat1 */
|
||||
DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
|
||||
"stm", "mod_microsd_sleep"), /* dat2 */
|
||||
DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
|
||||
"stm", "mod_microsd_sleep"), /* dat3 */
|
||||
DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
|
||||
"stm", "mod_microsd_sleep"), /* uartmod rx */
|
||||
DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
|
||||
"stm", "mod_microsd_sleep"), /* uartmod tx */
|
||||
|
||||
/* STM dual Modem/APE pins state */
|
||||
DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
|
||||
"stm", "mod_mipi34_ape_mipi60"),
|
||||
DB8500_MUX_STATE("stmape_c_2", "stmape",
|
||||
"stm", "mod_mipi34_ape_mipi60"),
|
||||
DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
|
||||
"stm", "mod_mipi34_ape_mipi60"),
|
||||
DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
|
||||
"stm", "mod_mipi34_ape_mipi60"),
|
||||
DB8500_PIN_STATE("GPIO70_G5", in_nopull,
|
||||
"stm", "mod_mipi34_ape_mipi60"), /* clk */
|
||||
DB8500_PIN_STATE("GPIO71_G4", in_nopull,
|
||||
"stm", "mod_mipi34_ape_mipi60"), /* dat3 */
|
||||
DB8500_PIN_STATE("GPIO72_H4", in_nopull,
|
||||
"stm", "mod_mipi34_ape_mipi60"), /* dat2 */
|
||||
DB8500_PIN_STATE("GPIO73_H3", in_nopull,
|
||||
"stm", "mod_mipi34_ape_mipi60"), /* dat1 */
|
||||
DB8500_PIN_STATE("GPIO74_J3", in_nopull,
|
||||
"stm", "mod_mipi34_ape_mipi60"), /* dat0 */
|
||||
DB8500_PIN_STATE("GPIO75_H2", in_pu,
|
||||
"stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */
|
||||
DB8500_PIN_STATE("GPIO76_J2", out_lo,
|
||||
"stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */
|
||||
DB8500_PIN_STATE("GPIO155_C19", in_nopull,
|
||||
"stm", "mod_mipi34_ape_mipi60"), /* clk */
|
||||
DB8500_PIN_STATE("GPIO156_C17", in_nopull,
|
||||
"stm", "mod_mipi34_ape_mipi60"), /* dat3 */
|
||||
DB8500_PIN_STATE("GPIO157_A18", in_nopull,
|
||||
"stm", "mod_mipi34_ape_mipi60"), /* dat2 */
|
||||
DB8500_PIN_STATE("GPIO158_C18", in_nopull,
|
||||
"stm", "mod_mipi34_ape_mipi60"), /* dat1 */
|
||||
DB8500_PIN_STATE("GPIO159_B19", in_nopull,
|
||||
"stm", "mod_mipi34_ape_mipi60"), /* dat0 */
|
||||
|
||||
DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
|
||||
"stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
|
||||
DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
|
||||
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
|
||||
DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
|
||||
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
|
||||
DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
|
||||
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
|
||||
DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
|
||||
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
|
||||
DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
|
||||
"stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */
|
||||
DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
|
||||
"stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */
|
||||
DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis,
|
||||
"stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
|
||||
DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis,
|
||||
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
|
||||
DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis,
|
||||
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
|
||||
DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis,
|
||||
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
|
||||
DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis,
|
||||
"stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
|
||||
};
|
||||
|
||||
/*
|
||||
* These are specifically for the MOP500 and HREFP (pre-v60) version of the
|
||||
* board, which utilized a TC35892 GPIO expander instead of using a lot of
|
||||
* on-chip pins as the HREFv60 and later does.
|
||||
*/
|
||||
static struct pinctrl_map __initdata mop500_pinmap[] = {
|
||||
/* Mux in SSP0, pull down RXD pin */
|
||||
DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
|
||||
DB8500_PIN_HOG("GPIO145_C13", pd),
|
||||
/*
|
||||
* XENON Flashgun on image processor GPIO (controlled from image
|
||||
* processor firmware), mux in these image processor GPIO lines 0
|
||||
* (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
|
||||
* the pins.
|
||||
*/
|
||||
DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
|
||||
DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
|
||||
DB8500_PIN_HOG("GPIO6_AF6", in_pu),
|
||||
DB8500_PIN_HOG("GPIO7_AG5", in_pu),
|
||||
/* TC35892 IRQ, pull up the line, let the driver mux in the pin */
|
||||
DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
|
||||
/* Mux in UART1 and set the pull-ups */
|
||||
DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
|
||||
DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
|
||||
DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
|
||||
/*
|
||||
* Runtime stuff: make it possible to mux in the SKE keypad
|
||||
* and bias the pins
|
||||
*/
|
||||
/* ske default state */
|
||||
DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
|
||||
DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */
|
||||
DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */
|
||||
DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */
|
||||
DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */
|
||||
DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */
|
||||
DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */
|
||||
DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */
|
||||
DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */
|
||||
DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
|
||||
DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
|
||||
DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
|
||||
DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
|
||||
DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
|
||||
DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
|
||||
DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
|
||||
DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
|
||||
/* ske sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
|
||||
DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
|
||||
DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
|
||||
DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
|
||||
DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
|
||||
DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
|
||||
DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
|
||||
DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
|
||||
DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
|
||||
DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
|
||||
DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
|
||||
DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
|
||||
DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
|
||||
DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
|
||||
DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
|
||||
DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
|
||||
|
||||
/* Mux in and drive the SDI0 DAT31DIR line high at runtime */
|
||||
DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
|
||||
DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
|
||||
};
|
||||
|
||||
/*
|
||||
* The HREFv60 series of platforms is using available pins on the DB8500
|
||||
* insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
|
||||
* and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
|
||||
*/
|
||||
static struct pinctrl_map __initdata hrefv60_pinmap[] = {
|
||||
/* Drive WLAN_ENA low */
|
||||
DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
|
||||
/*
|
||||
* XENON Flashgun on image processor GPIO (controlled from image
|
||||
* processor firmware), mux in these image processor GPIO lines 0
|
||||
* (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
|
||||
* LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
|
||||
* from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
|
||||
*/
|
||||
DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
|
||||
DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
|
||||
DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
|
||||
DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
|
||||
DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
|
||||
DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
|
||||
DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
|
||||
/* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
|
||||
DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
|
||||
DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
|
||||
/*
|
||||
* Display Interface 1 uses GPIO 65 for RST (reset).
|
||||
* Display Interface 2 uses GPIO 66 for RST (reset).
|
||||
* Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
|
||||
*/
|
||||
DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
|
||||
DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
|
||||
/*
|
||||
* Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
|
||||
* GPIO 67 for interrupts. Pull-up the IRQ line and drive both
|
||||
* reset signals low.
|
||||
*/
|
||||
DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
|
||||
DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
|
||||
DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
|
||||
/*
|
||||
* Drive D19-D23 for the ETM PTM trace interface low,
|
||||
* (presumably pins are unconnected therefore grounded here,
|
||||
* the "other alt C1" setting enables these pins)
|
||||
*/
|
||||
DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
|
||||
DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
|
||||
DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
|
||||
DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
|
||||
DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
|
||||
/* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
|
||||
DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
|
||||
DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
|
||||
/* NFC ENA and RESET to low, pulldown IRQ line */
|
||||
DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
|
||||
DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
|
||||
DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
|
||||
/*
|
||||
* SKE keyboard partly on alt A and partly on "Other alt C1"
|
||||
* Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
|
||||
* rows of 6 keys, then pull up force sensing interrup and
|
||||
* drive reset and force sensing WU low.
|
||||
*/
|
||||
DB8500_MUX_HOG("kp_a_1", "kp"),
|
||||
DB8500_MUX_HOG("kp_oc1_1", "kp"),
|
||||
DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
|
||||
DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
|
||||
DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
|
||||
DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
|
||||
DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
|
||||
DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
|
||||
DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
|
||||
DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
|
||||
DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
|
||||
DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
|
||||
DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
|
||||
/* DiPro Sensor interrupt */
|
||||
DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
|
||||
/* Audio Amplifier HF enable */
|
||||
DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
|
||||
/* GBF interface, pull low to reset state */
|
||||
DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
|
||||
/* MSP : HDTV INTERFACE GPIO line */
|
||||
DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
|
||||
/* Accelerometer interrupt lines */
|
||||
DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
|
||||
DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
|
||||
/* SD card detect GPIO pin */
|
||||
DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
|
||||
/*
|
||||
* Runtime stuff
|
||||
* Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
|
||||
* etc.
|
||||
*/
|
||||
DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
|
||||
DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
|
||||
DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
|
||||
};
|
||||
|
||||
static struct pinctrl_map __initdata u9500_pinmap[] = {
|
||||
/* Mux in UART1 (just RX/TX) and set the pull-ups */
|
||||
DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
|
||||
DB8500_PIN_HOG("GPIO4_AH6", in_pu),
|
||||
DB8500_PIN_HOG("GPIO5_AG6", out_hi),
|
||||
/* WLAN_IRQ line */
|
||||
DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
|
||||
/* HSI */
|
||||
DB8500_MUX_HOG("hsir_a_1", "hsi"),
|
||||
DB8500_MUX_HOG("hsit_a_2", "hsi"),
|
||||
DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
|
||||
DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
|
||||
DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
|
||||
DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
|
||||
DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
|
||||
DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
|
||||
DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
|
||||
DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
|
||||
};
|
||||
|
||||
static struct pinctrl_map __initdata u8500_pinmap[] = {
|
||||
DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
|
||||
DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
|
||||
};
|
||||
|
||||
static struct pinctrl_map __initdata snowball_pinmap[] = {
|
||||
/* Mux in SSP0 connected to AB8500, pull down RXD pin */
|
||||
DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
|
||||
DB8500_PIN_HOG("GPIO145_C13", pd),
|
||||
/* Always drive the MC0 DAT31DIR line high on these boards */
|
||||
DB8500_PIN_HOG("GPIO21_AB3", out_hi),
|
||||
/* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
|
||||
DB8500_MUX_HOG("sm_b_1", "sm"),
|
||||
/* User LED */
|
||||
DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
|
||||
/* Drive RSTn_LAN high */
|
||||
DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
|
||||
/* Accelerometer/Magnetometer */
|
||||
DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
|
||||
DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
|
||||
DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
|
||||
/* WLAN/GBF */
|
||||
DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
|
||||
DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
|
||||
DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
|
||||
DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
|
||||
};
|
||||
|
||||
/*
|
||||
* passing "pinsfor=" in kernel cmdline allows for custom
|
||||
* configuration of GPIOs on u8500 derived boards.
|
||||
*/
|
||||
static int __init early_pinsfor(char *p)
|
||||
{
|
||||
pinsfor = PINS_FOR_DEFAULT;
|
||||
|
||||
if (strcmp(p, "u9500-21") == 0)
|
||||
pinsfor = PINS_FOR_U9500;
|
||||
|
||||
return 0;
|
||||
}
|
||||
early_param("pinsfor", early_pinsfor);
|
||||
|
||||
int pins_for_u9500(void)
|
||||
{
|
||||
if (pinsfor == PINS_FOR_U9500)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init mop500_href_family_pinmaps_init(void)
|
||||
{
|
||||
switch (pinsfor) {
|
||||
case PINS_FOR_U9500:
|
||||
pinctrl_register_mappings(u9500_pinmap,
|
||||
ARRAY_SIZE(u9500_pinmap));
|
||||
break;
|
||||
case PINS_FOR_DEFAULT:
|
||||
pinctrl_register_mappings(u8500_pinmap,
|
||||
ARRAY_SIZE(u8500_pinmap));
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void __init mop500_pinmaps_init(void)
|
||||
{
|
||||
pinctrl_register_mappings(mop500_family_pinmap,
|
||||
ARRAY_SIZE(mop500_family_pinmap));
|
||||
pinctrl_register_mappings(mop500_pinmap,
|
||||
ARRAY_SIZE(mop500_pinmap));
|
||||
mop500_href_family_pinmaps_init();
|
||||
if (machine_is_u8520())
|
||||
pinctrl_register_mappings(ab8505_pinmap,
|
||||
ARRAY_SIZE(ab8505_pinmap));
|
||||
@ -1073,23 +280,12 @@ void __init mop500_pinmaps_init(void)
|
||||
|
||||
void __init snowball_pinmaps_init(void)
|
||||
{
|
||||
pinctrl_register_mappings(mop500_family_pinmap,
|
||||
ARRAY_SIZE(mop500_family_pinmap));
|
||||
pinctrl_register_mappings(snowball_pinmap,
|
||||
ARRAY_SIZE(snowball_pinmap));
|
||||
pinctrl_register_mappings(u8500_pinmap,
|
||||
ARRAY_SIZE(u8500_pinmap));
|
||||
pinctrl_register_mappings(ab8500_pinmap,
|
||||
ARRAY_SIZE(ab8500_pinmap));
|
||||
}
|
||||
|
||||
void __init hrefv60_pinmaps_init(void)
|
||||
{
|
||||
pinctrl_register_mappings(mop500_family_pinmap,
|
||||
ARRAY_SIZE(mop500_family_pinmap));
|
||||
pinctrl_register_mappings(hrefv60_pinmap,
|
||||
ARRAY_SIZE(hrefv60_pinmap));
|
||||
mop500_href_family_pinmaps_init();
|
||||
pinctrl_register_mappings(ab8500_pinmap,
|
||||
ARRAY_SIZE(ab8500_pinmap));
|
||||
}
|
||||
|
||||
@ -14,10 +14,8 @@
|
||||
#include <linux/platform_data/dma-ste-dma40.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include "devices.h"
|
||||
|
||||
#include "db8500-regs.h"
|
||||
#include "devices-db8500.h"
|
||||
#include "board-mop500.h"
|
||||
#include "ste-dma40-db8500.h"
|
||||
|
||||
|
||||
@ -1,78 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2008-2012 ST-Ericsson
|
||||
*
|
||||
* Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_data/db8500_thermal.h>
|
||||
#include <linux/amba/bus.h>
|
||||
#include <linux/amba/pl022.h>
|
||||
#include <linux/mfd/abx500/ab8500.h>
|
||||
#include <linux/regulator/ab8500.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/driver.h>
|
||||
#include <linux/mfd/tps6105x.h>
|
||||
#include <linux/platform_data/leds-lp55xx.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/platform_data/pinctrl-nomadik.h>
|
||||
#include <linux/platform_data/dma-ste-dma40.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include "setup.h"
|
||||
#include "devices.h"
|
||||
#include "irqs.h"
|
||||
|
||||
#include "ste-dma40-db8500.h"
|
||||
#include "db8500-regs.h"
|
||||
#include "devices-db8500.h"
|
||||
#include "board-mop500.h"
|
||||
#include "board-mop500-regulators.h"
|
||||
|
||||
struct ab8500_platform_data ab8500_platdata = {
|
||||
.irq_base = MOP500_AB8500_IRQ_BASE,
|
||||
.regulator = &ab8500_regulator_plat_data,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_STE_DMA40
|
||||
static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
|
||||
.mode = STEDMA40_MODE_LOGICAL,
|
||||
.dir = DMA_DEV_TO_MEM,
|
||||
.dev_type = DB8500_DMA_DEV8_SSP0,
|
||||
};
|
||||
|
||||
static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
|
||||
.mode = STEDMA40_MODE_LOGICAL,
|
||||
.dir = DMA_MEM_TO_DEV,
|
||||
.dev_type = DB8500_DMA_DEV8_SSP0,
|
||||
};
|
||||
#endif
|
||||
|
||||
struct pl022_ssp_controller ssp0_plat = {
|
||||
.bus_id = 0,
|
||||
#ifdef CONFIG_STE_DMA40
|
||||
.enable_dma = 1,
|
||||
.dma_filter = stedma40_filter,
|
||||
.dma_rx_param = &ssp0_dma_cfg_rx,
|
||||
.dma_tx_param = &ssp0_dma_cfg_tx,
|
||||
#else
|
||||
.enable_dma = 0,
|
||||
#endif
|
||||
/* on this platform, gpio 31,142,144,214 &
|
||||
* 224 are connected as chip selects
|
||||
*/
|
||||
.num_chipselect = 5,
|
||||
};
|
||||
@ -87,7 +87,6 @@ extern struct msp_i2s_platform_data msp0_platform_data;
|
||||
extern struct msp_i2s_platform_data msp1_platform_data;
|
||||
extern struct msp_i2s_platform_data msp2_platform_data;
|
||||
extern struct msp_i2s_platform_data msp3_platform_data;
|
||||
extern struct pl022_ssp_controller ssp0_plat;
|
||||
|
||||
void __init mop500_pinmaps_init(void);
|
||||
void __init snowball_pinmaps_init(void);
|
||||
|
||||
@ -21,21 +21,32 @@
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/platform_data/pinctrl-nomadik.h>
|
||||
#include <linux/random.h>
|
||||
|
||||
#include <asm/pmu.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "setup.h"
|
||||
#include "devices.h"
|
||||
#include "irqs.h"
|
||||
|
||||
#include "devices-db8500.h"
|
||||
#include "db8500-regs.h"
|
||||
#include "board-mop500-regulators.h"
|
||||
#include "board-mop500.h"
|
||||
#include "db8500-regs.h"
|
||||
#include "id.h"
|
||||
|
||||
struct ab8500_platform_data ab8500_platdata = {
|
||||
.irq_base = MOP500_AB8500_IRQ_BASE,
|
||||
.regulator = &ab8500_regulator_plat_data,
|
||||
};
|
||||
|
||||
struct prcmu_pdata db8500_prcmu_pdata = {
|
||||
.ab_platdata = &ab8500_platdata,
|
||||
.ab_irq = IRQ_DB8500_AB8500,
|
||||
.irq_base = IRQ_PRCMU_BASE,
|
||||
.version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
|
||||
.legacy_offset = DB8500_PRCMU_LEGACY_OFFSET,
|
||||
};
|
||||
|
||||
/* minimum static i/o mapping required to boot U8500 platforms */
|
||||
static struct map_desc u8500_uart_io_desc[] __initdata = {
|
||||
__IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
|
||||
@ -155,9 +166,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL),
|
||||
OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0",
|
||||
NULL),
|
||||
/* Requires device name bindings. */
|
||||
OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE,
|
||||
"pinctrl-db8500", NULL),
|
||||
{},
|
||||
};
|
||||
|
||||
|
||||
@ -25,7 +25,6 @@
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "setup.h"
|
||||
#include "devices.h"
|
||||
|
||||
#include "board-mop500.h"
|
||||
#include "db8500-regs.h"
|
||||
@ -64,12 +63,7 @@ void __init ux500_init_irq(void)
|
||||
} else
|
||||
ux500_unknown_soc();
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
if (of_have_populated_dt())
|
||||
irqchip_init();
|
||||
else
|
||||
#endif
|
||||
gic_init(0, 29, dist_base, cpu_base);
|
||||
irqchip_init();
|
||||
|
||||
/*
|
||||
* Init clocks here so that they are available for system timer
|
||||
@ -79,16 +73,11 @@ void __init ux500_init_irq(void)
|
||||
prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
|
||||
ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
|
||||
|
||||
if (of_have_populated_dt())
|
||||
u8500_of_clk_init(U8500_CLKRST1_BASE,
|
||||
U8500_CLKRST2_BASE,
|
||||
U8500_CLKRST3_BASE,
|
||||
U8500_CLKRST5_BASE,
|
||||
U8500_CLKRST6_BASE);
|
||||
else
|
||||
u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
|
||||
U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
|
||||
U8500_CLKRST6_BASE);
|
||||
u8500_of_clk_init(U8500_CLKRST1_BASE,
|
||||
U8500_CLKRST2_BASE,
|
||||
U8500_CLKRST3_BASE,
|
||||
U8500_CLKRST5_BASE,
|
||||
U8500_CLKRST6_BASE);
|
||||
} else if (cpu_is_u9540()) {
|
||||
prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
|
||||
ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
|
||||
|
||||
@ -1,28 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2010
|
||||
*
|
||||
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/amba/bus.h>
|
||||
#include <linux/amba/pl022.h>
|
||||
#include <linux/mfd/dbx500-prcmu.h>
|
||||
|
||||
#include "setup.h"
|
||||
#include "irqs.h"
|
||||
|
||||
#include "db8500-regs.h"
|
||||
#include "devices-db8500.h"
|
||||
|
||||
struct prcmu_pdata db8500_prcmu_pdata = {
|
||||
.ab_platdata = &ab8500_platdata,
|
||||
.ab_irq = IRQ_DB8500_AB8500,
|
||||
.irq_base = IRQ_PRCMU_BASE,
|
||||
.version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
|
||||
.legacy_offset = DB8500_PRCMU_LEGACY_OFFSET,
|
||||
};
|
||||
@ -1,19 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2010
|
||||
*
|
||||
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL), version 2.
|
||||
*/
|
||||
|
||||
#ifndef __DEVICES_DB8500_H
|
||||
#define __DEVICES_DB8500_H
|
||||
|
||||
#include "irqs.h"
|
||||
#include "db8500-regs.h"
|
||||
|
||||
struct platform_device;
|
||||
|
||||
extern struct ab8500_platform_data ab8500_platdata;
|
||||
extern struct prcmu_pdata db8500_prcmu_pdata;
|
||||
|
||||
#endif
|
||||
@ -1,26 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2010
|
||||
*
|
||||
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/amba/bus.h>
|
||||
|
||||
#include "setup.h"
|
||||
|
||||
#include "db8500-regs.h"
|
||||
|
||||
void __init amba_add_devices(struct amba_device *devs[], int num)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num; i++) {
|
||||
struct amba_device *d = devs[i];
|
||||
amba_device_register(d, &iomem_resource);
|
||||
}
|
||||
}
|
||||
@ -1,15 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2010
|
||||
*
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_DEVICES_H__
|
||||
#define __ASM_ARCH_DEVICES_H__
|
||||
|
||||
struct platform_device;
|
||||
struct amba_device;
|
||||
|
||||
extern struct amba_device ux500_pl031_device;
|
||||
|
||||
#endif
|
||||
@ -19,17 +19,11 @@
|
||||
void ux500_restart(enum reboot_mode mode, const char *cmd);
|
||||
|
||||
void __init ux500_map_io(void);
|
||||
extern void __init u8500_map_io(void);
|
||||
|
||||
extern struct device * __init u8500_init_devices(void);
|
||||
|
||||
extern void __init ux500_init_irq(void);
|
||||
|
||||
extern struct device *ux500_soc_device_init(const char *soc_id);
|
||||
|
||||
struct amba_device;
|
||||
extern void __init amba_add_devices(struct amba_device *devs[], int num);
|
||||
|
||||
extern void ux500_timer_init(void);
|
||||
|
||||
#define __IO_DEV_DESC(x, sz) { \
|
||||
|
||||
@ -10,40 +10,12 @@
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_data/clocksource-nomadik-mtu.h>
|
||||
|
||||
#include <asm/smp_twd.h>
|
||||
|
||||
#include "setup.h"
|
||||
#include "irqs.h"
|
||||
|
||||
#include "db8500-regs.h"
|
||||
#include "id.h"
|
||||
|
||||
#ifdef CONFIG_HAVE_ARM_TWD
|
||||
static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
|
||||
U8500_TWD_BASE, IRQ_LOCALTIMER);
|
||||
|
||||
static void __init ux500_twd_init(void)
|
||||
{
|
||||
struct twd_local_timer *twd_local_timer;
|
||||
int err;
|
||||
|
||||
/* Use this to switch local timer base if changed in new ASICs */
|
||||
twd_local_timer = &u8500_twd_local_timer;
|
||||
|
||||
if (of_have_populated_dt())
|
||||
clocksource_of_init();
|
||||
else {
|
||||
err = twd_local_timer_register(twd_local_timer);
|
||||
if (err)
|
||||
pr_err("twd_local_timer_register failed %d\n", err);
|
||||
}
|
||||
}
|
||||
#else
|
||||
#define ux500_twd_init() do { } while(0)
|
||||
#endif
|
||||
|
||||
const static struct of_device_id prcmu_timer_of_match[] __initconst = {
|
||||
{ .compatible = "stericsson,db8500-prcmu-timer-4", },
|
||||
{ },
|
||||
@ -51,54 +23,26 @@ const static struct of_device_id prcmu_timer_of_match[] __initconst = {
|
||||
|
||||
void __init ux500_timer_init(void)
|
||||
{
|
||||
void __iomem *mtu_timer_base;
|
||||
void __iomem *prcmu_timer_base;
|
||||
void __iomem *tmp_base;
|
||||
struct device_node *np;
|
||||
|
||||
if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
|
||||
mtu_timer_base = __io_address(U8500_MTU0_BASE);
|
||||
if (cpu_is_u8500_family() || cpu_is_ux540_family())
|
||||
prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
|
||||
} else {
|
||||
else
|
||||
ux500_unknown_soc();
|
||||
}
|
||||
|
||||
/* TODO: Once MTU has been DT:ed place code above into else. */
|
||||
if (of_have_populated_dt()) {
|
||||
#ifdef CONFIG_OF
|
||||
np = of_find_matching_node(NULL, prcmu_timer_of_match);
|
||||
if (!np)
|
||||
#endif
|
||||
goto dt_fail;
|
||||
np = of_find_matching_node(NULL, prcmu_timer_of_match);
|
||||
if (!np)
|
||||
goto dt_fail;
|
||||
|
||||
tmp_base = of_iomap(np, 0);
|
||||
if (!tmp_base)
|
||||
goto dt_fail;
|
||||
tmp_base = of_iomap(np, 0);
|
||||
if (!tmp_base)
|
||||
goto dt_fail;
|
||||
|
||||
prcmu_timer_base = tmp_base;
|
||||
}
|
||||
prcmu_timer_base = tmp_base;
|
||||
|
||||
dt_fail:
|
||||
/* Doing it the old fashioned way. */
|
||||
|
||||
/*
|
||||
* Here we register the timerblocks active in the system.
|
||||
* Localtimers (twd) is started when both cpu is up and running.
|
||||
* MTU register a clocksource, clockevent and sched_clock.
|
||||
* Since the MTU is located in the VAPE power domain
|
||||
* it will be cleared in sleep which makes it unsuitable.
|
||||
* We however need it as a timer tick (clockevent)
|
||||
* during boot to calibrate delay until twd is started.
|
||||
* RTC-RTT have problems as timer tick during boot since it is
|
||||
* depending on delay which is not yet calibrated. RTC-RTT is in the
|
||||
* always-on powerdomain and is used as clockevent instead of twd when
|
||||
* sleeping.
|
||||
* The PRCMU timer 4 register a clocksource and
|
||||
* sched_clock with higher rating then MTU since is always-on.
|
||||
*
|
||||
*/
|
||||
if (!of_have_populated_dt())
|
||||
nmdk_timer_init(mtu_timer_base, IRQ_MTU0);
|
||||
clksrc_dbx500_prcmu_init(prcmu_timer_base);
|
||||
ux500_twd_init();
|
||||
clocksource_of_init();
|
||||
}
|
||||
|
||||
@ -20,7 +20,6 @@
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/platform_data/clocksource-nomadik-mtu.h>
|
||||
#include <linux/sched_clock.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
@ -103,7 +102,7 @@ static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void nmdk_clkevt_reset(void)
|
||||
static void nmdk_clkevt_reset(void)
|
||||
{
|
||||
if (clkevt_periodic) {
|
||||
/* Timer: configure load and background-load, and fire it up */
|
||||
@ -144,7 +143,7 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
|
||||
}
|
||||
}
|
||||
|
||||
void nmdk_clksrc_reset(void)
|
||||
static void nmdk_clksrc_reset(void)
|
||||
{
|
||||
/* Disable */
|
||||
writel(0, mtu_base + MTU_CR(0));
|
||||
@ -192,8 +191,8 @@ static struct irqaction nmdk_timer_irq = {
|
||||
.dev_id = &nmdk_clkevt,
|
||||
};
|
||||
|
||||
static void __init __nmdk_timer_init(void __iomem *base, int irq,
|
||||
struct clk *pclk, struct clk *clk)
|
||||
static void __init nmdk_timer_init(void __iomem *base, int irq,
|
||||
struct clk *pclk, struct clk *clk)
|
||||
{
|
||||
unsigned long rate;
|
||||
|
||||
@ -245,18 +244,6 @@ static void __init __nmdk_timer_init(void __iomem *base, int irq,
|
||||
register_current_timer_delay(&mtu_delay_timer);
|
||||
}
|
||||
|
||||
void __init nmdk_timer_init(void __iomem *base, int irq)
|
||||
{
|
||||
struct clk *clk0, *pclk0;
|
||||
|
||||
pclk0 = clk_get_sys("mtu0", "apb_pclk");
|
||||
BUG_ON(IS_ERR(pclk0));
|
||||
clk0 = clk_get_sys("mtu0", NULL);
|
||||
BUG_ON(IS_ERR(clk0));
|
||||
|
||||
__nmdk_timer_init(base, irq, pclk0, clk0);
|
||||
}
|
||||
|
||||
static void __init nmdk_timer_of_init(struct device_node *node)
|
||||
{
|
||||
struct clk *pclk;
|
||||
@ -280,7 +267,7 @@ static void __init nmdk_timer_of_init(struct device_node *node)
|
||||
if (irq <= 0)
|
||||
panic("Can't parse IRQ");
|
||||
|
||||
__nmdk_timer_init(base, irq, pclk, clk);
|
||||
nmdk_timer_init(base, irq, pclk, clk);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
|
||||
nmdk_timer_of_init);
|
||||
|
||||
@ -2409,6 +2409,7 @@ static void d40_set_prio_realtime(struct d40_chan *d40c)
|
||||
#define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1)
|
||||
#define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
|
||||
#define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
|
||||
#define D40_DT_FLAGS_HIGH_PRIO(flags) ((flags >> 4) & 0x1)
|
||||
|
||||
static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
@ -2446,6 +2447,9 @@ static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
|
||||
cfg.use_fixed_channel = true;
|
||||
}
|
||||
|
||||
if (D40_DT_FLAGS_HIGH_PRIO(flags))
|
||||
cfg.high_priority = true;
|
||||
|
||||
return dma_request_channel(cap, stedma40_filter, &cfg);
|
||||
}
|
||||
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
* Copyright (C) 2008,2009 STMicroelectronics
|
||||
* Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
|
||||
* Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
|
||||
* Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
|
||||
* Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
@ -33,7 +33,6 @@
|
||||
#include <linux/pinctrl/pinconf.h>
|
||||
/* Since we request GPIOs from ourself */
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/platform_data/pinctrl-nomadik.h>
|
||||
#include "pinctrl-nomadik.h"
|
||||
#include "core.h"
|
||||
|
||||
@ -45,6 +44,221 @@
|
||||
* Symbols in this file are called "nmk_gpio" for "nomadik gpio"
|
||||
*/
|
||||
|
||||
/*
|
||||
* pin configurations are represented by 32-bit integers:
|
||||
*
|
||||
* bit 0.. 8 - Pin Number (512 Pins Maximum)
|
||||
* bit 9..10 - Alternate Function Selection
|
||||
* bit 11..12 - Pull up/down state
|
||||
* bit 13 - Sleep mode behaviour
|
||||
* bit 14 - Direction
|
||||
* bit 15 - Value (if output)
|
||||
* bit 16..18 - SLPM pull up/down state
|
||||
* bit 19..20 - SLPM direction
|
||||
* bit 21..22 - SLPM Value (if output)
|
||||
* bit 23..25 - PDIS value (if input)
|
||||
* bit 26 - Gpio mode
|
||||
* bit 27 - Sleep mode
|
||||
*
|
||||
* to facilitate the definition, the following macros are provided
|
||||
*
|
||||
* PIN_CFG_DEFAULT - default config (0):
|
||||
* pull up/down = disabled
|
||||
* sleep mode = input/wakeup
|
||||
* direction = input
|
||||
* value = low
|
||||
* SLPM direction = same as normal
|
||||
* SLPM pull = same as normal
|
||||
* SLPM value = same as normal
|
||||
*
|
||||
* PIN_CFG - default config with alternate function
|
||||
*/
|
||||
|
||||
typedef unsigned long pin_cfg_t;
|
||||
|
||||
#define PIN_NUM_MASK 0x1ff
|
||||
#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
|
||||
|
||||
#define PIN_ALT_SHIFT 9
|
||||
#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
|
||||
#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
|
||||
#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
|
||||
#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
|
||||
#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
|
||||
#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
|
||||
|
||||
#define PIN_PULL_SHIFT 11
|
||||
#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
|
||||
#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
|
||||
#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
|
||||
#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
|
||||
#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
|
||||
|
||||
#define PIN_SLPM_SHIFT 13
|
||||
#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
|
||||
#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
|
||||
#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
|
||||
#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
|
||||
/* These two replace the above in DB8500v2+ */
|
||||
#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
|
||||
#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
|
||||
#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
|
||||
|
||||
#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
|
||||
#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
|
||||
|
||||
#define PIN_DIR_SHIFT 14
|
||||
#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
|
||||
#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
|
||||
#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
|
||||
#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
|
||||
|
||||
#define PIN_VAL_SHIFT 15
|
||||
#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
|
||||
#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
|
||||
#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
|
||||
#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
|
||||
|
||||
#define PIN_SLPM_PULL_SHIFT 16
|
||||
#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
|
||||
#define PIN_SLPM_PULL(x) \
|
||||
(((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
|
||||
#define PIN_SLPM_PULL_NONE \
|
||||
((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
|
||||
#define PIN_SLPM_PULL_UP \
|
||||
((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
|
||||
#define PIN_SLPM_PULL_DOWN \
|
||||
((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
|
||||
|
||||
#define PIN_SLPM_DIR_SHIFT 19
|
||||
#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
|
||||
#define PIN_SLPM_DIR(x) \
|
||||
(((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
|
||||
#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
|
||||
#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
|
||||
|
||||
#define PIN_SLPM_VAL_SHIFT 21
|
||||
#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
|
||||
#define PIN_SLPM_VAL(x) \
|
||||
(((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
|
||||
#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
|
||||
#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
|
||||
|
||||
#define PIN_SLPM_PDIS_SHIFT 23
|
||||
#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
|
||||
#define PIN_SLPM_PDIS(x) \
|
||||
(((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
|
||||
#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
|
||||
#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
|
||||
#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
|
||||
|
||||
#define PIN_LOWEMI_SHIFT 25
|
||||
#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
|
||||
#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
|
||||
#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
|
||||
#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
|
||||
|
||||
#define PIN_GPIOMODE_SHIFT 26
|
||||
#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
|
||||
#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
|
||||
#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
|
||||
#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
|
||||
|
||||
#define PIN_SLEEPMODE_SHIFT 27
|
||||
#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
|
||||
#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
|
||||
#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
|
||||
#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
|
||||
|
||||
|
||||
/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
|
||||
#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
|
||||
#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
|
||||
#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
|
||||
#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
|
||||
#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
|
||||
|
||||
#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
|
||||
#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
|
||||
#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
|
||||
#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
|
||||
#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
|
||||
|
||||
#define PIN_CFG_DEFAULT (0)
|
||||
|
||||
#define PIN_CFG(num, alt) \
|
||||
(PIN_CFG_DEFAULT |\
|
||||
(PIN_NUM(num) | PIN_##alt))
|
||||
|
||||
#define PIN_CFG_INPUT(num, alt, pull) \
|
||||
(PIN_CFG_DEFAULT |\
|
||||
(PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
|
||||
|
||||
#define PIN_CFG_OUTPUT(num, alt, val) \
|
||||
(PIN_CFG_DEFAULT |\
|
||||
(PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
|
||||
|
||||
/*
|
||||
* "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
|
||||
* the "gpio" namespace for generic and cross-machine functions
|
||||
*/
|
||||
|
||||
#define GPIO_BLOCK_SHIFT 5
|
||||
#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
|
||||
|
||||
/* Register in the logic block */
|
||||
#define NMK_GPIO_DAT 0x00
|
||||
#define NMK_GPIO_DATS 0x04
|
||||
#define NMK_GPIO_DATC 0x08
|
||||
#define NMK_GPIO_PDIS 0x0c
|
||||
#define NMK_GPIO_DIR 0x10
|
||||
#define NMK_GPIO_DIRS 0x14
|
||||
#define NMK_GPIO_DIRC 0x18
|
||||
#define NMK_GPIO_SLPC 0x1c
|
||||
#define NMK_GPIO_AFSLA 0x20
|
||||
#define NMK_GPIO_AFSLB 0x24
|
||||
#define NMK_GPIO_LOWEMI 0x28
|
||||
|
||||
#define NMK_GPIO_RIMSC 0x40
|
||||
#define NMK_GPIO_FIMSC 0x44
|
||||
#define NMK_GPIO_IS 0x48
|
||||
#define NMK_GPIO_IC 0x4c
|
||||
#define NMK_GPIO_RWIMSC 0x50
|
||||
#define NMK_GPIO_FWIMSC 0x54
|
||||
#define NMK_GPIO_WKS 0x58
|
||||
/* These appear in DB8540 and later ASICs */
|
||||
#define NMK_GPIO_EDGELEVEL 0x5C
|
||||
#define NMK_GPIO_LEVEL 0x60
|
||||
|
||||
|
||||
/* Pull up/down values */
|
||||
enum nmk_gpio_pull {
|
||||
NMK_GPIO_PULL_NONE,
|
||||
NMK_GPIO_PULL_UP,
|
||||
NMK_GPIO_PULL_DOWN,
|
||||
};
|
||||
|
||||
/* Sleep mode */
|
||||
enum nmk_gpio_slpm {
|
||||
NMK_GPIO_SLPM_INPUT,
|
||||
NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
|
||||
NMK_GPIO_SLPM_NOCHANGE,
|
||||
NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
|
||||
};
|
||||
|
||||
/*
|
||||
* Platform data to register a block: only the initial gpio/irq number.
|
||||
*/
|
||||
struct nmk_gpio_platform_data {
|
||||
char *name;
|
||||
int first_gpio;
|
||||
int first_irq;
|
||||
int num_gpio;
|
||||
u32 (*get_secondary_status)(unsigned int bank);
|
||||
void (*set_ioforce)(bool enable);
|
||||
bool supports_sleepmode;
|
||||
};
|
||||
|
||||
struct nmk_gpio_chip {
|
||||
struct gpio_chip chip;
|
||||
struct irq_domain *domain;
|
||||
@ -1026,7 +1240,7 @@ static const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
|
||||
|
||||
static int nmk_gpio_probe(struct platform_device *dev)
|
||||
{
|
||||
struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
|
||||
struct nmk_gpio_platform_data *pdata;
|
||||
struct device_node *np = dev->dev.of_node;
|
||||
struct nmk_gpio_chip *nmk_chip;
|
||||
struct gpio_chip *chip;
|
||||
@ -1034,31 +1248,23 @@ static int nmk_gpio_probe(struct platform_device *dev)
|
||||
struct clk *clk;
|
||||
int secondary_irq;
|
||||
void __iomem *base;
|
||||
int irq_start = 0;
|
||||
int irq;
|
||||
int ret;
|
||||
|
||||
if (!pdata && !np) {
|
||||
dev_err(&dev->dev, "No platform data or device tree found\n");
|
||||
return -ENODEV;
|
||||
pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
|
||||
if (!pdata)
|
||||
return -ENOMEM;
|
||||
|
||||
if (of_get_property(np, "st,supports-sleepmode", NULL))
|
||||
pdata->supports_sleepmode = true;
|
||||
|
||||
if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
|
||||
dev_err(&dev->dev, "gpio-bank property not found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (np) {
|
||||
pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
|
||||
if (!pdata)
|
||||
return -ENOMEM;
|
||||
|
||||
if (of_get_property(np, "st,supports-sleepmode", NULL))
|
||||
pdata->supports_sleepmode = true;
|
||||
|
||||
if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
|
||||
dev_err(&dev->dev, "gpio-bank property not found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
|
||||
pdata->num_gpio = NMK_GPIO_PER_CHIP;
|
||||
}
|
||||
pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
|
||||
pdata->num_gpio = NMK_GPIO_PER_CHIP;
|
||||
|
||||
irq = platform_get_irq(dev, 0);
|
||||
if (irq < 0)
|
||||
@ -1107,10 +1313,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
|
||||
clk_enable(nmk_chip->clk);
|
||||
nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
|
||||
clk_disable(nmk_chip->clk);
|
||||
|
||||
#ifdef CONFIG_OF_GPIO
|
||||
chip->of_node = np;
|
||||
#endif
|
||||
|
||||
ret = gpiochip_add(&nmk_chip->chip);
|
||||
if (ret)
|
||||
@ -1122,10 +1325,8 @@ static int nmk_gpio_probe(struct platform_device *dev)
|
||||
|
||||
platform_set_drvdata(dev, nmk_chip);
|
||||
|
||||
if (!np)
|
||||
irq_start = pdata->first_irq;
|
||||
nmk_chip->domain = irq_domain_add_simple(np,
|
||||
NMK_GPIO_PER_CHIP, irq_start,
|
||||
NMK_GPIO_PER_CHIP, 0,
|
||||
&nmk_gpio_irq_simple_ops, nmk_chip);
|
||||
if (!nmk_chip->domain) {
|
||||
dev_err(&dev->dev, "failed to create irqdomain\n");
|
||||
@ -1858,11 +2059,10 @@ static int nmk_pinctrl_resume(struct platform_device *pdev)
|
||||
|
||||
static int nmk_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct platform_device_id *platid = platform_get_device_id(pdev);
|
||||
const struct of_device_id *match;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct device_node *prcm_np;
|
||||
struct nmk_pinctrl *npct;
|
||||
struct resource *res;
|
||||
unsigned int version = 0;
|
||||
int i;
|
||||
|
||||
@ -1870,16 +2070,10 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
|
||||
if (!npct)
|
||||
return -ENOMEM;
|
||||
|
||||
if (platid)
|
||||
version = platid->driver_data;
|
||||
else if (np) {
|
||||
const struct of_device_id *match;
|
||||
|
||||
match = of_match_device(nmk_pinctrl_match, &pdev->dev);
|
||||
if (!match)
|
||||
return -ENODEV;
|
||||
version = (unsigned int) match->data;
|
||||
}
|
||||
match = of_match_device(nmk_pinctrl_match, &pdev->dev);
|
||||
if (!match)
|
||||
return -ENODEV;
|
||||
version = (unsigned int) match->data;
|
||||
|
||||
/* Poke in other ASIC variants here */
|
||||
if (version == PINCTRL_NMK_STN8815)
|
||||
@ -1889,17 +2083,9 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
|
||||
if (version == PINCTRL_NMK_DB8540)
|
||||
nmk_pinctrl_db8540_init(&npct->soc);
|
||||
|
||||
if (np) {
|
||||
prcm_np = of_parse_phandle(np, "prcm", 0);
|
||||
if (prcm_np)
|
||||
npct->prcm_base = of_iomap(prcm_np, 0);
|
||||
}
|
||||
|
||||
/* Allow platform passed information to over-write DT. */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (res)
|
||||
npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
|
||||
resource_size(res));
|
||||
prcm_np = of_parse_phandle(np, "prcm", 0);
|
||||
if (prcm_np)
|
||||
npct->prcm_base = of_iomap(prcm_np, 0);
|
||||
if (!npct->prcm_base) {
|
||||
if (version == PINCTRL_NMK_STN8815) {
|
||||
dev_info(&pdev->dev,
|
||||
@ -1958,13 +2144,6 @@ static struct platform_driver nmk_gpio_driver = {
|
||||
.probe = nmk_gpio_probe,
|
||||
};
|
||||
|
||||
static const struct platform_device_id nmk_pinctrl_id[] = {
|
||||
{ "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
|
||||
{ "pinctrl-db8500", PINCTRL_NMK_DB8500 },
|
||||
{ "pinctrl-db8540", PINCTRL_NMK_DB8540 },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver nmk_pinctrl_driver = {
|
||||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
@ -1972,7 +2151,6 @@ static struct platform_driver nmk_pinctrl_driver = {
|
||||
.of_match_table = nmk_pinctrl_match,
|
||||
},
|
||||
.probe = nmk_pinctrl_probe,
|
||||
.id_table = nmk_pinctrl_id,
|
||||
#ifdef CONFIG_PM
|
||||
.suspend = nmk_pinctrl_suspend,
|
||||
.resume = nmk_pinctrl_resume,
|
||||
|
||||
@ -1,13 +1,23 @@
|
||||
#ifndef PINCTRL_PINCTRL_NOMADIK_H
|
||||
#define PINCTRL_PINCTRL_NOMADIK_H
|
||||
|
||||
#include <linux/platform_data/pinctrl-nomadik.h>
|
||||
|
||||
/* Package definitions */
|
||||
#define PINCTRL_NMK_STN8815 0
|
||||
#define PINCTRL_NMK_DB8500 1
|
||||
#define PINCTRL_NMK_DB8540 2
|
||||
|
||||
/* Alternate functions: function C is set in hw by setting both A and B */
|
||||
#define NMK_GPIO_ALT_GPIO 0
|
||||
#define NMK_GPIO_ALT_A 1
|
||||
#define NMK_GPIO_ALT_B 2
|
||||
#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
|
||||
|
||||
#define NMK_GPIO_ALT_CX_SHIFT 2
|
||||
#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
|
||||
#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
|
||||
#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
|
||||
#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
|
||||
|
||||
#define PRCM_GPIOCR_ALTCX(pin_num,\
|
||||
altc1_used, altc1_ri, altc1_cb,\
|
||||
altc2_used, altc2_ri, altc2_cb,\
|
||||
|
||||
@ -1,9 +0,0 @@
|
||||
#ifndef __PLAT_MTU_H
|
||||
#define __PLAT_MTU_H
|
||||
|
||||
void nmdk_timer_init(void __iomem *base, int irq);
|
||||
void nmdk_clkevt_reset(void);
|
||||
void nmdk_clksrc_reset(void);
|
||||
|
||||
#endif /* __PLAT_MTU_H */
|
||||
|
||||
@ -1,242 +0,0 @@
|
||||
/*
|
||||
* Structures and registers for GPIO access in the Nomadik SoC
|
||||
*
|
||||
* Copyright (C) 2008 STMicroelectronics
|
||||
* Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
|
||||
* Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_NOMADIK_GPIO
|
||||
#define __PLAT_NOMADIK_GPIO
|
||||
|
||||
/*
|
||||
* pin configurations are represented by 32-bit integers:
|
||||
*
|
||||
* bit 0.. 8 - Pin Number (512 Pins Maximum)
|
||||
* bit 9..10 - Alternate Function Selection
|
||||
* bit 11..12 - Pull up/down state
|
||||
* bit 13 - Sleep mode behaviour
|
||||
* bit 14 - Direction
|
||||
* bit 15 - Value (if output)
|
||||
* bit 16..18 - SLPM pull up/down state
|
||||
* bit 19..20 - SLPM direction
|
||||
* bit 21..22 - SLPM Value (if output)
|
||||
* bit 23..25 - PDIS value (if input)
|
||||
* bit 26 - Gpio mode
|
||||
* bit 27 - Sleep mode
|
||||
*
|
||||
* to facilitate the definition, the following macros are provided
|
||||
*
|
||||
* PIN_CFG_DEFAULT - default config (0):
|
||||
* pull up/down = disabled
|
||||
* sleep mode = input/wakeup
|
||||
* direction = input
|
||||
* value = low
|
||||
* SLPM direction = same as normal
|
||||
* SLPM pull = same as normal
|
||||
* SLPM value = same as normal
|
||||
*
|
||||
* PIN_CFG - default config with alternate function
|
||||
*/
|
||||
|
||||
typedef unsigned long pin_cfg_t;
|
||||
|
||||
#define PIN_NUM_MASK 0x1ff
|
||||
#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
|
||||
|
||||
#define PIN_ALT_SHIFT 9
|
||||
#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
|
||||
#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
|
||||
#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
|
||||
#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
|
||||
#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
|
||||
#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
|
||||
|
||||
#define PIN_PULL_SHIFT 11
|
||||
#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
|
||||
#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
|
||||
#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
|
||||
#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
|
||||
#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
|
||||
|
||||
#define PIN_SLPM_SHIFT 13
|
||||
#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
|
||||
#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
|
||||
#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
|
||||
#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
|
||||
/* These two replace the above in DB8500v2+ */
|
||||
#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
|
||||
#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
|
||||
#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
|
||||
|
||||
#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
|
||||
#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
|
||||
|
||||
#define PIN_DIR_SHIFT 14
|
||||
#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
|
||||
#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
|
||||
#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
|
||||
#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
|
||||
|
||||
#define PIN_VAL_SHIFT 15
|
||||
#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
|
||||
#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
|
||||
#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
|
||||
#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
|
||||
|
||||
#define PIN_SLPM_PULL_SHIFT 16
|
||||
#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
|
||||
#define PIN_SLPM_PULL(x) \
|
||||
(((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
|
||||
#define PIN_SLPM_PULL_NONE \
|
||||
((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
|
||||
#define PIN_SLPM_PULL_UP \
|
||||
((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
|
||||
#define PIN_SLPM_PULL_DOWN \
|
||||
((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
|
||||
|
||||
#define PIN_SLPM_DIR_SHIFT 19
|
||||
#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
|
||||
#define PIN_SLPM_DIR(x) \
|
||||
(((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
|
||||
#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
|
||||
#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
|
||||
|
||||
#define PIN_SLPM_VAL_SHIFT 21
|
||||
#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
|
||||
#define PIN_SLPM_VAL(x) \
|
||||
(((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
|
||||
#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
|
||||
#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
|
||||
|
||||
#define PIN_SLPM_PDIS_SHIFT 23
|
||||
#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
|
||||
#define PIN_SLPM_PDIS(x) \
|
||||
(((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
|
||||
#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
|
||||
#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
|
||||
#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
|
||||
|
||||
#define PIN_LOWEMI_SHIFT 25
|
||||
#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
|
||||
#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
|
||||
#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
|
||||
#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
|
||||
|
||||
#define PIN_GPIOMODE_SHIFT 26
|
||||
#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
|
||||
#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
|
||||
#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
|
||||
#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
|
||||
|
||||
#define PIN_SLEEPMODE_SHIFT 27
|
||||
#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
|
||||
#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
|
||||
#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
|
||||
#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
|
||||
|
||||
|
||||
/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
|
||||
#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
|
||||
#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
|
||||
#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
|
||||
#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
|
||||
#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
|
||||
|
||||
#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
|
||||
#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
|
||||
#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
|
||||
#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
|
||||
#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
|
||||
|
||||
#define PIN_CFG_DEFAULT (0)
|
||||
|
||||
#define PIN_CFG(num, alt) \
|
||||
(PIN_CFG_DEFAULT |\
|
||||
(PIN_NUM(num) | PIN_##alt))
|
||||
|
||||
#define PIN_CFG_INPUT(num, alt, pull) \
|
||||
(PIN_CFG_DEFAULT |\
|
||||
(PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
|
||||
|
||||
#define PIN_CFG_OUTPUT(num, alt, val) \
|
||||
(PIN_CFG_DEFAULT |\
|
||||
(PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
|
||||
|
||||
/*
|
||||
* "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
|
||||
* the "gpio" namespace for generic and cross-machine functions
|
||||
*/
|
||||
|
||||
#define GPIO_BLOCK_SHIFT 5
|
||||
#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
|
||||
|
||||
/* Register in the logic block */
|
||||
#define NMK_GPIO_DAT 0x00
|
||||
#define NMK_GPIO_DATS 0x04
|
||||
#define NMK_GPIO_DATC 0x08
|
||||
#define NMK_GPIO_PDIS 0x0c
|
||||
#define NMK_GPIO_DIR 0x10
|
||||
#define NMK_GPIO_DIRS 0x14
|
||||
#define NMK_GPIO_DIRC 0x18
|
||||
#define NMK_GPIO_SLPC 0x1c
|
||||
#define NMK_GPIO_AFSLA 0x20
|
||||
#define NMK_GPIO_AFSLB 0x24
|
||||
#define NMK_GPIO_LOWEMI 0x28
|
||||
|
||||
#define NMK_GPIO_RIMSC 0x40
|
||||
#define NMK_GPIO_FIMSC 0x44
|
||||
#define NMK_GPIO_IS 0x48
|
||||
#define NMK_GPIO_IC 0x4c
|
||||
#define NMK_GPIO_RWIMSC 0x50
|
||||
#define NMK_GPIO_FWIMSC 0x54
|
||||
#define NMK_GPIO_WKS 0x58
|
||||
/* These appear in DB8540 and later ASICs */
|
||||
#define NMK_GPIO_EDGELEVEL 0x5C
|
||||
#define NMK_GPIO_LEVEL 0x60
|
||||
|
||||
/* Alternate functions: function C is set in hw by setting both A and B */
|
||||
#define NMK_GPIO_ALT_GPIO 0
|
||||
#define NMK_GPIO_ALT_A 1
|
||||
#define NMK_GPIO_ALT_B 2
|
||||
#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
|
||||
|
||||
#define NMK_GPIO_ALT_CX_SHIFT 2
|
||||
#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
|
||||
#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
|
||||
#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
|
||||
#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
|
||||
|
||||
/* Pull up/down values */
|
||||
enum nmk_gpio_pull {
|
||||
NMK_GPIO_PULL_NONE,
|
||||
NMK_GPIO_PULL_UP,
|
||||
NMK_GPIO_PULL_DOWN,
|
||||
};
|
||||
|
||||
/* Sleep mode */
|
||||
enum nmk_gpio_slpm {
|
||||
NMK_GPIO_SLPM_INPUT,
|
||||
NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
|
||||
NMK_GPIO_SLPM_NOCHANGE,
|
||||
NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
|
||||
};
|
||||
|
||||
/*
|
||||
* Platform data to register a block: only the initial gpio/irq number.
|
||||
*/
|
||||
struct nmk_gpio_platform_data {
|
||||
char *name;
|
||||
int first_gpio;
|
||||
int first_irq;
|
||||
int num_gpio;
|
||||
u32 (*get_secondary_status)(unsigned int bank);
|
||||
void (*set_ioforce)(bool enable);
|
||||
bool supports_sleepmode;
|
||||
};
|
||||
|
||||
#endif /* __PLAT_NOMADIK_GPIO */
|
||||
Loading…
Reference in New Issue
Block a user