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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge branch 'net-dsa-Global-2-cosmetics'
Vivien Didelot says: ==================== net: dsa: Global 2 cosmetics Similarly to what has been done for the Port and Global 1 registers, this patch series prefixes and documents the macros of Global 2. It brings no functional changes except for 1/10 which fixes the IRL init for 88E6390 family. Changes in v2: make *_g2_irl_init_all static inline without NET_DSA_MV88E6XXX_GLOBAL2 and compile test with and without the symbol. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
da16349d7e
@ -941,6 +941,26 @@ static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
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return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
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}
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static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
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{
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int port;
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int err;
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if (!chip->info->ops->irl_init_all)
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return 0;
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for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
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/* Disable ingress rate limiting by resetting all per port
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* ingress rate limit resources to their initial state.
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*/
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err = chip->info->ops->irl_init_all(chip, port);
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if (err)
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return err;
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}
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return 0;
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}
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static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
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{
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u16 pvlan = 0;
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@ -2102,6 +2122,10 @@ static int mv88e6xxx_setup(struct dsa_switch *ds)
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goto unlock;
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}
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err = mv88e6xxx_irl_setup(chip);
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if (err)
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goto unlock;
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err = mv88e6xxx_phy_setup(chip);
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if (err)
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goto unlock;
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@ -2339,6 +2363,7 @@ static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
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static const struct mv88e6xxx_ops mv88e6085_ops = {
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/* MV88E6XXX_FAMILY_6097 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
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.phy_read = mv88e6185_phy_ppu_read,
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.phy_write = mv88e6185_phy_ppu_write,
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@ -2393,6 +2418,7 @@ static const struct mv88e6xxx_ops mv88e6095_ops = {
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static const struct mv88e6xxx_ops mv88e6097_ops = {
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/* MV88E6XXX_FAMILY_6097 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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.phy_read = mv88e6xxx_g2_smi_phy_read,
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.phy_write = mv88e6xxx_g2_smi_phy_write,
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@ -2423,6 +2449,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
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static const struct mv88e6xxx_ops mv88e6123_ops = {
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/* MV88E6XXX_FAMILY_6165 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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.phy_read = mv88e6xxx_g2_smi_phy_read,
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.phy_write = mv88e6xxx_g2_smi_phy_write,
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@ -2479,6 +2506,7 @@ static const struct mv88e6xxx_ops mv88e6131_ops = {
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static const struct mv88e6xxx_ops mv88e6141_ops = {
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/* MV88E6XXX_FAMILY_6341 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom8,
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.set_eeprom = mv88e6xxx_g2_set_eeprom8,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -2512,6 +2540,7 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {
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static const struct mv88e6xxx_ops mv88e6161_ops = {
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/* MV88E6XXX_FAMILY_6165 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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.phy_read = mv88e6xxx_g2_smi_phy_read,
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.phy_write = mv88e6xxx_g2_smi_phy_write,
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@ -2542,6 +2571,7 @@ static const struct mv88e6xxx_ops mv88e6161_ops = {
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static const struct mv88e6xxx_ops mv88e6165_ops = {
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/* MV88E6XXX_FAMILY_6165 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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.phy_read = mv88e6165_phy_read,
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.phy_write = mv88e6165_phy_write,
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@ -2565,6 +2595,7 @@ static const struct mv88e6xxx_ops mv88e6165_ops = {
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static const struct mv88e6xxx_ops mv88e6171_ops = {
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/* MV88E6XXX_FAMILY_6351 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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.phy_read = mv88e6xxx_g2_smi_phy_read,
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.phy_write = mv88e6xxx_g2_smi_phy_write,
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@ -2596,6 +2627,7 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {
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static const struct mv88e6xxx_ops mv88e6172_ops = {
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/* MV88E6XXX_FAMILY_6352 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom16,
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.set_eeprom = mv88e6xxx_g2_set_eeprom16,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -2630,6 +2662,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
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static const struct mv88e6xxx_ops mv88e6175_ops = {
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/* MV88E6XXX_FAMILY_6351 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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.phy_read = mv88e6xxx_g2_smi_phy_read,
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.phy_write = mv88e6xxx_g2_smi_phy_write,
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@ -2661,6 +2694,7 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {
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static const struct mv88e6xxx_ops mv88e6176_ops = {
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/* MV88E6XXX_FAMILY_6352 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom16,
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.set_eeprom = mv88e6xxx_g2_set_eeprom16,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -2722,6 +2756,7 @@ static const struct mv88e6xxx_ops mv88e6185_ops = {
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static const struct mv88e6xxx_ops mv88e6190_ops = {
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/* MV88E6XXX_FAMILY_6390 */
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.irl_init_all = mv88e6390_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom8,
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.set_eeprom = mv88e6xxx_g2_set_eeprom8,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -2755,6 +2790,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
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static const struct mv88e6xxx_ops mv88e6190x_ops = {
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/* MV88E6XXX_FAMILY_6390 */
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.irl_init_all = mv88e6390_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom8,
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.set_eeprom = mv88e6xxx_g2_set_eeprom8,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -2788,6 +2824,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
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static const struct mv88e6xxx_ops mv88e6191_ops = {
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/* MV88E6XXX_FAMILY_6390 */
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.irl_init_all = mv88e6390_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom8,
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.set_eeprom = mv88e6xxx_g2_set_eeprom8,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -2821,6 +2858,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
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static const struct mv88e6xxx_ops mv88e6240_ops = {
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/* MV88E6XXX_FAMILY_6352 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom16,
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.set_eeprom = mv88e6xxx_g2_set_eeprom16,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -2855,6 +2893,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
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static const struct mv88e6xxx_ops mv88e6290_ops = {
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/* MV88E6XXX_FAMILY_6390 */
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.irl_init_all = mv88e6390_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom8,
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.set_eeprom = mv88e6xxx_g2_set_eeprom8,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -2889,6 +2928,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
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static const struct mv88e6xxx_ops mv88e6320_ops = {
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/* MV88E6XXX_FAMILY_6320 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom16,
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.set_eeprom = mv88e6xxx_g2_set_eeprom16,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -2920,6 +2960,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops = {
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static const struct mv88e6xxx_ops mv88e6321_ops = {
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/* MV88E6XXX_FAMILY_6321 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom16,
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.set_eeprom = mv88e6xxx_g2_set_eeprom16,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -2950,6 +2991,7 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {
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static const struct mv88e6xxx_ops mv88e6341_ops = {
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/* MV88E6XXX_FAMILY_6341 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom8,
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.set_eeprom = mv88e6xxx_g2_set_eeprom8,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -2983,6 +3025,7 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
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static const struct mv88e6xxx_ops mv88e6350_ops = {
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/* MV88E6XXX_FAMILY_6351 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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.phy_read = mv88e6xxx_g2_smi_phy_read,
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.phy_write = mv88e6xxx_g2_smi_phy_write,
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@ -3014,6 +3057,7 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {
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static const struct mv88e6xxx_ops mv88e6351_ops = {
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/* MV88E6XXX_FAMILY_6351 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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.phy_read = mv88e6xxx_g2_smi_phy_read,
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.phy_write = mv88e6xxx_g2_smi_phy_write,
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@ -3045,6 +3089,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
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static const struct mv88e6xxx_ops mv88e6352_ops = {
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/* MV88E6XXX_FAMILY_6352 */
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.irl_init_all = mv88e6352_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom16,
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.set_eeprom = mv88e6xxx_g2_set_eeprom16,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -3079,6 +3124,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
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static const struct mv88e6xxx_ops mv88e6390_ops = {
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/* MV88E6XXX_FAMILY_6390 */
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.irl_init_all = mv88e6390_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom8,
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.set_eeprom = mv88e6xxx_g2_set_eeprom8,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -3115,6 +3161,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
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static const struct mv88e6xxx_ops mv88e6390x_ops = {
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/* MV88E6XXX_FAMILY_6390 */
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.irl_init_all = mv88e6390_g2_irl_init_all,
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.get_eeprom = mv88e6xxx_g2_get_eeprom8,
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.set_eeprom = mv88e6xxx_g2_set_eeprom8,
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.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
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@ -121,8 +121,6 @@ enum mv88e6xxx_cap {
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MV88E6XXX_CAP_G2_INT, /* (0x00) Interrupt Status */
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MV88E6XXX_CAP_G2_MGMT_EN_2X, /* (0x02) MGMT Enable Register 2x */
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MV88E6XXX_CAP_G2_MGMT_EN_0X, /* (0x03) MGMT Enable Register 0x */
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MV88E6XXX_CAP_G2_IRL_CMD, /* (0x09) Ingress Rate Command */
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MV88E6XXX_CAP_G2_IRL_DATA, /* (0x0a) Ingress Rate Data */
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MV88E6XXX_CAP_G2_POT, /* (0x0f) Priority Override Table */
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/* Per VLAN Spanning Tree Unit (STU).
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@ -149,15 +147,8 @@ enum mv88e6xxx_cap {
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#define MV88E6XXX_FLAG_G2_INT BIT_ULL(MV88E6XXX_CAP_G2_INT)
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#define MV88E6XXX_FLAG_G2_MGMT_EN_2X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_2X)
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#define MV88E6XXX_FLAG_G2_MGMT_EN_0X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_0X)
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#define MV88E6XXX_FLAG_G2_IRL_CMD BIT_ULL(MV88E6XXX_CAP_G2_IRL_CMD)
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#define MV88E6XXX_FLAG_G2_IRL_DATA BIT_ULL(MV88E6XXX_CAP_G2_IRL_DATA)
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#define MV88E6XXX_FLAG_G2_POT BIT_ULL(MV88E6XXX_CAP_G2_POT)
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/* Ingress Rate Limit unit */
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#define MV88E6XXX_FLAGS_IRL \
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(MV88E6XXX_FLAG_G2_IRL_CMD | \
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MV88E6XXX_FLAG_G2_IRL_DATA)
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/* Multi-chip Addressing Mode */
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#define MV88E6XXX_FLAGS_MULTI_CHIP \
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(MV88E6XXX_FLAG_SMI_CMD | \
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@ -175,7 +166,6 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_G2_POT | \
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MV88E6XXX_FLAGS_IRL | \
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MV88E6XXX_FLAGS_MULTI_CHIP)
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#define MV88E6XXX_FLAGS_FAMILY_6165 \
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@ -185,7 +175,6 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_G2_POT | \
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MV88E6XXX_FLAGS_IRL | \
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MV88E6XXX_FLAGS_MULTI_CHIP)
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#define MV88E6XXX_FLAGS_FAMILY_6185 \
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@ -200,7 +189,6 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_G2_POT | \
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MV88E6XXX_FLAGS_IRL | \
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MV88E6XXX_FLAGS_MULTI_CHIP)
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#define MV88E6XXX_FLAGS_FAMILY_6341 \
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@ -209,7 +197,6 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_INT | \
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MV88E6XXX_FLAG_G2_POT | \
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MV88E6XXX_FLAGS_IRL | \
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MV88E6XXX_FLAGS_MULTI_CHIP)
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#define MV88E6XXX_FLAGS_FAMILY_6351 \
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@ -219,7 +206,6 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_G2_POT | \
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MV88E6XXX_FLAGS_IRL | \
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MV88E6XXX_FLAGS_MULTI_CHIP)
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#define MV88E6XXX_FLAGS_FAMILY_6352 \
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@ -230,14 +216,12 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_G2_POT | \
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MV88E6XXX_FLAGS_IRL | \
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MV88E6XXX_FLAGS_MULTI_CHIP)
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#define MV88E6XXX_FLAGS_FAMILY_6390 \
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(MV88E6XXX_FLAG_EEE | \
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MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_INT | \
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MV88E6XXX_FLAGS_IRL | \
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MV88E6XXX_FLAGS_MULTI_CHIP)
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struct mv88e6xxx_ops;
|
||||
@ -358,6 +342,9 @@ struct mv88e6xxx_mdio_bus {
|
||||
};
|
||||
|
||||
struct mv88e6xxx_ops {
|
||||
/* Ingress Rate Limit unit (IRL) operations */
|
||||
int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
|
||||
|
||||
int (*get_eeprom)(struct mv88e6xxx_chip *chip,
|
||||
struct ethtool_eeprom *eeprom, u8 *data);
|
||||
int (*set_eeprom)(struct mv88e6xxx_chip *chip,
|
||||
|
||||
@ -1,6 +1,5 @@
|
||||
/*
|
||||
* Marvell 88E6xxx Switch Global 2 Registers support (device address
|
||||
* 0x1C)
|
||||
* Marvell 88E6xxx Switch Global 2 Registers support
|
||||
*
|
||||
* Copyright (c) 2008 Marvell Semiconductor
|
||||
*
|
||||
@ -13,6 +12,7 @@
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irqdomain.h>
|
||||
|
||||
@ -22,22 +22,22 @@
|
||||
|
||||
static int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
|
||||
{
|
||||
return mv88e6xxx_read(chip, ADDR_GLOBAL2, reg, val);
|
||||
return mv88e6xxx_read(chip, MV88E6XXX_G2, reg, val);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
|
||||
{
|
||||
return mv88e6xxx_write(chip, ADDR_GLOBAL2, reg, val);
|
||||
return mv88e6xxx_write(chip, MV88E6XXX_G2, reg, val);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
|
||||
{
|
||||
return mv88e6xxx_update(chip, ADDR_GLOBAL2, reg, update);
|
||||
return mv88e6xxx_update(chip, MV88E6XXX_G2, reg, update);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
|
||||
{
|
||||
return mv88e6xxx_wait(chip, ADDR_GLOBAL2, reg, mask);
|
||||
return mv88e6xxx_wait(chip, MV88E6XXX_G2, reg, mask);
|
||||
}
|
||||
|
||||
/* Offset 0x02: Management Enable 2x */
|
||||
@ -51,7 +51,7 @@ int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
|
||||
* addresses matching 01:80:c2:00:00:2x as MGMT.
|
||||
*/
|
||||
if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
|
||||
err = mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_2X, 0xffff);
|
||||
err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_2X, 0xffff);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
@ -60,7 +60,8 @@ int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
|
||||
* addresses matching 01:80:c2:00:00:0x as MGMT.
|
||||
*/
|
||||
if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X))
|
||||
return mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_0X, 0xffff);
|
||||
return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_0X,
|
||||
0xffff);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -72,7 +73,7 @@ static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
|
||||
{
|
||||
u16 val = (target << 8) | (port & 0xf);
|
||||
|
||||
return mv88e6xxx_g2_update(chip, GLOBAL2_DEVICE_MAPPING, val);
|
||||
return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_DEVICE_MAPPING, val);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
|
||||
@ -101,15 +102,14 @@ static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
|
||||
/* Offset 0x07: Trunk Mask Table register */
|
||||
|
||||
static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
|
||||
bool hask, u16 mask)
|
||||
bool hash, u16 mask)
|
||||
{
|
||||
const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
|
||||
u16 val = (num << 12) | (mask & port_mask);
|
||||
u16 val = (num << 12) | (mask & mv88e6xxx_port_mask(chip));
|
||||
|
||||
if (hask)
|
||||
val |= GLOBAL2_TRUNK_MASK_HASK;
|
||||
if (hash)
|
||||
val |= MV88E6XXX_G2_TRUNK_MASK_HASH;
|
||||
|
||||
return mv88e6xxx_g2_update(chip, GLOBAL2_TRUNK_MASK, val);
|
||||
return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_TRUNK_MASK, val);
|
||||
}
|
||||
|
||||
/* Offset 0x08: Trunk Mapping Table register */
|
||||
@ -120,7 +120,7 @@ static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
|
||||
const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
|
||||
u16 val = (id << 11) | (map & port_mask);
|
||||
|
||||
return mv88e6xxx_g2_update(chip, GLOBAL2_TRUNK_MAPPING, val);
|
||||
return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_TRUNK_MAPPING, val);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
|
||||
@ -149,27 +149,36 @@ static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
|
||||
* Offset 0x0A: Ingress Rate Data register
|
||||
*/
|
||||
|
||||
static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
|
||||
static int mv88e6xxx_g2_irl_wait(struct mv88e6xxx_chip *chip)
|
||||
{
|
||||
int port, err;
|
||||
return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_IRL_CMD,
|
||||
MV88E6XXX_G2_IRL_CMD_BUSY);
|
||||
}
|
||||
|
||||
/* Init all Ingress Rate Limit resources of all ports */
|
||||
for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
|
||||
/* XXX newer chips (like 88E6390) have different 2-bit ops */
|
||||
err = mv88e6xxx_g2_write(chip, GLOBAL2_IRL_CMD,
|
||||
GLOBAL2_IRL_CMD_OP_INIT_ALL |
|
||||
(port << 8));
|
||||
if (err)
|
||||
break;
|
||||
static int mv88e6xxx_g2_irl_op(struct mv88e6xxx_chip *chip, u16 op, int port,
|
||||
int res, int reg)
|
||||
{
|
||||
int err;
|
||||
|
||||
/* Wait for the operation to complete */
|
||||
err = mv88e6xxx_g2_wait(chip, GLOBAL2_IRL_CMD,
|
||||
GLOBAL2_IRL_CMD_BUSY);
|
||||
if (err)
|
||||
break;
|
||||
}
|
||||
err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_IRL_CMD,
|
||||
MV88E6XXX_G2_IRL_CMD_BUSY | op | (port << 8) |
|
||||
(res << 5) | reg);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return err;
|
||||
return mv88e6xxx_g2_irl_wait(chip);
|
||||
}
|
||||
|
||||
int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
|
||||
{
|
||||
return mv88e6xxx_g2_irl_op(chip, MV88E6352_G2_IRL_CMD_OP_INIT_ALL, port,
|
||||
0, 0);
|
||||
}
|
||||
|
||||
int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
|
||||
{
|
||||
return mv88e6xxx_g2_irl_op(chip, MV88E6390_G2_IRL_CMD_OP_INIT_ALL, port,
|
||||
0, 0);
|
||||
}
|
||||
|
||||
/* Offset 0x0B: Cross-chip Port VLAN (Addr) Register
|
||||
@ -178,7 +187,8 @@ static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
|
||||
|
||||
static int mv88e6xxx_g2_pvt_op_wait(struct mv88e6xxx_chip *chip)
|
||||
{
|
||||
return mv88e6xxx_g2_wait(chip, GLOBAL2_PVT_ADDR, GLOBAL2_PVT_ADDR_BUSY);
|
||||
return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_PVT_ADDR,
|
||||
MV88E6XXX_G2_PVT_ADDR_BUSY);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_pvt_op(struct mv88e6xxx_chip *chip, int src_dev,
|
||||
@ -186,13 +196,14 @@ static int mv88e6xxx_g2_pvt_op(struct mv88e6xxx_chip *chip, int src_dev,
|
||||
{
|
||||
int err;
|
||||
|
||||
/* 9-bit Cross-chip PVT pointer: with GLOBAL2_MISC_5_BIT_PORT cleared,
|
||||
* source device is 5-bit, source port is 4-bit.
|
||||
/* 9-bit Cross-chip PVT pointer: with MV88E6XXX_G2_MISC_5_BIT_PORT
|
||||
* cleared, source device is 5-bit, source port is 4-bit.
|
||||
*/
|
||||
op |= MV88E6XXX_G2_PVT_ADDR_BUSY;
|
||||
op |= (src_dev & 0x1f) << 4;
|
||||
op |= (src_port & 0xf);
|
||||
|
||||
err = mv88e6xxx_g2_write(chip, GLOBAL2_PVT_ADDR, op);
|
||||
err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_ADDR, op);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
@ -208,12 +219,12 @@ int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = mv88e6xxx_g2_write(chip, GLOBAL2_PVT_DATA, data);
|
||||
err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_DATA, data);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return mv88e6xxx_g2_pvt_op(chip, src_dev, src_port,
|
||||
GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN);
|
||||
MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN);
|
||||
}
|
||||
|
||||
/* Offset 0x0D: Switch MAC/WoL/WoF register */
|
||||
@ -223,7 +234,7 @@ static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
|
||||
{
|
||||
u16 val = (pointer << 8) | data;
|
||||
|
||||
return mv88e6xxx_g2_update(chip, GLOBAL2_SWITCH_MAC, val);
|
||||
return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_SWITCH_MAC, val);
|
||||
}
|
||||
|
||||
int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
|
||||
@ -246,7 +257,7 @@ static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
|
||||
{
|
||||
u16 val = (pointer << 8) | (data & 0x7);
|
||||
|
||||
return mv88e6xxx_g2_update(chip, GLOBAL2_PRIO_OVERRIDE, val);
|
||||
return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_PRIO_OVERRIDE, val);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
|
||||
@ -270,16 +281,17 @@ static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
|
||||
|
||||
static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
|
||||
{
|
||||
return mv88e6xxx_g2_wait(chip, GLOBAL2_EEPROM_CMD,
|
||||
GLOBAL2_EEPROM_CMD_BUSY |
|
||||
GLOBAL2_EEPROM_CMD_RUNNING);
|
||||
return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_EEPROM_CMD,
|
||||
MV88E6XXX_G2_EEPROM_CMD_BUSY |
|
||||
MV88E6XXX_G2_EEPROM_CMD_RUNNING);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_CMD, cmd);
|
||||
err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_EEPROM_CMD,
|
||||
MV88E6XXX_G2_EEPROM_CMD_BUSY | cmd);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
@ -289,14 +301,14 @@ static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
|
||||
static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip,
|
||||
u16 addr, u8 *data)
|
||||
{
|
||||
u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ;
|
||||
u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ;
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_g2_eeprom_wait(chip);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_ADDR, addr);
|
||||
err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
@ -304,7 +316,7 @@ static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip,
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_CMD, &cmd);
|
||||
err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &cmd);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
@ -316,14 +328,15 @@ static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip,
|
||||
static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip,
|
||||
u16 addr, u8 data)
|
||||
{
|
||||
u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | GLOBAL2_EEPROM_CMD_WRITE_EN;
|
||||
u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE |
|
||||
MV88E6XXX_G2_EEPROM_CMD_WRITE_EN;
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_g2_eeprom_wait(chip);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_ADDR, addr);
|
||||
err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
@ -333,7 +346,7 @@ static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip,
|
||||
static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
|
||||
u8 addr, u16 *data)
|
||||
{
|
||||
u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
|
||||
u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ | addr;
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_g2_eeprom_wait(chip);
|
||||
@ -344,20 +357,20 @@ static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_DATA, data);
|
||||
return mv88e6xxx_g2_read(chip, MV88E6352_G2_EEPROM_DATA, data);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
|
||||
u8 addr, u16 data)
|
||||
{
|
||||
u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
|
||||
u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE | addr;
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_g2_eeprom_wait(chip);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_DATA, data);
|
||||
err = mv88e6xxx_g2_write(chip, MV88E6352_G2_EEPROM_DATA, data);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
@ -469,11 +482,11 @@ int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
|
||||
int err;
|
||||
|
||||
/* Ensure the RO WriteEn bit is set */
|
||||
err = mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_CMD, &val);
|
||||
err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &val);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
|
||||
if (!(val & MV88E6XXX_G2_EEPROM_CMD_WRITE_EN))
|
||||
return -EROFS;
|
||||
|
||||
eeprom->len = 0;
|
||||
@ -532,178 +545,213 @@ int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
|
||||
|
||||
static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
|
||||
{
|
||||
return mv88e6xxx_g2_wait(chip, GLOBAL2_SMI_PHY_CMD,
|
||||
GLOBAL2_SMI_PHY_CMD_BUSY);
|
||||
return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_SMI_PHY_CMD,
|
||||
MV88E6XXX_G2_SMI_PHY_CMD_BUSY);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_CMD, cmd);
|
||||
err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_CMD,
|
||||
MV88E6XXX_G2_SMI_PHY_CMD_BUSY | cmd);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return mv88e6xxx_g2_smi_phy_wait(chip);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_smi_phy_write_addr(struct mv88e6xxx_chip *chip,
|
||||
int addr, int device, int reg,
|
||||
bool external)
|
||||
static int mv88e6xxx_g2_smi_phy_access(struct mv88e6xxx_chip *chip,
|
||||
bool external, bool c45, u16 op, int dev,
|
||||
int reg)
|
||||
{
|
||||
int cmd = SMI_CMD_OP_45_WRITE_ADDR | (addr << 5) | device;
|
||||
int err;
|
||||
u16 cmd = op;
|
||||
|
||||
if (external)
|
||||
cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
|
||||
cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL;
|
||||
else
|
||||
cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL; /* empty mask */
|
||||
|
||||
err = mv88e6xxx_g2_smi_phy_wait(chip);
|
||||
if (err)
|
||||
return err;
|
||||
if (c45)
|
||||
cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_45; /* empty mask */
|
||||
else
|
||||
cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_22;
|
||||
|
||||
err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, reg);
|
||||
if (err)
|
||||
return err;
|
||||
dev <<= __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK);
|
||||
cmd |= dev & MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK;
|
||||
cmd |= reg & MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK;
|
||||
|
||||
return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
|
||||
int addr, int reg_c45, u16 *val,
|
||||
bool external)
|
||||
static int mv88e6xxx_g2_smi_phy_access_c22(struct mv88e6xxx_chip *chip,
|
||||
bool external, u16 op, int dev,
|
||||
int reg)
|
||||
{
|
||||
int device = (reg_c45 >> 16) & 0x1f;
|
||||
int reg = reg_c45 & 0xffff;
|
||||
int err;
|
||||
u16 cmd;
|
||||
|
||||
err = mv88e6xxx_g2_smi_phy_write_addr(chip, addr, device, reg,
|
||||
external);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
cmd = GLOBAL2_SMI_PHY_CMD_OP_45_READ_DATA | (addr << 5) | device;
|
||||
|
||||
if (external)
|
||||
cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
|
||||
|
||||
err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = *val;
|
||||
|
||||
return 0;
|
||||
return mv88e6xxx_g2_smi_phy_access(chip, external, false, op, dev, reg);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip,
|
||||
int addr, int reg, u16 *val,
|
||||
bool external)
|
||||
/* IEEE 802.3 Clause 22 Read Data Register */
|
||||
static int mv88e6xxx_g2_smi_phy_read_data_c22(struct mv88e6xxx_chip *chip,
|
||||
bool external, int dev, int reg,
|
||||
u16 *data)
|
||||
{
|
||||
u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg;
|
||||
u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA;
|
||||
int err;
|
||||
|
||||
if (external)
|
||||
cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
|
||||
|
||||
err = mv88e6xxx_g2_smi_phy_wait(chip);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
|
||||
err = mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val);
|
||||
return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
|
||||
}
|
||||
|
||||
int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
|
||||
struct mii_bus *bus,
|
||||
/* IEEE 802.3 Clause 22 Write Data Register */
|
||||
static int mv88e6xxx_g2_smi_phy_write_data_c22(struct mv88e6xxx_chip *chip,
|
||||
bool external, int dev, int reg,
|
||||
u16 data)
|
||||
{
|
||||
u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA;
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_g2_smi_phy_wait(chip);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_smi_phy_access_c45(struct mv88e6xxx_chip *chip,
|
||||
bool external, u16 op, int port,
|
||||
int dev)
|
||||
{
|
||||
return mv88e6xxx_g2_smi_phy_access(chip, external, true, op, port, dev);
|
||||
}
|
||||
|
||||
/* IEEE 802.3 Clause 45 Write Address Register */
|
||||
static int mv88e6xxx_g2_smi_phy_write_addr_c45(struct mv88e6xxx_chip *chip,
|
||||
bool external, int port, int dev,
|
||||
int addr)
|
||||
{
|
||||
u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR;
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_g2_smi_phy_wait(chip);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, addr);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
|
||||
}
|
||||
|
||||
/* IEEE 802.3 Clause 45 Read Data Register */
|
||||
static int mv88e6xxx_g2_smi_phy_read_data_c45(struct mv88e6xxx_chip *chip,
|
||||
bool external, int port, int dev,
|
||||
u16 *data)
|
||||
{
|
||||
u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA;
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
|
||||
bool external, int port, int reg,
|
||||
u16 *data)
|
||||
{
|
||||
int dev = (reg >> 16) & 0x1f;
|
||||
int addr = reg & 0xffff;
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
|
||||
addr);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, dev,
|
||||
data);
|
||||
}
|
||||
|
||||
/* IEEE 802.3 Clause 45 Write Data Register */
|
||||
static int mv88e6xxx_g2_smi_phy_write_data_c45(struct mv88e6xxx_chip *chip,
|
||||
bool external, int port, int dev,
|
||||
u16 data)
|
||||
{
|
||||
u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA;
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
|
||||
bool external, int port, int reg,
|
||||
u16 data)
|
||||
{
|
||||
int dev = (reg >> 16) & 0x1f;
|
||||
int addr = reg & 0xffff;
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
|
||||
addr);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, dev,
|
||||
data);
|
||||
}
|
||||
|
||||
int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
|
||||
int addr, int reg, u16 *val)
|
||||
{
|
||||
struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
|
||||
bool external = mdio_bus->external;
|
||||
|
||||
if (reg & MII_ADDR_C45)
|
||||
return mv88e6xxx_g2_smi_phy_read_c45(chip, addr, reg, val,
|
||||
external);
|
||||
return mv88e6xxx_g2_smi_phy_read_c22(chip, addr, reg, val, external);
|
||||
return mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, reg,
|
||||
val);
|
||||
|
||||
return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg,
|
||||
val);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
|
||||
int addr, int reg_c45, u16 val,
|
||||
bool external)
|
||||
{
|
||||
int device = (reg_c45 >> 16) & 0x1f;
|
||||
int reg = reg_c45 & 0xffff;
|
||||
int err;
|
||||
u16 cmd;
|
||||
|
||||
err = mv88e6xxx_g2_smi_phy_write_addr(chip, addr, device, reg,
|
||||
external);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
cmd = GLOBAL2_SMI_PHY_CMD_OP_45_WRITE_DATA | (addr << 5) | device;
|
||||
|
||||
if (external)
|
||||
cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
|
||||
|
||||
err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, val);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip,
|
||||
int addr, int reg, u16 val,
|
||||
bool external)
|
||||
{
|
||||
u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg;
|
||||
int err;
|
||||
|
||||
if (external)
|
||||
cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
|
||||
|
||||
err = mv88e6xxx_g2_smi_phy_wait(chip);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, val);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
|
||||
}
|
||||
|
||||
int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
|
||||
struct mii_bus *bus,
|
||||
int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
|
||||
int addr, int reg, u16 val)
|
||||
{
|
||||
struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
|
||||
bool external = mdio_bus->external;
|
||||
|
||||
if (reg & MII_ADDR_C45)
|
||||
return mv88e6xxx_g2_smi_phy_write_c45(chip, addr, reg, val,
|
||||
external);
|
||||
return mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, reg,
|
||||
val);
|
||||
|
||||
return mv88e6xxx_g2_smi_phy_write_c22(chip, addr, reg, val, external);
|
||||
return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg,
|
||||
val);
|
||||
}
|
||||
|
||||
static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
|
||||
{
|
||||
u16 reg;
|
||||
|
||||
mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®);
|
||||
mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®);
|
||||
|
||||
dev_info(chip->dev, "Watchdog event: 0x%04x", reg);
|
||||
|
||||
@ -714,20 +762,20 @@ static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip)
|
||||
{
|
||||
u16 reg;
|
||||
|
||||
mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®);
|
||||
mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®);
|
||||
|
||||
reg &= ~(GLOBAL2_WDOG_CONTROL_EGRESS_ENABLE |
|
||||
GLOBAL2_WDOG_CONTROL_QC_ENABLE);
|
||||
reg &= ~(MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE |
|
||||
MV88E6352_G2_WDOG_CTL_QC_ENABLE);
|
||||
|
||||
mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL, reg);
|
||||
mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL, reg);
|
||||
}
|
||||
|
||||
static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip)
|
||||
{
|
||||
return mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL,
|
||||
GLOBAL2_WDOG_CONTROL_EGRESS_ENABLE |
|
||||
GLOBAL2_WDOG_CONTROL_QC_ENABLE |
|
||||
GLOBAL2_WDOG_CONTROL_SWRESET);
|
||||
return mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL,
|
||||
MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE |
|
||||
MV88E6352_G2_WDOG_CTL_QC_ENABLE |
|
||||
MV88E6352_G2_WDOG_CTL_SWRESET);
|
||||
}
|
||||
|
||||
const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {
|
||||
@ -738,12 +786,12 @@ const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {
|
||||
|
||||
static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip)
|
||||
{
|
||||
return mv88e6xxx_g2_update(chip, GLOBAL2_WDOG_CONTROL,
|
||||
GLOBAL2_WDOG_INT_ENABLE |
|
||||
GLOBAL2_WDOG_CUT_THROUGH |
|
||||
GLOBAL2_WDOG_QUEUE_CONTROLLER |
|
||||
GLOBAL2_WDOG_EGRESS |
|
||||
GLOBAL2_WDOG_FORCE_IRQ);
|
||||
return mv88e6xxx_g2_update(chip, MV88E6390_G2_WDOG_CTL,
|
||||
MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE |
|
||||
MV88E6390_G2_WDOG_CTL_CUT_THROUGH |
|
||||
MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER |
|
||||
MV88E6390_G2_WDOG_CTL_EGRESS |
|
||||
MV88E6390_G2_WDOG_CTL_FORCE_IRQ);
|
||||
}
|
||||
|
||||
static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
|
||||
@ -751,17 +799,19 @@ static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
|
||||
int err;
|
||||
u16 reg;
|
||||
|
||||
mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL, GLOBAL2_WDOG_EVENT);
|
||||
err = mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®);
|
||||
mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
|
||||
MV88E6390_G2_WDOG_CTL_PTR_EVENT);
|
||||
err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®);
|
||||
|
||||
dev_info(chip->dev, "Watchdog event: 0x%04x",
|
||||
reg & GLOBAL2_WDOG_DATA_MASK);
|
||||
reg & MV88E6390_G2_WDOG_CTL_DATA_MASK);
|
||||
|
||||
mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL, GLOBAL2_WDOG_HISTORY);
|
||||
err = mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®);
|
||||
mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
|
||||
MV88E6390_G2_WDOG_CTL_PTR_HISTORY);
|
||||
err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®);
|
||||
|
||||
dev_info(chip->dev, "Watchdog history: 0x%04x",
|
||||
reg & GLOBAL2_WDOG_DATA_MASK);
|
||||
reg & MV88E6390_G2_WDOG_CTL_DATA_MASK);
|
||||
|
||||
/* Trigger a software reset to try to recover the switch */
|
||||
if (chip->info->ops->reset)
|
||||
@ -774,8 +824,8 @@ static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
|
||||
|
||||
static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip)
|
||||
{
|
||||
mv88e6xxx_g2_update(chip, GLOBAL2_WDOG_CONTROL,
|
||||
GLOBAL2_WDOG_INT_ENABLE);
|
||||
mv88e6xxx_g2_update(chip, MV88E6390_G2_WDOG_CTL,
|
||||
MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE);
|
||||
}
|
||||
|
||||
const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {
|
||||
@ -813,7 +863,7 @@ static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip)
|
||||
int err;
|
||||
|
||||
chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain,
|
||||
GLOBAL2_INT_SOURCE_WATCHDOG);
|
||||
MV88E6XXX_G2_INT_SOURCE_WATCHDOG);
|
||||
if (chip->watchdog_irq < 0)
|
||||
return chip->watchdog_irq;
|
||||
|
||||
@ -840,16 +890,16 @@ static int mv88e6xxx_g2_misc_5_bit_port(struct mv88e6xxx_chip *chip,
|
||||
u16 val;
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_g2_read(chip, GLOBAL2_MISC, &val);
|
||||
err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_MISC, &val);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (port_5_bit)
|
||||
val |= GLOBAL2_MISC_5_BIT_PORT;
|
||||
val |= MV88E6XXX_G2_MISC_5_BIT_PORT;
|
||||
else
|
||||
val &= ~GLOBAL2_MISC_5_BIT_PORT;
|
||||
val &= ~MV88E6XXX_G2_MISC_5_BIT_PORT;
|
||||
|
||||
return mv88e6xxx_g2_write(chip, GLOBAL2_MISC, val);
|
||||
return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MISC, val);
|
||||
}
|
||||
|
||||
int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
|
||||
@ -883,7 +933,7 @@ static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id)
|
||||
u16 reg;
|
||||
|
||||
mutex_lock(&chip->reg_lock);
|
||||
err = mv88e6xxx_g2_read(chip, GLOBAL2_INT_SOURCE, ®);
|
||||
err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_INT_SOURCE, ®);
|
||||
mutex_unlock(&chip->reg_lock);
|
||||
if (err)
|
||||
goto out;
|
||||
@ -910,7 +960,7 @@ static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d)
|
||||
{
|
||||
struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
|
||||
|
||||
mv88e6xxx_g2_write(chip, GLOBAL2_INT_MASK, ~chip->g2_irq.masked);
|
||||
mv88e6xxx_g2_write(chip, MV88E6XXX_G2_INT_MASK, ~chip->g2_irq.masked);
|
||||
|
||||
mutex_unlock(&chip->reg_lock);
|
||||
}
|
||||
@ -1012,11 +1062,11 @@ int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
|
||||
* highest, and send all special multicast frames to the CPU
|
||||
* port at the highest priority.
|
||||
*/
|
||||
reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
|
||||
reg = MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI | (0x7 << 4);
|
||||
if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
|
||||
mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
|
||||
reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
|
||||
err = mv88e6xxx_g2_write(chip, GLOBAL2_SWITCH_MGMT, reg);
|
||||
reg |= MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU | 0x7;
|
||||
err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, reg);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
@ -1030,15 +1080,6 @@ int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
|
||||
/* Disable ingress rate limiting by resetting all per port
|
||||
* ingress rate limit resources to their initial state.
|
||||
*/
|
||||
err = mv88e6xxx_g2_clear_irl(chip);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
|
||||
/* Clear the priority override table. */
|
||||
err = mv88e6xxx_g2_clear_pot(chip);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Marvell 88E6xxx Switch Global 2 Registers support (device address 0x1C)
|
||||
* Marvell 88E6xxx Switch Global 2 Registers support
|
||||
*
|
||||
* Copyright (c) 2008 Marvell Semiconductor
|
||||
*
|
||||
@ -17,108 +17,198 @@
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#define ADDR_GLOBAL2 0x1c
|
||||
#define MV88E6XXX_G2 0x1c
|
||||
|
||||
#define GLOBAL2_INT_SOURCE 0x00
|
||||
#define GLOBAL2_INT_SOURCE_WATCHDOG 15
|
||||
#define GLOBAL2_INT_MASK 0x01
|
||||
#define GLOBAL2_MGMT_EN_2X 0x02
|
||||
#define GLOBAL2_MGMT_EN_0X 0x03
|
||||
#define GLOBAL2_FLOW_CONTROL 0x04
|
||||
#define GLOBAL2_SWITCH_MGMT 0x05
|
||||
#define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
|
||||
#define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14)
|
||||
#define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13)
|
||||
#define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
|
||||
#define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3)
|
||||
#define GLOBAL2_DEVICE_MAPPING 0x06
|
||||
#define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15)
|
||||
#define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8
|
||||
#define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f
|
||||
#define GLOBAL2_TRUNK_MASK 0x07
|
||||
#define GLOBAL2_TRUNK_MASK_UPDATE BIT(15)
|
||||
#define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12
|
||||
#define GLOBAL2_TRUNK_MASK_HASK BIT(11)
|
||||
#define GLOBAL2_TRUNK_MAPPING 0x08
|
||||
#define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15)
|
||||
#define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11
|
||||
#define GLOBAL2_IRL_CMD 0x09
|
||||
#define GLOBAL2_IRL_CMD_BUSY BIT(15)
|
||||
#define GLOBAL2_IRL_CMD_OP_INIT_ALL ((0x001 << 12) | GLOBAL2_IRL_CMD_BUSY)
|
||||
#define GLOBAL2_IRL_CMD_OP_INIT_SEL ((0x010 << 12) | GLOBAL2_IRL_CMD_BUSY)
|
||||
#define GLOBAL2_IRL_CMD_OP_WRITE_SEL ((0x011 << 12) | GLOBAL2_IRL_CMD_BUSY)
|
||||
#define GLOBAL2_IRL_CMD_OP_READ_SEL ((0x100 << 12) | GLOBAL2_IRL_CMD_BUSY)
|
||||
#define GLOBAL2_IRL_DATA 0x0a
|
||||
#define GLOBAL2_PVT_ADDR 0x0b
|
||||
#define GLOBAL2_PVT_ADDR_BUSY BIT(15)
|
||||
#define GLOBAL2_PVT_ADDR_OP_INIT_ONES ((0x01 << 12) | GLOBAL2_PVT_ADDR_BUSY)
|
||||
#define GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN ((0x03 << 12) | GLOBAL2_PVT_ADDR_BUSY)
|
||||
#define GLOBAL2_PVT_ADDR_OP_READ ((0x04 << 12) | GLOBAL2_PVT_ADDR_BUSY)
|
||||
#define GLOBAL2_PVT_DATA 0x0c
|
||||
#define GLOBAL2_SWITCH_MAC 0x0d
|
||||
#define GLOBAL2_ATU_STATS 0x0e
|
||||
#define GLOBAL2_PRIO_OVERRIDE 0x0f
|
||||
#define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7)
|
||||
#define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4
|
||||
#define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3)
|
||||
#define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0
|
||||
#define GLOBAL2_EEPROM_CMD 0x14
|
||||
#define GLOBAL2_EEPROM_CMD_BUSY BIT(15)
|
||||
#define GLOBAL2_EEPROM_CMD_OP_WRITE ((0x3 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
|
||||
#define GLOBAL2_EEPROM_CMD_OP_READ ((0x4 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
|
||||
#define GLOBAL2_EEPROM_CMD_OP_LOAD ((0x6 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
|
||||
#define GLOBAL2_EEPROM_CMD_RUNNING BIT(11)
|
||||
#define GLOBAL2_EEPROM_CMD_WRITE_EN BIT(10)
|
||||
#define GLOBAL2_EEPROM_CMD_ADDR_MASK 0xff
|
||||
#define GLOBAL2_EEPROM_DATA 0x15
|
||||
#define GLOBAL2_EEPROM_ADDR 0x15 /* 6390, 6341 */
|
||||
#define GLOBAL2_PTP_AVB_OP 0x16
|
||||
#define GLOBAL2_PTP_AVB_DATA 0x17
|
||||
#define GLOBAL2_SMI_PHY_CMD 0x18
|
||||
#define GLOBAL2_SMI_PHY_CMD_BUSY BIT(15)
|
||||
#define GLOBAL2_SMI_PHY_CMD_EXTERNAL BIT(13)
|
||||
#define GLOBAL2_SMI_PHY_CMD_MODE_22 BIT(12)
|
||||
#define GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA ((0x1 << 10) | \
|
||||
GLOBAL2_SMI_PHY_CMD_MODE_22 | \
|
||||
GLOBAL2_SMI_PHY_CMD_BUSY)
|
||||
#define GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA ((0x2 << 10) | \
|
||||
GLOBAL2_SMI_PHY_CMD_MODE_22 | \
|
||||
GLOBAL2_SMI_PHY_CMD_BUSY)
|
||||
#define GLOBAL2_SMI_PHY_CMD_OP_45_WRITE_ADDR ((0x0 << 10) | \
|
||||
GLOBAL2_SMI_PHY_CMD_BUSY)
|
||||
#define GLOBAL2_SMI_PHY_CMD_OP_45_WRITE_DATA ((0x1 << 10) | \
|
||||
GLOBAL2_SMI_PHY_CMD_BUSY)
|
||||
#define GLOBAL2_SMI_PHY_CMD_OP_45_READ_DATA ((0x3 << 10) | \
|
||||
GLOBAL2_SMI_PHY_CMD_BUSY)
|
||||
/* Offset 0x00: Interrupt Source Register */
|
||||
#define MV88E6XXX_G2_INT_SOURCE 0x00
|
||||
#define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15
|
||||
|
||||
#define GLOBAL2_SMI_PHY_DATA 0x19
|
||||
#define GLOBAL2_SCRATCH_MISC 0x1a
|
||||
#define GLOBAL2_SCRATCH_BUSY BIT(15)
|
||||
#define GLOBAL2_SCRATCH_REGISTER_SHIFT 8
|
||||
#define GLOBAL2_SCRATCH_VALUE_MASK 0xff
|
||||
#define GLOBAL2_WDOG_CONTROL 0x1b
|
||||
#define GLOBAL2_WDOG_CONTROL_EGRESS_EVENT BIT(7)
|
||||
#define GLOBAL2_WDOG_CONTROL_RMU_TIMEOUT BIT(6)
|
||||
#define GLOBAL2_WDOG_CONTROL_QC_ENABLE BIT(5)
|
||||
#define GLOBAL2_WDOG_CONTROL_EGRESS_HISTORY BIT(4)
|
||||
#define GLOBAL2_WDOG_CONTROL_EGRESS_ENABLE BIT(3)
|
||||
#define GLOBAL2_WDOG_CONTROL_FORCE_IRQ BIT(2)
|
||||
#define GLOBAL2_WDOG_CONTROL_HISTORY BIT(1)
|
||||
#define GLOBAL2_WDOG_CONTROL_SWRESET BIT(0)
|
||||
#define GLOBAL2_WDOG_UPDATE BIT(15)
|
||||
#define GLOBAL2_WDOG_INT_SOURCE (0x00 << 8)
|
||||
#define GLOBAL2_WDOG_INT_STATUS (0x10 << 8)
|
||||
#define GLOBAL2_WDOG_INT_ENABLE (0x11 << 8)
|
||||
#define GLOBAL2_WDOG_EVENT (0x12 << 8)
|
||||
#define GLOBAL2_WDOG_HISTORY (0x13 << 8)
|
||||
#define GLOBAL2_WDOG_DATA_MASK 0xff
|
||||
#define GLOBAL2_WDOG_CUT_THROUGH BIT(3)
|
||||
#define GLOBAL2_WDOG_QUEUE_CONTROLLER BIT(2)
|
||||
#define GLOBAL2_WDOG_EGRESS BIT(1)
|
||||
#define GLOBAL2_WDOG_FORCE_IRQ BIT(0)
|
||||
#define GLOBAL2_QOS_WEIGHT 0x1c
|
||||
#define GLOBAL2_MISC 0x1d
|
||||
#define GLOBAL2_MISC_5_BIT_PORT BIT(14)
|
||||
/* Offset 0x01: Interrupt Mask Register */
|
||||
#define MV88E6XXX_G2_INT_MASK 0x01
|
||||
|
||||
/* Offset 0x02: MGMT Enable Register 2x */
|
||||
#define MV88E6XXX_G2_MGMT_EN_2X 0x02
|
||||
|
||||
/* Offset 0x03: MGMT Enable Register 0x */
|
||||
#define MV88E6XXX_G2_MGMT_EN_0X 0x03
|
||||
|
||||
/* Offset 0x04: Flow Control Delay Register */
|
||||
#define MV88E6XXX_G2_FLOW_CTL 0x04
|
||||
|
||||
/* Offset 0x05: Switch Management Register */
|
||||
#define MV88E6XXX_G2_SWITCH_MGMT 0x05
|
||||
#define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000
|
||||
#define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000
|
||||
#define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000
|
||||
#define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080
|
||||
#define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008
|
||||
|
||||
/* Offset 0x06: Device Mapping Table Register */
|
||||
#define MV88E6XXX_G2_DEVICE_MAPPING 0x06
|
||||
#define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000
|
||||
#define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00
|
||||
#define MV88E6XXX_G2_DEVICE_MAPPING_PORT_MASK 0x000f
|
||||
|
||||
/* Offset 0x07: Trunk Mask Table Register */
|
||||
#define MV88E6XXX_G2_TRUNK_MASK 0x07
|
||||
#define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000
|
||||
#define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000
|
||||
#define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800
|
||||
|
||||
/* Offset 0x08: Trunk Mapping Table Register */
|
||||
#define MV88E6XXX_G2_TRUNK_MAPPING 0x08
|
||||
#define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000
|
||||
#define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800
|
||||
|
||||
/* Offset 0x09: Ingress Rate Command Register */
|
||||
#define MV88E6XXX_G2_IRL_CMD 0x09
|
||||
#define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000
|
||||
#define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000
|
||||
#define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000
|
||||
#define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000
|
||||
#define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000
|
||||
#define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000
|
||||
#define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000
|
||||
#define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000
|
||||
#define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000
|
||||
#define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000
|
||||
#define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000
|
||||
#define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000
|
||||
#define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00
|
||||
#define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00
|
||||
#define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0
|
||||
#define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f
|
||||
|
||||
/* Offset 0x0A: Ingress Rate Data Register */
|
||||
#define MV88E6XXX_G2_IRL_DATA 0x0a
|
||||
#define MV88E6XXX_G2_IRL_DATA_MASK 0xffff
|
||||
|
||||
/* Offset 0x0B: Cross-chip Port VLAN Register */
|
||||
#define MV88E6XXX_G2_PVT_ADDR 0x0b
|
||||
#define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000
|
||||
#define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000
|
||||
#define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000
|
||||
#define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000
|
||||
#define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000
|
||||
#define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff
|
||||
|
||||
/* Offset 0x0C: Cross-chip Port VLAN Data Register */
|
||||
#define MV88E6XXX_G2_PVT_DATA 0x0c
|
||||
#define MV88E6XXX_G2_PVT_DATA_MASK 0x7f
|
||||
|
||||
/* Offset 0x0D: Switch MAC/WoL/WoF Register */
|
||||
#define MV88E6XXX_G2_SWITCH_MAC 0x0d
|
||||
#define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000
|
||||
#define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00
|
||||
#define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff
|
||||
|
||||
/* Offset 0x0E: ATU Stats Register */
|
||||
#define MV88E6XXX_G2_ATU_STATS 0x0e
|
||||
|
||||
/* Offset 0x0F: Priority Override Table */
|
||||
#define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f
|
||||
#define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000
|
||||
#define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000
|
||||
#define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00
|
||||
#define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080
|
||||
#define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030
|
||||
#define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008
|
||||
#define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007
|
||||
|
||||
/* Offset 0x14: EEPROM Command */
|
||||
#define MV88E6XXX_G2_EEPROM_CMD 0x14
|
||||
#define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000
|
||||
#define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000
|
||||
#define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000
|
||||
#define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000
|
||||
#define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000
|
||||
#define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800
|
||||
#define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400
|
||||
#define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff
|
||||
#define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff
|
||||
|
||||
/* Offset 0x15: EEPROM Data */
|
||||
#define MV88E6352_G2_EEPROM_DATA 0x15
|
||||
#define MV88E6352_G2_EEPROM_DATA_MASK 0xffff
|
||||
|
||||
/* Offset 0x15: EEPROM Addr */
|
||||
#define MV88E6390_G2_EEPROM_ADDR 0x15
|
||||
#define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff
|
||||
|
||||
/* Offset 0x16: AVB Command Register */
|
||||
#define MV88E6352_G2_AVB_CMD 0x16
|
||||
|
||||
/* Offset 0x17: AVB Data Register */
|
||||
#define MV88E6352_G2_AVB_DATA 0x17
|
||||
|
||||
/* Offset 0x18: SMI PHY Command Register */
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD 0x18
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000
|
||||
#define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000
|
||||
#define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000
|
||||
#define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000
|
||||
#define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f
|
||||
#define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff
|
||||
|
||||
/* Offset 0x19: SMI PHY Data Register */
|
||||
#define MV88E6XXX_G2_SMI_PHY_DATA 0x19
|
||||
|
||||
/* Offset 0x1A: Scratch and Misc. Register */
|
||||
#define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a
|
||||
#define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000
|
||||
#define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00
|
||||
#define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff
|
||||
|
||||
/* Offset 0x1B: Watch Dog Control Register */
|
||||
#define MV88E6352_G2_WDOG_CTL 0x1b
|
||||
#define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080
|
||||
#define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040
|
||||
#define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020
|
||||
#define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010
|
||||
#define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008
|
||||
#define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004
|
||||
#define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002
|
||||
#define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001
|
||||
|
||||
/* Offset 0x1B: Watch Dog Control Register */
|
||||
#define MV88E6390_G2_WDOG_CTL 0x1b
|
||||
#define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000
|
||||
#define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00
|
||||
#define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000
|
||||
#define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000
|
||||
#define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100
|
||||
#define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200
|
||||
#define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300
|
||||
#define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff
|
||||
#define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008
|
||||
#define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004
|
||||
#define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002
|
||||
#define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001
|
||||
|
||||
/* Offset 0x1C: QoS Weights Register */
|
||||
#define MV88E6XXX_G2_QOS_WEIGHTS 0x1c
|
||||
#define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000
|
||||
#define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00
|
||||
#define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00
|
||||
#define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff
|
||||
|
||||
/* Offset 0x1D: Misc Register */
|
||||
#define MV88E6XXX_G2_MISC 0x1d
|
||||
#define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000
|
||||
#define MV88E6352_G2_NOEGR_POLICY 0x2000
|
||||
#define MV88E6390_G2_LAG_ID_4 0x2000
|
||||
|
||||
#ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2
|
||||
|
||||
@ -127,6 +217,9 @@ static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
|
||||
int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
|
||||
|
||||
int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
|
||||
struct mii_bus *bus,
|
||||
int addr, int reg, u16 *val);
|
||||
@ -169,6 +262,18 @@ static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip,
|
||||
int port)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip,
|
||||
int port)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
|
||||
struct mii_bus *bus,
|
||||
int addr, int reg, u16 *val)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user