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drm/i915/guc: Move doc near related definitions

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After GuC code reorg some documentation was left in wrong
place. Move it closer to corresponding definitions.

v2: use consistent name for the GuC (Sagar)

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171016144724.17244-5-michal.wajdeczko@intel.com
This commit is contained in:
Michal Wajdeczko 2017-10-16 14:47:13 +00:00 committed by Joonas Lahtinen
parent fdc6d7319e
commit d9e2e0143c
3 changed files with 16 additions and 23 deletions
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11
drivers/gpu/drm/i915/intel_guc.h
View File

@ -33,6 +33,11 @@
#include "i915_guc_reg.h" #include "i915_guc_reg.h"
#include "i915_vma.h" #include "i915_vma.h"
/*
* Top level structure of GuC. It handles firmware loading and manages client
* pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
* ExecList submission.
*/
struct intel_guc { struct intel_guc {
struct intel_uc_fw fw; struct intel_uc_fw fw;
struct intel_guc_log log; struct intel_guc_log log;
@ -83,6 +88,12 @@ static inline void intel_guc_notify(struct intel_guc *guc)
guc->notify(guc); guc->notify(guc);
} }
/*
* GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
* which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
* 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
* used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
*/
static inline u32 guc_ggtt_offset(struct i915_vma *vma) static inline u32 guc_ggtt_offset(struct i915_vma *vma)
{ {
u32 offset = i915_ggtt_offset(vma); u32 offset = i915_ggtt_offset(vma);

23
drivers/gpu/drm/i915/intel_guc_loader.c
View File

@ -29,29 +29,6 @@
#include "i915_drv.h" #include "i915_drv.h"
#include "intel_uc.h" #include "intel_uc.h"
/**
* DOC: GuC-specific firmware loader
*
* intel_guc:
* Top level structure of guc. It handles firmware loading and manages client
* pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
* ExecList submission.
*
* Firmware versioning:
* The firmware build process will generate a version header file with major and
* minor version defined. The versions are built into CSS header of firmware.
* i915 kernel driver set the minimal firmware version required per platform.
* The firmware installation package will install (symbolic link) proper version
* of firmware.
*
* GuC address space:
* GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
* which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
* 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
* used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
*
*/
#define SKL_FW_MAJOR 6 #define SKL_FW_MAJOR 6
#define SKL_FW_MINOR 1 #define SKL_FW_MINOR 1

5
drivers/gpu/drm/i915/intel_uc_fw.h
View File

@ -50,6 +50,11 @@ struct intel_uc_fw {
enum intel_uc_fw_status fetch_status; enum intel_uc_fw_status fetch_status;
enum intel_uc_fw_status load_status; enum intel_uc_fw_status load_status;
/*
* The firmware build process will generate a version header file with major and
* minor version defined. The versions are built into CSS header of firmware.
* i915 kernel driver set the minimal firmware version required per platform.
*/
u16 major_ver_wanted; u16 major_ver_wanted;
u16 minor_ver_wanted; u16 minor_ver_wanted;
u16 major_ver_found; u16 major_ver_found;