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drm/i915/ringbuffer: Remove irq-seqno w/a for gen6 xcs

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The MI_FLUSH_DW does appear coherent with the following
MI_USER_INTERRUPT, but only on Sandybridge. Ivybridge requires a heavier
hammer, but on Sandybridge we can stop requiring the irq_seqno barrier.

Testcase: igt/gem_sync
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181228171641.16531-3-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson 2018-12-28 17:16:38 +00:00
parent 2f0c733b35
commit d9cad2206a
1 changed files with 4 additions and 2 deletions
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6
drivers/gpu/drm/i915/intel_ringbuffer.c
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@ -2260,7 +2260,8 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb;
engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz;
engine->irq_seqno_barrier = gen6_seqno_barrier;
if (!IS_GEN(dev_priv, 6))
engine->irq_seqno_barrier = gen6_seqno_barrier;
} else {
engine->emit_flush = bsd_ring_flush;
if (IS_GEN(dev_priv, 5))
@ -2285,7 +2286,8 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb;
engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz;
engine->irq_seqno_barrier = gen6_seqno_barrier;
if (!IS_GEN(dev_priv, 6))
engine->irq_seqno_barrier = gen6_seqno_barrier;
return intel_init_ring_buffer(engine);
}