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drm: rcar-du: Configure DPAD0 routing through last group on Gen3

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On Gen3 SoCs DPAD0 routing is configured through the last CRTC group,
unlike on Gen2 where it is configured through the first CRTC group. Fix
the driver accordingly.

Fixes: 2427b30377 ("drm: rcar-du: Add R8A7795 device support")
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
This commit is contained in:
Laurent Pinchart 2017-06-26 16:41:47 +03:00
parent 6a00a4221a
commit d99a6b5eef
1 changed files with 14 additions and 6 deletions
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20
drivers/gpu/drm/rcar-du/rcar_du_group.c
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@ -212,6 +212,9 @@ void rcar_du_group_restart(struct rcar_du_group *rgrp)
int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
{
struct rcar_du_group *rgrp;
struct rcar_du_crtc *crtc;
unsigned int index;
int ret;
if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
@ -219,17 +222,22 @@ int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
/*
* RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
* configured in the DEFR8 register of the first group. As this function
* can be called with the DU0 and DU1 CRTCs disabled, we need to enable
* the first group clock before accessing the register.
* configured in the DEFR8 register of the first group on Gen2 and the
* last group on Gen3. As this function can be called with the DU
* channels of the corresponding CRTCs disabled, we need to enable the
* group clock before accessing the register.
*/
ret = clk_prepare_enable(rcdu->crtcs[0].clock);
index = rcdu->info->gen < 3 ? 0 : DIV_ROUND_UP(rcdu->num_crtcs, 2) - 1;
rgrp = &rcdu->groups[index];
crtc = &rcdu->crtcs[index * 2];
ret = clk_prepare_enable(crtc->clock);
if (ret < 0)
return ret;
rcar_du_group_setup_defr8(&rcdu->groups[0]);
rcar_du_group_setup_defr8(rgrp);
clk_disable_unprepare(rcdu->crtcs[0].clock);
clk_disable_unprepare(crtc->clock);
return 0;
}