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drm/amd/powerplay: use MGPU friendly err/warn/info/dbg messages

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Use dev_err/warn/info/dbg instead of pr_err/warn/info/debug.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2020-06-05 15:27:57 +08:00 committed by Alex Deucher
parent 207f0f1357
commit d9811cfc0e
7 changed files with 745 additions and 739 deletions
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70
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
View File

@ -609,7 +609,7 @@ int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
return -EOPNOTSUPP;
if (header->usStructureSize != size) {
pr_err("pp table size not matched !\n");
dev_err(smu->adev->dev, "pp table size not matched !\n");
return -EIO;
}
@ -633,7 +633,7 @@ int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
ret = smu_reset(smu);
if (ret)
pr_info("smu reset failed, ret = %d\n", ret);
dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
smu->uploading_custom_pp_table = false;
@ -847,7 +847,7 @@ static int smu_init_fb_allocations(struct smu_context *smu)
&tables[SMU_TABLE_PMSTATUSLOG].mc_address,
&tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
if (ret) {
pr_err("VRAM allocation for tool table failed!\n");
dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
return ret;
}
}
@ -876,7 +876,7 @@ static int smu_init_fb_allocations(struct smu_context *smu)
&driver_table->mc_address,
&driver_table->cpu_addr);
if (ret) {
pr_err("VRAM allocation for driver table failed!\n");
dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
&tables[SMU_TABLE_PMSTATUSLOG].mc_address,
@ -979,7 +979,7 @@ static int smu_smc_table_sw_init(struct smu_context *smu)
*/
ret = smu_init_smc_tables(smu);
if (ret) {
pr_err("Failed to init smc tables!\n");
dev_err(smu->adev->dev, "Failed to init smc tables!\n");
return ret;
}
@ -989,7 +989,7 @@ static int smu_smc_table_sw_init(struct smu_context *smu)
*/
ret = smu_init_power(smu);
if (ret) {
pr_err("Failed to init smu_init_power!\n");
dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
return ret;
}
@ -1021,13 +1021,13 @@ static int smu_smc_table_sw_fini(struct smu_context *smu)
ret = smu_fini_power(smu);
if (ret) {
pr_err("Failed to init smu_fini_power!\n");
dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
return ret;
}
ret = smu_fini_smc_tables(smu);
if (ret) {
pr_err("Failed to smu_fini_smc_tables!\n");
dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
return ret;
}
@ -1090,19 +1090,19 @@ static int smu_sw_init(void *handle)
smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
ret = smu_init_microcode(smu);
if (ret) {
pr_err("Failed to load smu firmware!\n");
dev_err(adev->dev, "Failed to load smu firmware!\n");
return ret;
}
ret = smu_smc_table_sw_init(smu);
if (ret) {
pr_err("Failed to sw init smc table!\n");
dev_err(adev->dev, "Failed to sw init smc table!\n");
return ret;
}
ret = smu_register_irq_handler(smu);
if (ret) {
pr_err("Failed to register smc irq handler!\n");
dev_err(adev->dev, "Failed to register smc irq handler!\n");
return ret;
}
@ -1117,7 +1117,7 @@ static int smu_sw_fini(void *handle)
ret = smu_smc_table_sw_fini(smu);
if (ret) {
pr_err("Failed to sw fini smc table!\n");
dev_err(adev->dev, "Failed to sw fini smc table!\n");
return ret;
}
@ -1132,7 +1132,7 @@ static int smu_smc_hw_setup(struct smu_context *smu)
int ret;
if (smu_is_dpm_running(smu) && adev->in_suspend) {
pr_info("dpm has been enabled\n");
dev_info(adev->dev, "dpm has been enabled\n");
return 0;
}
@ -1182,7 +1182,7 @@ static int smu_smc_hw_setup(struct smu_context *smu)
return ret;
if (!smu_is_dpm_running(smu))
pr_info("dpm has been disabled\n");
dev_info(adev->dev, "dpm has been disabled\n");
ret = smu_override_pcie_parameters(smu);
if (ret)
@ -1198,7 +1198,7 @@ static int smu_smc_hw_setup(struct smu_context *smu)
ret = smu_disable_umc_cdr_12gbps_workaround(smu);
if (ret) {
pr_err("Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
dev_err(adev->dev, "Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
return ret;
}
@ -1210,7 +1210,7 @@ static int smu_smc_hw_setup(struct smu_context *smu)
adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
SMU_POWER_SOURCE_DC);
if (ret) {
pr_err("Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
dev_err(adev->dev, "Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
return ret;
}
@ -1247,7 +1247,7 @@ static int smu_start_smc_engine(struct smu_context *smu)
if (smu->ppt_funcs->check_fw_status) {
ret = smu->ppt_funcs->check_fw_status(smu);
if (ret) {
pr_err("SMC is not ready\n");
dev_err(adev->dev, "SMC is not ready\n");
return ret;
}
}
@ -1274,7 +1274,7 @@ static int smu_hw_init(void *handle)
ret = smu_start_smc_engine(smu);
if (ret) {
pr_err("SMU is not ready yet!\n");
dev_err(adev->dev, "SMU is not ready yet!\n");
return ret;
}
@ -1307,7 +1307,7 @@ static int smu_hw_init(void *handle)
adev->pm.dpm_enabled = true;
pr_info("SMU is initialized successfully!\n");
dev_info(adev->dev, "SMU is initialized successfully!\n");
return 0;
@ -1360,11 +1360,11 @@ static int smu_disable_dpms(struct smu_context *smu)
features_to_disable,
0);
if (ret)
pr_err("Failed to disable smu features except BACO.\n");
dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
} else {
ret = smu_system_features_control(smu, false);
if (ret)
pr_err("Failed to disable smu features.\n");
dev_err(adev->dev, "Failed to disable smu features.\n");
}
if (adev->asic_type >= CHIP_NAVI10 &&
@ -1385,7 +1385,7 @@ static int smu_smc_hw_cleanup(struct smu_context *smu)
ret = smu_disable_thermal_alert(smu);
if (ret) {
pr_warn("Fail to stop thermal control!\n");
dev_warn(adev->dev, "Fail to stop thermal control!\n");
return ret;
}
@ -1479,11 +1479,11 @@ static int smu_resume(void *handle)
if (!smu->pm_enabled)
return 0;
pr_info("SMU is resuming...\n");
dev_info(adev->dev, "SMU is resuming...\n");
ret = smu_start_smc_engine(smu);
if (ret) {
pr_err("SMU is not ready yet!\n");
dev_err(adev->dev, "SMU is not ready yet!\n");
goto failed;
}
@ -1498,7 +1498,7 @@ static int smu_resume(void *handle)
adev->pm.dpm_enabled = true;
pr_info("SMU is resumed successfully!\n");
dev_info(adev->dev, "SMU is resumed successfully!\n");
return 0;
@ -1591,7 +1591,7 @@ int smu_get_current_clocks(struct smu_context *smu,
ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
if (ret) {
pr_err("Error in smu_get_clock_info\n");
dev_err(smu->adev->dev, "Error in smu_get_clock_info\n");
goto failed;
}
@ -1687,21 +1687,21 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
if (!skip_display_settings) {
ret = smu_display_config_changed(smu);
if (ret) {
pr_err("Failed to change display config!");
dev_err(smu->adev->dev, "Failed to change display config!");
return ret;
}
}
ret = smu_apply_clocks_adjust_rules(smu);
if (ret) {
pr_err("Failed to apply clocks adjust rules!");
dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
return ret;
}
if (!skip_display_settings) {
ret = smu_notify_smc_display_config(smu);
if (ret) {
pr_err("Failed to notify smc display config!");
dev_err(smu->adev->dev, "Failed to notify smc display config!");
return ret;
}
}
@ -1709,7 +1709,7 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
if (smu_dpm_ctx->dpm_level != level) {
ret = smu_asic_set_performance_level(smu, level);
if (ret) {
pr_err("Failed to set performance level!");
dev_err(smu->adev->dev, "Failed to set performance level!");
return ret;
}
@ -1875,7 +1875,7 @@ int smu_force_clk_levels(struct smu_context *smu,
return -EOPNOTSUPP;
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
pr_debug("force clock level is for dpm manual mode only.\n");
dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
return -EINVAL;
}
@ -1933,7 +1933,7 @@ int smu_set_mp1_state(struct smu_context *smu,
ret = smu_send_smc_msg(smu, msg, NULL);
if (ret)
pr_err("[PrepareMp1] Failed!\n");
dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
mutex_unlock(&smu->mutex);
@ -1955,7 +1955,7 @@ int smu_set_df_cstate(struct smu_context *smu,
ret = smu->ppt_funcs->set_df_cstate(smu, state);
if (ret)
pr_err("[SetDfCstate] failed!\n");
dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
mutex_unlock(&smu->mutex);
@ -1976,7 +1976,7 @@ int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
if (ret)
pr_err("[AllowXgmiPowerDown] failed!\n");
dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
mutex_unlock(&smu->mutex);
@ -2042,7 +2042,7 @@ int smu_set_ac_dc(struct smu_context *smu)
smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
SMU_POWER_SOURCE_DC);
if (ret)
pr_err("Failed to switch to %s mode!\n",
dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
smu->adev->pm.ac_power ? "AC" : "DC");
mutex_unlock(&smu->mutex);

509
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
View File

File diff suppressed because it is too large Load Diff

121
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
View File

@ -462,12 +462,12 @@ static int navi10_append_powerplay_table(struct smu_context *smu)
if (ret)
return ret;
pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
smc_dpm_table->table_header.format_revision,
smc_dpm_table->table_header.content_revision);
if (smc_dpm_table->table_header.format_revision != 4) {
pr_err("smc_dpm_info table format revision is not 4!\n");
dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n");
return -EINVAL;
}
@ -485,7 +485,7 @@ static int navi10_append_powerplay_table(struct smu_context *smu)
sizeof(*smc_dpm_table_v4_7) - sizeof(smc_dpm_table_v4_7->table_header));
break;
default:
pr_err("smc_dpm_info with unsupported content revision %d!\n",
dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",
smc_dpm_table->table_header.content_revision);
return -EINVAL;
}
@ -580,7 +580,7 @@ static int navi10_get_smu_metrics_data(struct smu_context *smu,
smu_table->metrics_table,
false);
if (ret) {
pr_info("Failed to export SMU metrics table!\n");
dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
mutex_unlock(&smu->metrics_lock);
return ret;
}
@ -1245,7 +1245,7 @@ static int navi10_get_current_activity_percent(struct smu_context *smu,
value);
break;
default:
pr_err("Invalid sensor for retrieving clock activity\n");
dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
return -EINVAL;
}
@ -1336,7 +1336,7 @@ static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
(void *)(&activity_monitor), false);
if (result) {
pr_err("[%s] Failed to get activity monitor!", __func__);
dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
return result;
}
@ -1397,7 +1397,7 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
smu->power_profile_mode = input[size];
if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
return -EINVAL;
}
@ -1407,7 +1407,7 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
(void *)(&activity_monitor), false);
if (ret) {
pr_err("[%s] Failed to get activity monitor!", __func__);
dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
return ret;
}
@ -1451,7 +1451,7 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
(void *)(&activity_monitor), true);
if (ret) {
pr_err("[%s] Failed to set activity monitor!", __func__);
dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
return ret;
}
}
@ -1529,19 +1529,19 @@ static int navi10_notify_smc_display_config(struct smu_context *smu)
min_clocks.dcef_clock_in_sr/100,
NULL);
if (ret) {
pr_err("Attempt to set divider for DCEFCLK Failed!");
dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
return ret;
}
}
} else {
pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
}
}
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
if (ret) {
pr_err("[%s] Set hard min uclk failed!", __func__);
dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
return ret;
}
}
@ -1613,7 +1613,7 @@ static int navi10_set_watermarks_table(struct smu_context *smu,
if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
ret = smu_write_watermarks_table(smu);
if (ret) {
pr_err("Failed to update WMTABLE!");
dev_err(smu->adev->dev, "Failed to update WMTABLE!");
return ret;
}
smu->watermarks_bitmap |= WATERMARKS_LOADED;
@ -1648,7 +1648,7 @@ static int navi10_thermal_get_temperature(struct smu_context *smu,
value);
break;
default:
pr_err("Invalid sensor for retrieving temp\n");
dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
return -EINVAL;
}
@ -1930,13 +1930,13 @@ static int navi10_get_power_limit(struct smu_context *smu,
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
power_src << 16, &asic_default_power_limit);
if (ret) {
pr_err("[%s] get PPT limit failed!", __func__);
dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
return ret;
}
} else {
/* the last hope to figure out the ppt limit */
if (!pptable) {
pr_err("Cannot get PPT limit due to pptable missing!");
dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
return -EINVAL;
}
asic_default_power_limit =
@ -1987,23 +1987,28 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
return 0;
}
static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
pr_debug("OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
pr_debug("OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
pr_debug("OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
pr_debug("OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
pr_debug("OD: UclkFmax: %d\n", od_table->UclkFmax);
pr_debug("OD: OverDrivePct: %d\n", od_table->OverDrivePct);
static inline void navi10_dump_od_table(struct smu_context *smu,
OverDriveTable_t *od_table)
{
dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax);
dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct);
}
static int navi10_od_setting_check_range(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t value)
static int navi10_od_setting_check_range(struct smu_context *smu,
struct smu_11_0_overdrive_table *od_table,
enum SMU_11_0_ODSETTING_ID setting,
uint32_t value)
{
if (value < od_table->min[setting]) {
pr_warn("OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
return -EINVAL;
}
if (value > od_table->max[setting]) {
pr_warn("OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
return -EINVAL;
}
return 0;
@ -2022,7 +2027,7 @@ static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
param,
&value);
if (ret) {
pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
return ret;
}
@ -2053,7 +2058,7 @@ static int navi10_set_default_od_settings(struct smu_context *smu)
ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, false);
if (ret) {
pr_err("Failed to get overdrive table!\n");
dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
return ret;
}
@ -2083,7 +2088,7 @@ static int navi10_set_default_od_settings(struct smu_context *smu)
memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t));
navi10_dump_od_table(od_table);
navi10_dump_od_table(smu, od_table);
return 0;
}
@ -2099,12 +2104,12 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
od_table = (OverDriveTable_t *)table_context->overdrive_table;
if (!smu->od_enabled) {
pr_warn("OverDrive is not enabled!\n");
dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
return -EINVAL;
}
if (!smu->od_settings) {
pr_err("OD board limits are not set!\n");
dev_err(smu->adev->dev, "OD board limits are not set!\n");
return -ENOENT;
}
@ -2113,16 +2118,16 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
switch (type) {
case PP_OD_EDIT_SCLK_VDDC_TABLE:
if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
pr_warn("GFXCLK_LIMITS not supported!\n");
dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
return -ENOTSUPP;
}
if (!table_context->overdrive_table) {
pr_err("Overdrive is not initialized\n");
dev_err(smu->adev->dev, "Overdrive is not initialized\n");
return -EINVAL;
}
for (i = 0; i < size; i += 2) {
if (i + 2 > size) {
pr_info("invalid number of input parameters %d\n", size);
dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
return -EINVAL;
}
switch (input[i]) {
@ -2130,7 +2135,7 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
freq_ptr = &od_table->GfxclkFmin;
if (input[i + 1] > od_table->GfxclkFmax) {
pr_info("GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
input[i + 1],
od_table->GfxclkFmin);
return -EINVAL;
@ -2140,18 +2145,18 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
freq_ptr = &od_table->GfxclkFmax;
if (input[i + 1] < od_table->GfxclkFmin) {
pr_info("GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
input[i + 1],
od_table->GfxclkFmax);
return -EINVAL;
}
break;
default:
pr_info("Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
pr_info("Supported indices: [0:min,1:max]\n");
dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
return -EINVAL;
}
ret = navi10_od_setting_check_range(od_settings, freq_setting, input[i + 1]);
ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
if (ret)
return ret;
*freq_ptr = input[i + 1];
@ -2159,35 +2164,35 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
break;
case PP_OD_EDIT_MCLK_VDDC_TABLE:
if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
pr_warn("UCLK_MAX not supported!\n");
dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n");
return -ENOTSUPP;
}
if (size < 2) {
pr_info("invalid number of parameters: %d\n", size);
dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
return -EINVAL;
}
if (input[0] != 1) {
pr_info("Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
pr_info("Supported indices: [1:max]\n");
dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
dev_info(smu->adev->dev, "Supported indices: [1:max]\n");
return -EINVAL;
}
ret = navi10_od_setting_check_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
if (ret)
return ret;
od_table->UclkFmax = input[1];
break;
case PP_OD_RESTORE_DEFAULT_TABLE:
if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
pr_err("Overdrive table was not initialized!\n");
dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
return -EINVAL;
}
memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
break;
case PP_OD_COMMIT_DPM_TABLE:
navi10_dump_od_table(od_table);
navi10_dump_od_table(smu, od_table);
ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
if (ret) {
pr_err("Failed to import overdrive table!\n");
dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
return ret;
}
// no lock needed because smu_od_edit_dpm_table has it
@ -2200,15 +2205,15 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
break;
case PP_OD_EDIT_VDDC_CURVE:
if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
pr_warn("GFXCLK_CURVE not supported!\n");
dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n");
return -ENOTSUPP;
}
if (size < 3) {
pr_info("invalid number of parameters: %d\n", size);
dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
return -EINVAL;
}
if (!od_table) {
pr_info("Overdrive is not initialized\n");
dev_info(smu->adev->dev, "Overdrive is not initialized\n");
return -EINVAL;
}
@ -2232,28 +2237,28 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
voltage_ptr = &od_table->GfxclkVolt3;
break;
default:
pr_info("Invalid VDDC_CURVE index: %ld\n", input[0]);
pr_info("Supported indices: [0, 1, 2]\n");
dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]);
dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n");
return -EINVAL;
}
ret = navi10_od_setting_check_range(od_settings, freq_setting, input[1]);
ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
if (ret)
return ret;
// Allow setting zero to disable the OverDrive VDDC curve
if (input[2] != 0) {
ret = navi10_od_setting_check_range(od_settings, voltage_setting, input[2]);
ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);
if (ret)
return ret;
*freq_ptr = input[1];
*voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
pr_debug("OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
} else {
// If setting 0, disable all voltage curve settings
od_table->GfxclkVolt1 = 0;
od_table->GfxclkVolt2 = 0;
od_table->GfxclkVolt3 = 0;
}
navi10_dump_od_table(od_table);
navi10_dump_od_table(smu, od_table);
break;
default:
return -ENOSYS;
@ -2267,7 +2272,7 @@ static int navi10_run_btc(struct smu_context *smu)
ret = smu_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
if (ret)
pr_err("RunBtc failed!\n");
dev_err(smu->adev->dev, "RunBtc failed!\n");
return ret;
}
@ -2394,7 +2399,7 @@ static uint32_t navi10_get_max_power_limit(struct smu_context *smu) {
if (smu->od_enabled) {
od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
max_power_limit *= (100 + od_limit);
max_power_limit /= 100;

14
drivers/gpu/drm/amd/powerplay/renoir_ppt.c
View File

@ -175,7 +175,7 @@ static int renoir_get_metrics_table(struct smu_context *smu,
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
(void *)smu_table->metrics_table, false);
if (ret) {
pr_info("Failed to export SMU metrics table!\n");
dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
mutex_unlock(&smu->metrics_lock);
return ret;
}
@ -508,7 +508,7 @@ static int renoir_get_current_activity_percent(struct smu_context *smu,
*value = metrics.AverageGfxActivity / 100;
break;
default:
pr_err("Invalid sensor for retrieving clock activity\n");
dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
return -EINVAL;
}
@ -620,7 +620,7 @@ static int renoir_force_clk_levels(struct smu_context *smu,
case SMU_GFXCLK:
case SMU_SCLK:
if (soft_min_level > 2 || soft_max_level > 2) {
pr_info("Currently sclk only support 3 levels on APU\n");
dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n");
return -EINVAL;
}
@ -674,7 +674,7 @@ static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, u
uint32_t profile_mode = input[size];
if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
return -EINVAL;
}
@ -685,7 +685,7 @@ static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, u
* TODO: If some case need switch to powersave/default power mode
* then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving.
*/
pr_err_once("Unsupported power profile mode %d on RENOIR\n",smu->power_profile_mode);
dev_err_once(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n",smu->power_profile_mode);
return -EINVAL;
}
@ -693,7 +693,7 @@ static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, u
1 << workload_type,
NULL);
if (ret) {
pr_err_once("Fail to set workload type %d\n", workload_type);
dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
return ret;
}
@ -826,7 +826,7 @@ static int renoir_set_watermarks_table(
if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
ret = smu_write_watermarks_table(smu);
if (ret) {
pr_err("Failed to update WMTABLE!");
dev_err(smu->adev->dev, "Failed to update WMTABLE!");
return ret;
}
smu->watermarks_bitmap |= WATERMARKS_LOADED;

706
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
View File

File diff suppressed because it is too large Load Diff

50
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
View File

@ -105,7 +105,7 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu,
mutex_lock(&smu->message_lock);
ret = smu_v11_0_wait_for_response(smu);
if (ret) {
pr_err("Msg issuing pre-check failed and "
dev_err(adev->dev, "Msg issuing pre-check failed and "
"SMU may be not in the right state!\n");
goto out;
}
@ -118,7 +118,7 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu,
ret = smu_v11_0_wait_for_response(smu);
if (ret) {
pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
dev_err(adev->dev, "failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
smu_get_message_name(smu, msg), index, param, ret);
goto out;
}
@ -126,7 +126,7 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu,
if (read_arg) {
ret = smu_v11_0_read_arg(smu, read_arg);
if (ret) {
pr_err("failed to read message arg: %10s (%d) \tparam: 0x%08x response %#x\n",
dev_err(adev->dev, "failed to read message arg: %10s (%d) \tparam: 0x%08x response %#x\n",
smu_get_message_name(smu, msg), index, param, ret);
goto out;
}
@ -294,7 +294,7 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
break;
default:
pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
break;
}
@ -308,11 +308,11 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
* of halt driver loading.
*/
if (if_version != smu->smc_driver_if_version) {
pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
"smu fw version = 0x%08x (%d.%d.%d)\n",
smu->smc_driver_if_version, if_version,
smu_version, smu_major, smu_minor, smu_debug);
pr_warn("SMU driver if version not matched\n");
dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
}
return ret;
@ -375,7 +375,7 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
version_major = le16_to_cpu(hdr->header.header_version_major);
version_minor = le16_to_cpu(hdr->header.header_version_minor);
if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
switch (version_minor) {
case 0:
ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
@ -392,7 +392,7 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
return ret;
} else {
pr_info("use vbios provided pptable\n");
dev_info(adev->dev, "use vbios provided pptable\n");
index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
powerplayinfo);
@ -617,7 +617,7 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
return ret;
if (header->format_revision != 3) {
pr_err("unknown atom_firmware_info version! for smu11\n");
dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
return -EINVAL;
}
@ -767,7 +767,7 @@ int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
if (ret)
pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
return ret;
}
@ -951,7 +951,7 @@ smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
clk_id << 16, clock);
if (ret) {
pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
return ret;
}
@ -962,7 +962,7 @@ smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
clk_id << 16, clock);
if (ret) {
pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
return ret;
}
@ -987,7 +987,7 @@ int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
&(max_sustainable_clocks->uclock),
SMU_UCLK);
if (ret) {
pr_err("[%s] failed to get max UCLK from SMC!",
dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
__func__);
return ret;
}
@ -998,7 +998,7 @@ int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
&(max_sustainable_clocks->soc_clock),
SMU_SOCCLK);
if (ret) {
pr_err("[%s] failed to get max SOCCLK from SMC!",
dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
__func__);
return ret;
}
@ -1009,7 +1009,7 @@ int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
&(max_sustainable_clocks->dcef_clock),
SMU_DCEFCLK);
if (ret) {
pr_err("[%s] failed to get max DCEFCLK from SMC!",
dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
__func__);
return ret;
}
@ -1018,7 +1018,7 @@ int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
&(max_sustainable_clocks->display_clock),
SMU_DISPCLK);
if (ret) {
pr_err("[%s] failed to get max DISPCLK from SMC!",
dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
__func__);
return ret;
}
@ -1026,7 +1026,7 @@ int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
&(max_sustainable_clocks->phy_clock),
SMU_PHYCLK);
if (ret) {
pr_err("[%s] failed to get max PHYCLK from SMC!",
dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
__func__);
return ret;
}
@ -1034,7 +1034,7 @@ int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
&(max_sustainable_clocks->pixel_clock),
SMU_PIXCLK);
if (ret) {
pr_err("[%s] failed to get max PIXCLK from SMC!",
dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
__func__);
return ret;
}
@ -1054,7 +1054,7 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
max_power_limit = smu_get_max_power_limit(smu);
if (n > max_power_limit) {
pr_err("New power limit (%d) is over the max allowed %d\n",
dev_err(smu->adev->dev, "New power limit (%d) is over the max allowed %d\n",
n,
max_power_limit);
return -EINVAL;
@ -1064,13 +1064,13 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
n = smu->default_power_limit;
if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
pr_err("Setting new power limit is not supported!\n");
dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
return -EOPNOTSUPP;
}
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
if (ret) {
pr_err("[%s] Set power limit Failed!\n", __func__);
dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
return ret;
}
smu->power_limit = n;
@ -1243,7 +1243,7 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
clk_select = SMU_UCLK;
break;
default:
pr_info("[%s] Invalid Clock Type!", __func__);
dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
ret = -EINVAL;
break;
}
@ -1307,7 +1307,7 @@ smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
if (ret)
pr_err("[%s]%s smc FAN CONTROL feature failed!",
dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
__func__, (auto_fan_control ? "Start" : "Stop"));
return ret;
@ -1378,7 +1378,7 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
}
if (ret) {
pr_err("[%s]Set fan control mode failed!", __func__);
dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
return -EINVAL;
}
@ -1849,7 +1849,7 @@ int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
if (ret)
pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
dev_err(adev->dev, "[%s] Attempt to override pcie params failed!\n", __func__);
return ret;

14
drivers/gpu/drm/amd/powerplay/smu_v12_0.c
View File

@ -92,7 +92,7 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu,
mutex_lock(&smu->message_lock);
ret = smu_v12_0_wait_for_response(smu);
if (ret) {
pr_err("Msg issuing pre-check failed and "
dev_err(adev->dev, "Msg issuing pre-check failed and "
"SMU may be not in the right state!\n");
goto out;
}
@ -105,14 +105,14 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu,
ret = smu_v12_0_wait_for_response(smu);
if (ret) {
pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
dev_err(adev->dev, "Failed to send message 0x%x, response 0x%x param 0x%x\n",
index, ret, param);
goto out;
}
if (read_arg) {
ret = smu_v12_0_read_arg(smu, read_arg);
if (ret) {
pr_err("Failed to read message arg 0x%x, response 0x%x param 0x%x\n",
dev_err(adev->dev, "Failed to read message arg 0x%x, response 0x%x param 0x%x\n",
index, ret, param);
goto out;
}
@ -161,11 +161,11 @@ int smu_v12_0_check_fw_version(struct smu_context *smu)
* of halt driver loading.
*/
if (if_version != smu->smc_driver_if_version) {
pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
"smu fw version = 0x%08x (%d.%d.%d)\n",
smu->smc_driver_if_version, if_version,
smu_version, smu_major, smu_minor, smu_debug);
pr_warn("SMU driver if version not matched\n");
dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
}
return ret;
@ -378,7 +378,7 @@ int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type c
case SMU_SCLK:
ret = smu_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
if (ret) {
pr_err("Attempt to get max GX frequency from SMC Failed !\n");
dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
goto failed;
}
break;
@ -406,7 +406,7 @@ int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type c
case SMU_SCLK:
ret = smu_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
if (ret) {
pr_err("Attempt to get min GX frequency from SMC Failed !\n");
dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
goto failed;
}
break;