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csky: Enable defer flush_dcache_page for abiv2 cpus (807/810/860)
Instead of flushing cache per update_mmu_cache() called, we use flush_dcache_page to reduce the frequency of flashing the cache. As abiv2 cpus are all PIPT for icache & dcache, we needn't handle dcache aliasing problem. But their icache can't snoop dcache, so we still need sync_icache_dcache in update_mmu_cache(). Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
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@ -9,20 +9,22 @@
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
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pte_t *pte)
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{
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unsigned long addr, pfn;
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unsigned long addr;
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struct page *page;
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pfn = pte_pfn(*pte);
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if (unlikely(!pfn_valid(pfn)))
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page = pfn_to_page(pte_pfn(*pte));
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if (page == ZERO_PAGE(0))
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return;
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page = pfn_to_page(pfn);
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if (page == ZERO_PAGE(0))
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if (test_and_set_bit(PG_dcache_clean, &page->flags))
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return;
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addr = (unsigned long) kmap_atomic(page);
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cache_wbinv_range(addr, addr + PAGE_SIZE);
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dcache_wb_range(addr, addr + PAGE_SIZE);
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if (vma->vm_flags & VM_EXEC)
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icache_inv_range(addr, addr + PAGE_SIZE);
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kunmap_atomic((void *) addr);
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}
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@ -15,8 +15,16 @@
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define PG_dcache_clean PG_arch_1
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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static inline void flush_dcache_page(struct page *page)
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{
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if (test_bit(PG_dcache_clean, &page->flags))
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clear_bit(PG_dcache_clean, &page->flags);
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}
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_icache_page(vma, page) do { } while (0)
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