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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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rtw88: 8723d: Organize chip TX/RX FIFO
TX FIFO size is 32k and it was divided into 256 pages with 128 bytes. A boundary is used to split pages into two parts, head part is used to store TX packets coming from host, and tail part is reserved for special purposes, such as beacon packet, null data packet and so on. The TX packets coming from host have many categories, such as VO, VI, BE, BK, MG and etc. When going into head part of TX FIFO, they are classified to four priority queue named low, normal, high and extra priority queues. Each priority queue occupies predefined number of page, if a certain priority queue is full, TX packet will store into PUB priority queue. Similarly, RX FIFO is 16k and split into two parts, head part is used to store RX packets, and tail part is 128 bytes and used to store report. Thus, we fill this boundary to register as well. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200422034607.28747-8-yhchuang@realtek.com
This commit is contained in:
Ping-Ke Shih
Kalle Valo
parent
ba9f0d1b8d
commit
d91277de23
@ -1032,13 +1032,16 @@ static int set_trx_fifo_info(struct rtw_dev *rtwdev)
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/* config rsvd page num */
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fifo->rsvd_drv_pg_num = 8;
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fifo->txff_pg_num = chip->txff_size >> 7;
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fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num +
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RSVD_PG_H2C_EXTRAINFO_NUM +
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RSVD_PG_H2C_STATICINFO_NUM +
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RSVD_PG_H2CQ_NUM +
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RSVD_PG_CPU_INSTRUCTION_NUM +
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RSVD_PG_FW_TXBUF_NUM +
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csi_buf_pg_num;
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if (rtw_chip_wcpu_11n(rtwdev))
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fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num;
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else
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fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num +
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RSVD_PG_H2C_EXTRAINFO_NUM +
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RSVD_PG_H2C_STATICINFO_NUM +
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RSVD_PG_H2CQ_NUM +
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RSVD_PG_CPU_INSTRUCTION_NUM +
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RSVD_PG_FW_TXBUF_NUM +
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csi_buf_pg_num;
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if (fifo->rsvd_pg_num > fifo->txff_pg_num)
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return -ENOMEM;
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@ -1047,18 +1050,20 @@ static int set_trx_fifo_info(struct rtw_dev *rtwdev)
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fifo->rsvd_boundary = fifo->txff_pg_num - fifo->rsvd_pg_num;
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cur_pg_addr = fifo->txff_pg_num;
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cur_pg_addr -= csi_buf_pg_num;
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fifo->rsvd_csibuf_addr = cur_pg_addr;
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cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM;
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fifo->rsvd_fw_txbuf_addr = cur_pg_addr;
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cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM;
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fifo->rsvd_cpu_instr_addr = cur_pg_addr;
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cur_pg_addr -= RSVD_PG_H2CQ_NUM;
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fifo->rsvd_h2cq_addr = cur_pg_addr;
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cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM;
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fifo->rsvd_h2c_sta_info_addr = cur_pg_addr;
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cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM;
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fifo->rsvd_h2c_info_addr = cur_pg_addr;
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if (rtw_chip_wcpu_11ac(rtwdev)) {
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cur_pg_addr -= csi_buf_pg_num;
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fifo->rsvd_csibuf_addr = cur_pg_addr;
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cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM;
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fifo->rsvd_fw_txbuf_addr = cur_pg_addr;
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cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM;
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fifo->rsvd_cpu_instr_addr = cur_pg_addr;
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cur_pg_addr -= RSVD_PG_H2CQ_NUM;
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fifo->rsvd_h2cq_addr = cur_pg_addr;
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cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM;
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fifo->rsvd_h2c_sta_info_addr = cur_pg_addr;
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cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM;
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fifo->rsvd_h2c_info_addr = cur_pg_addr;
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}
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cur_pg_addr -= fifo->rsvd_drv_pg_num;
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fifo->rsvd_drv_addr = cur_pg_addr;
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@ -1070,6 +1075,65 @@ static int set_trx_fifo_info(struct rtw_dev *rtwdev)
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return 0;
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}
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static int __priority_queue_cfg(struct rtw_dev *rtwdev,
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const struct rtw_page_table *pg_tbl,
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u16 pubq_num)
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{
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struct rtw_fifo_conf *fifo = &rtwdev->fifo;
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struct rtw_chip_info *chip = rtwdev->chip;
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rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num);
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rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num);
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rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num);
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rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num);
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rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num);
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rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN);
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rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary);
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rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16);
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rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary);
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rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary);
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rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary);
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rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1);
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rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);
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if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0))
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return -EBUSY;
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rtw_write8(rtwdev, REG_CR + 3, 0);
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return 0;
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}
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static int __priority_queue_cfg_legacy(struct rtw_dev *rtwdev,
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const struct rtw_page_table *pg_tbl,
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u16 pubq_num)
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{
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struct rtw_fifo_conf *fifo = &rtwdev->fifo;
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struct rtw_chip_info *chip = rtwdev->chip;
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u32 val32;
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val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num);
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rtw_write32(rtwdev, REG_RQPN_NPQ, val32);
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val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num);
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rtw_write32(rtwdev, REG_RQPN, val32);
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rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary);
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rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1);
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rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary);
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rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary);
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rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary);
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rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary);
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rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT);
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if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0))
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return -EBUSY;
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return 0;
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}
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static int priority_queue_cfg(struct rtw_dev *rtwdev)
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{
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struct rtw_fifo_conf *fifo = &rtwdev->fifo;
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@ -1102,28 +1166,10 @@ static int priority_queue_cfg(struct rtw_dev *rtwdev)
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pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num -
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pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num;
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rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num);
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rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num);
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rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num);
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rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num);
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rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num);
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rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN);
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rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary);
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rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16);
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rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary);
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rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary);
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rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary);
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rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1);
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rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);
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if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0))
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return -EBUSY;
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rtw_write8(rtwdev, REG_CR + 3, 0);
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return 0;
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if (rtw_chip_wcpu_11n(rtwdev))
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return __priority_queue_cfg_legacy(rtwdev, pg_tbl, pubq_num);
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else
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return __priority_queue_cfg(rtwdev, pg_tbl, pubq_num);
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}
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static int init_h2c(struct rtw_dev *rtwdev)
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@ -1203,11 +1249,13 @@ static int rtw_drv_info_cfg(struct rtw_dev *rtwdev)
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u8 value8;
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rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE);
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value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1);
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value8 &= 0xF0;
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/* For rxdesc len = 0 issue */
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value8 |= 0xF;
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rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8);
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if (rtw_chip_wcpu_11ac(rtwdev)) {
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value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1);
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value8 &= 0xF0;
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/* For rxdesc len = 0 issue */
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value8 |= 0xF;
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rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8);
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}
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rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS);
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rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9));
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@ -10,6 +10,7 @@
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#define SDIO_LOCAL_OFFSET 0x10250000
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#define DDMA_POLLING_COUNT 1000
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#define C2H_PKT_BUF 256
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#define REPORT_BUF 128
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#define PHY_STATUS_SIZE 4
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#define ILLEGAL_KEY_GROUP 0xFAAAAA00
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@ -209,6 +209,19 @@
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#define REG_HMEBOX2_EX 0x01F8
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#define REG_HMEBOX3_EX 0x01FC
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#define REG_RQPN 0x0200
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#define BIT_MASK_HPQ 0xff
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#define BIT_SHIFT_HPQ 0
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#define BIT_RQPN_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ)
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#define BIT_MASK_LPQ 0xff
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#define BIT_SHIFT_LPQ 8
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#define BIT_RQPN_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ)
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#define BIT_MASK_PUBQ 0xff
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#define BIT_SHIFT_PUBQ 16
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#define BIT_RQPN_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ)
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#define BIT_RQPN_HLP(h, l, p) (BIT_LD_RQPN | BIT_RQPN_HPQ(h) | \
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BIT_RQPN_LPQ(l) | BIT_RQPN_PUBQ(p))
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#define REG_FIFOPAGE_CTRL_2 0x0204
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#define BIT_BCN_VALID_V1 BIT(15)
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#define BIT_MASK_BCN_HEAD_1_V1 0xfff
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@ -219,6 +232,18 @@
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#define REG_TXDMA_OFFSET_CHK 0x020C
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#define REG_TXDMA_STATUS 0x0210
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#define BTI_PAGE_OVF BIT(2)
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#define REG_RQPN_NPQ 0x0214
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#define BIT_MASK_NPQ 0xff
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#define BIT_SHIFT_NPQ 0
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#define BIT_MASK_EPQ 0xff
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#define BIT_SHIFT_EPQ 16
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#define BIT_RQPN_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ)
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#define BIT_RQPN_EPQ(x) (((x) & BIT_MASK_EPQ) << BIT_SHIFT_EPQ)
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#define BIT_RQPN_NE(n, e) (BIT_RQPN_NPQ(n) | BIT_RQPN_EPQ(e))
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#define REG_AUTO_LLT 0x0224
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#define BIT_AUTO_INIT_LLT BIT(16)
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#define REG_RQPN_CTRL_1 0x0228
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#define REG_RQPN_CTRL_2 0x022C
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#define BIT_LD_RQPN BIT(31)
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@ -249,6 +274,8 @@
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#define REG_HWSEQ_CTRL 0x0423
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#define REG_BCNQ_BDNY_V1 0x0424
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#define REG_BCNQ_BDNY 0x0424
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#define REG_MGQ_BDNY 0x0425
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#define REG_LIFETIME_EN 0x0426
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#define BIT_BA_PARSER_EN BIT(5)
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#define REG_SPEC_SIFS 0x0428
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@ -264,6 +291,7 @@
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#define BIT_CHECK_CCK_EN BIT(7)
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#define REG_AMPDU_MAX_TIME_V1 0x0455
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#define REG_BCNQ1_BDNY_V1 0x0456
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#define REG_WMAC_LBK_BF_HD 0x045D
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#define REG_TX_HANG_CTRL 0x045E
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#define BIT_EN_GNT_BT_AWAKE BIT(3)
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#define BIT_EN_EOF_V1 BIT(2)
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@ -556,6 +556,32 @@ static const struct rtw_pwr_seq_cmd *card_disable_flow_8723d[] = {
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NULL
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};
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static const struct rtw_page_table page_table_8723d[] = {
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{12, 2, 2, 0, 1},
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{12, 2, 2, 0, 1},
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{12, 2, 2, 0, 1},
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{12, 2, 2, 0, 1},
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{12, 2, 2, 0, 1},
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};
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static const struct rtw_rqpn rqpn_table_8723d[] = {
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{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
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RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
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RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
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{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
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RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
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RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
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{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
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RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
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RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
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{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
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RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
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RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
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{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
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RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
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RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
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};
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static const struct rtw_rf_sipi_addr rtw8723d_rf_sipi_addr[] = {
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[RF_PATH_A] = { .hssi_1 = 0x820, .lssi_read = 0x8a0,
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.hssi_2 = 0x824, .lssi_read_pi = 0x8b8},
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@ -580,17 +606,22 @@ struct rtw_chip_info rtw8723d_hw_spec = {
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.phy_efuse_size = 512,
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.log_efuse_size = 512,
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.ptct_efuse_size = 96 + 1,
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.txff_size = 32768,
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.rxff_size = 16384,
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.txgi_factor = 1,
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.is_pwr_by_rate_dec = true,
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.max_power_index = 0x3f,
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.csi_buf_pg_num = 0,
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.band = RTW_BAND_2G,
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.page_size = 128,
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.ht_supported = true,
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.vht_supported = false,
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.lps_deep_mode_supported = 0,
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.sys_func_en = 0xFD,
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.pwr_on_seq = card_enable_flow_8723d,
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.pwr_off_seq = card_disable_flow_8723d,
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.page_table = page_table_8723d,
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.rqpn_table = rqpn_table_8723d,
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.rf_sipi_addr = {0x840, 0x844},
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.rf_sipi_read_addr = rtw8723d_rf_sipi_addr,
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.fix_rf_phy_num = 2,
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