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net: qed: critical err reporting to management firmware
On various critical errors, notification handler should also report the err information into the management firmware. MFW can interact with server/motherboard backend agents - these are used by server manufacturers to monitor server HW health. Thus, it is important for driver to report on any faulty conditions Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -12492,6 +12492,8 @@ struct public_drv_mb {
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#define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000
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#define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000
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#define DRV_MSG_CODE_DEBUG_DATA_SEND 0xc0040000
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#define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F
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#define RESOURCE_CMD_REQ_RESC_SHIFT 0
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#define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0
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@ -12626,6 +12628,17 @@ struct public_drv_mb {
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#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
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#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000
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/* DRV_MSG_CODE_DEBUG_DATA_SEND parameters */
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#define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_OFFSET 0
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#define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK 0xFF
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/* Driver attributes params */
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#define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0
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#define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00FFFFFF
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#define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24
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#define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xFF000000
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#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET 0
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#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT 0
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#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000FFFF
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#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT 16
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@ -12678,6 +12691,12 @@ struct public_drv_mb {
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#define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000
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#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
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#define FW_MSG_CODE_DEBUG_DATA_SEND_INV_ARG 0xb0070000
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#define FW_MSG_CODE_DEBUG_DATA_SEND_BUF_FULL 0xb0080000
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#define FW_MSG_CODE_DEBUG_DATA_SEND_NO_BUF 0xb0090000
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#define FW_MSG_CODE_DEBUG_NOT_ENABLED 0xb00a0000
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#define FW_MSG_CODE_DEBUG_DATA_SEND_OK 0xb00b0000
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u32 fw_mb_param;
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#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
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#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
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@ -868,6 +868,9 @@ void qed_hw_err_notify(struct qed_hwfn *p_hwfn,
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}
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qed_hw_error_occurred(p_hwfn, err_type);
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if (fmt)
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qed_mcp_send_raw_debug_data(p_hwfn, p_ptt, buf, len);
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}
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int qed_dmae_sanity(struct qed_hwfn *p_hwfn,
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@ -3821,3 +3821,127 @@ int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
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DRV_MSG_CODE_SET_NVM_CFG_OPTION,
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mb_param, &resp, ¶m, len, (u32 *)p_buf);
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}
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#define QED_MCP_DBG_DATA_MAX_SIZE MCP_DRV_NVM_BUF_LEN
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#define QED_MCP_DBG_DATA_MAX_HEADER_SIZE sizeof(u32)
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#define QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE \
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(QED_MCP_DBG_DATA_MAX_SIZE - QED_MCP_DBG_DATA_MAX_HEADER_SIZE)
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static int
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__qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u8 *p_buf, u8 size)
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{
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struct qed_mcp_mb_params mb_params;
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int rc;
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if (size > QED_MCP_DBG_DATA_MAX_SIZE) {
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DP_ERR(p_hwfn,
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"Debug data size is %d while it should not exceed %d\n",
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size, QED_MCP_DBG_DATA_MAX_SIZE);
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return -EINVAL;
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}
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memset(&mb_params, 0, sizeof(mb_params));
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mb_params.cmd = DRV_MSG_CODE_DEBUG_DATA_SEND;
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SET_MFW_FIELD(mb_params.param, DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE, size);
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mb_params.p_data_src = p_buf;
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mb_params.data_src_size = size;
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rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
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if (rc)
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return rc;
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if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
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DP_INFO(p_hwfn,
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"The DEBUG_DATA_SEND command is unsupported by the MFW\n");
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return -EOPNOTSUPP;
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} else if (mb_params.mcp_resp == (u32)FW_MSG_CODE_DEBUG_NOT_ENABLED) {
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DP_INFO(p_hwfn, "The DEBUG_DATA_SEND command is not enabled\n");
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return -EBUSY;
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} else if (mb_params.mcp_resp != (u32)FW_MSG_CODE_DEBUG_DATA_SEND_OK) {
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DP_NOTICE(p_hwfn,
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"Failed to send debug data to the MFW [resp 0x%08x]\n",
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mb_params.mcp_resp);
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return -EINVAL;
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}
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return 0;
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}
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enum qed_mcp_dbg_data_type {
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QED_MCP_DBG_DATA_TYPE_RAW,
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};
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/* Header format: [31:28] PFID, [27:20] flags, [19:12] type, [11:0] S/N */
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#define QED_MCP_DBG_DATA_HDR_SN_OFFSET 0
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#define QED_MCP_DBG_DATA_HDR_SN_MASK 0x00000fff
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#define QED_MCP_DBG_DATA_HDR_TYPE_OFFSET 12
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#define QED_MCP_DBG_DATA_HDR_TYPE_MASK 0x000ff000
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#define QED_MCP_DBG_DATA_HDR_FLAGS_OFFSET 20
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#define QED_MCP_DBG_DATA_HDR_FLAGS_MASK 0x0ff00000
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#define QED_MCP_DBG_DATA_HDR_PF_OFFSET 28
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#define QED_MCP_DBG_DATA_HDR_PF_MASK 0xf0000000
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#define QED_MCP_DBG_DATA_HDR_FLAGS_FIRST 0x1
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#define QED_MCP_DBG_DATA_HDR_FLAGS_LAST 0x2
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static int
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qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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enum qed_mcp_dbg_data_type type, u8 *p_buf, u32 size)
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{
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u8 raw_data[QED_MCP_DBG_DATA_MAX_SIZE], *p_tmp_buf = p_buf;
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u32 tmp_size = size, *p_header, *p_payload;
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u8 flags = 0;
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u16 seq;
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int rc;
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p_header = (u32 *)raw_data;
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p_payload = (u32 *)(raw_data + QED_MCP_DBG_DATA_MAX_HEADER_SIZE);
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seq = (u16)atomic_inc_return(&p_hwfn->mcp_info->dbg_data_seq);
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/* First chunk is marked as 'first' */
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flags |= QED_MCP_DBG_DATA_HDR_FLAGS_FIRST;
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*p_header = 0;
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SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_SN, seq);
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SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_TYPE, type);
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SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags);
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SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_PF, p_hwfn->abs_pf_id);
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while (tmp_size > QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE) {
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memcpy(p_payload, p_tmp_buf, QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE);
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rc = __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data,
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QED_MCP_DBG_DATA_MAX_SIZE);
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if (rc)
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return rc;
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/* Clear the 'first' marking after sending the first chunk */
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if (p_tmp_buf == p_buf) {
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flags &= ~QED_MCP_DBG_DATA_HDR_FLAGS_FIRST;
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SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS,
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flags);
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}
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p_tmp_buf += QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE;
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tmp_size -= QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE;
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}
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/* Last chunk is marked as 'last' */
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flags |= QED_MCP_DBG_DATA_HDR_FLAGS_LAST;
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SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags);
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memcpy(p_payload, p_tmp_buf, tmp_size);
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/* Casting the left size to u8 is ok since at this point it is <= 32 */
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return __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data,
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(u8)(QED_MCP_DBG_DATA_MAX_HEADER_SIZE +
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tmp_size));
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}
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int
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qed_mcp_send_raw_debug_data(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u8 *p_buf, u32 size)
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{
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return qed_mcp_send_debug_data(p_hwfn, p_ptt,
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QED_MCP_DBG_DATA_TYPE_RAW, p_buf, size);
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}
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@ -685,6 +685,18 @@ int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn,
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*/
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int qed_mfw_process_tlv_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
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/**
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* @brief Send raw debug data to the MFW
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*
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* @param p_hwfn
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* @param p_ptt
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* @param p_buf - raw debug data buffer
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* @param size - buffer size
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*/
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int
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qed_mcp_send_raw_debug_data(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u8 *p_buf, u32 size);
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/* Using hwfn number (and not pf_num) is required since in CMT mode,
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* same pf_num may be used by two different hwfn
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* TODO - this shouldn't really be in .h file, but until all fields
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@ -731,6 +743,9 @@ struct qed_mcp_info {
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/* Capabilties negotiated with the MFW */
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u32 capabilities;
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/* S/N for debug data mailbox commands */
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atomic_t dbg_data_seq;
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};
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struct qed_mcp_mb_params {
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