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ARM: dts: qcom: Add idle states device nodes for 8084

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Add ARM common idle states device bindings for cpuidle support for APQ
8084.

Support Standalone power collapse (SPC) idle state (power down that does not
affect any SoC idle states) for each cpu.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Lina Iyer 2015-03-25 14:25:34 -06:00 committed by Olof Johansson
parent d596d620d8
commit d8664979e6
1 changed files with 14 additions and 0 deletions
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14
arch/arm/boot/dts/qcom-apq8084.dtsi
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@ -22,6 +22,7 @@ cpu@0 {
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
cpu-idle-states = <&CPU_SPC>;
};
cpu@1 {
@ -32,6 +33,7 @@ cpu@1 {
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
cpu-idle-states = <&CPU_SPC>;
};
cpu@2 {
@ -42,6 +44,7 @@ cpu@2 {
next-level-cache = <&L2>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
cpu-idle-states = <&CPU_SPC>;
};
cpu@3 {
@ -52,6 +55,7 @@ cpu@3 {
next-level-cache = <&L2>;
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
cpu-idle-states = <&CPU_SPC>;
};
L2: l2-cache {
@ -59,6 +63,16 @@ L2: l2-cache {
cache-level = <2>;
qcom,saw = <&saw_l2>;
};
idle-states {
CPU_SPC: spc {
compatible = "qcom,idle-state-spc",
"arm,idle-state";
entry-latency-us = <150>;
exit-latency-us = <200>;
min-residency-us = <2000>;
};
};
};
cpu-pmu {