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ice: Restructure VFs initialization flows

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This patch restructures how VFs are configured, and resources allocated.
Instead of freeing resources that were never allocated, and resetting
empty VFs that have never been created - the new flow will just allocate
resources for number of requested VFs based on the availability.

During VFs initialization process, global interrupt is disabled, and
rearmed after getting MSIX vectors for VFs. This allows immediate mailbox
communications, instead of delaying it till later and VFs.
PF communications resulted to using polling instead of actual interrupt.
The issue manifested when creating higher number of VFs (128 VFs) per PF.

Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Akeem G Abodunrin 2019-07-25 01:55:30 -07:00 committed by Jeff Kirsher
parent 9118fcd525
commit d82dd83df2
2 changed files with 48 additions and 22 deletions
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1
drivers/net/ethernet/intel/ice/ice.h
View File

@ -220,6 +220,7 @@ enum ice_state {
__ICE_CFG_BUSY,
__ICE_SERVICE_SCHED,
__ICE_SERVICE_DIS,
__ICE_OICR_INTR_DIS, /* Global OICR interrupt disabled */
__ICE_STATE_NBITS /* must be last */
};

69
drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c
View File

@ -974,6 +974,47 @@ ice_vf_set_vsi_promisc(struct ice_vf *vf, struct ice_vsi *vsi, u8 promisc_m,
return status;
}
/**
* ice_config_res_vfs - Finalize allocation of VFs resources in one go
* @pf: pointer to the PF structure
*
* This function is being called as last part of resetting all VFs, or when
* configuring VFs for the first time, where there is no resource to be freed
* Returns true if resources were properly allocated for all VFs, and false
* otherwise.
*/
static bool ice_config_res_vfs(struct ice_pf *pf)
{
struct ice_hw *hw = &pf->hw;
int v;
if (ice_check_avail_res(pf)) {
dev_err(&pf->pdev->dev,
"Cannot allocate VF resources, try with fewer number of VFs\n");
return false;
}
/* rearm global interrupts */
if (test_and_clear_bit(__ICE_OICR_INTR_DIS, pf->state))
ice_irq_dynamic_ena(hw, NULL, NULL);
/* Finish resetting each VF and allocate resources */
for (v = 0; v < pf->num_alloc_vfs; v++) {
struct ice_vf *vf = &pf->vf[v];
vf->num_vf_qs = pf->num_vf_qps;
dev_dbg(&pf->pdev->dev,
"VF-id %d has %d queues configured\n",
vf->vf_id, vf->num_vf_qs);
ice_cleanup_and_realloc_vf(vf);
}
ice_flush(hw);
clear_bit(__ICE_VF_DIS, pf->state);
return true;
}
/**
* ice_reset_all_vfs - reset all allocated VFs in one go
* @pf: pointer to the PF structure
@ -1066,25 +1107,8 @@ bool ice_reset_all_vfs(struct ice_pf *pf, bool is_vflr)
dev_err(&pf->pdev->dev,
"Failed to free MSIX resources used by SR-IOV\n");
if (ice_check_avail_res(pf)) {
dev_err(&pf->pdev->dev,
"Cannot allocate VF resources, try with fewer number of VFs\n");
if (!ice_config_res_vfs(pf))
return false;
}
/* Finish the reset on each VF */
for (v = 0; v < pf->num_alloc_vfs; v++) {
vf = &pf->vf[v];
vf->num_vf_qs = pf->num_vf_qps;
dev_dbg(&pf->pdev->dev,
"VF-id %d has %d queues configured\n",
vf->vf_id, vf->num_vf_qs);
ice_cleanup_and_realloc_vf(vf);
}
ice_flush(hw);
clear_bit(__ICE_VF_DIS, pf->state);
return true;
}
@ -1249,7 +1273,7 @@ static int ice_alloc_vfs(struct ice_pf *pf, u16 num_alloc_vfs)
/* Disable global interrupt 0 so we don't try to handle the VFLR. */
wr32(hw, GLINT_DYN_CTL(pf->oicr_idx),
ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S);
set_bit(__ICE_OICR_INTR_DIS, pf->state);
ice_flush(hw);
ret = pci_enable_sriov(pf->pdev, num_alloc_vfs);
@ -1278,13 +1302,13 @@ static int ice_alloc_vfs(struct ice_pf *pf, u16 num_alloc_vfs)
}
pf->num_alloc_vfs = num_alloc_vfs;
/* VF resources get allocated during reset */
if (!ice_reset_all_vfs(pf, true)) {
/* VF resources get allocated with initialization */
if (!ice_config_res_vfs(pf)) {
ret = -EIO;
goto err_unroll_sriov;
}
goto err_unroll_intr;
return ret;
err_unroll_sriov:
pf->vf = NULL;
@ -1296,6 +1320,7 @@ static int ice_alloc_vfs(struct ice_pf *pf, u16 num_alloc_vfs)
err_unroll_intr:
/* rearm interrupts here */
ice_irq_dynamic_ena(hw, NULL, NULL);
clear_bit(__ICE_OICR_INTR_DIS, pf->state);
return ret;
}