PCI/MSI: Support allocating virtual MSI interrupts

For NTB devices, we want to be able to trigger MSI interrupts
through a memory window. In these cases we may want to use
more interrupts than the NTB PCI device has available in its MSI-X
table.

We allow for this by creating a new 'virtual' interrupt. These
interrupts are allocated as usual but are not programmed into the
MSI-X table (as there may not be space for them).

The MSI address and data will then handled through an NTB MSI library
introduced later in this series.

Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
This commit is contained in:
Logan Gunthorpe 2019-05-23 16:30:51 -06:00 committed by Jon Mason
parent a944ccc3b0
commit d7cc609fb6
3 changed files with 62 additions and 9 deletions

View File

@ -192,6 +192,9 @@ static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
static void __iomem *pci_msix_desc_addr(struct msi_desc *desc) static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
{ {
if (desc->msi_attrib.is_virtual)
return NULL;
return desc->mask_base + return desc->mask_base +
desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
} }
@ -206,14 +209,19 @@ static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
{ {
u32 mask_bits = desc->masked; u32 mask_bits = desc->masked;
void __iomem *desc_addr;
if (pci_msi_ignore_mask) if (pci_msi_ignore_mask)
return 0; return 0;
desc_addr = pci_msix_desc_addr(desc);
if (!desc_addr)
return 0;
mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
if (flag) if (flag)
mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
writel(mask_bits, pci_msix_desc_addr(desc) + PCI_MSIX_ENTRY_VECTOR_CTRL);
writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
return mask_bits; return mask_bits;
} }
@ -273,6 +281,11 @@ void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
if (entry->msi_attrib.is_msix) { if (entry->msi_attrib.is_msix) {
void __iomem *base = pci_msix_desc_addr(entry); void __iomem *base = pci_msix_desc_addr(entry);
if (!base) {
WARN_ON(1);
return;
}
msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
msg->data = readl(base + PCI_MSIX_ENTRY_DATA); msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
@ -303,6 +316,9 @@ void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
} else if (entry->msi_attrib.is_msix) { } else if (entry->msi_attrib.is_msix) {
void __iomem *base = pci_msix_desc_addr(entry); void __iomem *base = pci_msix_desc_addr(entry);
if (!base)
goto skip;
writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
writel(msg->data, base + PCI_MSIX_ENTRY_DATA); writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
@ -327,7 +343,13 @@ void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
msg->data); msg->data);
} }
} }
skip:
entry->msg = *msg; entry->msg = *msg;
if (entry->write_msi_msg)
entry->write_msi_msg(entry, entry->write_msi_msg_data);
} }
void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
@ -550,6 +572,7 @@ msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
entry->msi_attrib.is_msix = 0; entry->msi_attrib.is_msix = 0;
entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
entry->msi_attrib.is_virtual = 0;
entry->msi_attrib.entry_nr = 0; entry->msi_attrib.entry_nr = 0;
entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
@ -674,6 +697,7 @@ static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
struct irq_affinity_desc *curmsk, *masks = NULL; struct irq_affinity_desc *curmsk, *masks = NULL;
struct msi_desc *entry; struct msi_desc *entry;
int ret, i; int ret, i;
int vec_count = pci_msix_vec_count(dev);
if (affd) if (affd)
masks = irq_create_affinity_masks(nvec, affd); masks = irq_create_affinity_masks(nvec, affd);
@ -696,6 +720,10 @@ static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
entry->msi_attrib.entry_nr = entries[i].entry; entry->msi_attrib.entry_nr = entries[i].entry;
else else
entry->msi_attrib.entry_nr = i; entry->msi_attrib.entry_nr = i;
entry->msi_attrib.is_virtual =
entry->msi_attrib.entry_nr >= vec_count;
entry->msi_attrib.default_irq = dev->irq; entry->msi_attrib.default_irq = dev->irq;
entry->mask_base = base; entry->mask_base = base;
@ -714,12 +742,19 @@ static void msix_program_entries(struct pci_dev *dev,
{ {
struct msi_desc *entry; struct msi_desc *entry;
int i = 0; int i = 0;
void __iomem *desc_addr;
for_each_pci_msi_entry(entry, dev) { for_each_pci_msi_entry(entry, dev) {
if (entries) if (entries)
entries[i++].vector = entry->irq; entries[i++].vector = entry->irq;
entry->masked = readl(pci_msix_desc_addr(entry) +
PCI_MSIX_ENTRY_VECTOR_CTRL); desc_addr = pci_msix_desc_addr(entry);
if (desc_addr)
entry->masked = readl(desc_addr +
PCI_MSIX_ENTRY_VECTOR_CTRL);
else
entry->masked = 0;
msix_mask_irq(entry, 1); msix_mask_irq(entry, 1);
} }
} }
@ -932,7 +967,7 @@ int pci_msix_vec_count(struct pci_dev *dev)
EXPORT_SYMBOL(pci_msix_vec_count); EXPORT_SYMBOL(pci_msix_vec_count);
static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
int nvec, struct irq_affinity *affd) int nvec, struct irq_affinity *affd, int flags)
{ {
int nr_entries; int nr_entries;
int i, j; int i, j;
@ -943,7 +978,7 @@ static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
nr_entries = pci_msix_vec_count(dev); nr_entries = pci_msix_vec_count(dev);
if (nr_entries < 0) if (nr_entries < 0)
return nr_entries; return nr_entries;
if (nvec > nr_entries) if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL))
return nr_entries; return nr_entries;
if (entries) { if (entries) {
@ -1079,7 +1114,8 @@ EXPORT_SYMBOL(pci_enable_msi);
static int __pci_enable_msix_range(struct pci_dev *dev, static int __pci_enable_msix_range(struct pci_dev *dev,
struct msix_entry *entries, int minvec, struct msix_entry *entries, int minvec,
int maxvec, struct irq_affinity *affd) int maxvec, struct irq_affinity *affd,
int flags)
{ {
int rc, nvec = maxvec; int rc, nvec = maxvec;
@ -1096,7 +1132,7 @@ static int __pci_enable_msix_range(struct pci_dev *dev,
return -ENOSPC; return -ENOSPC;
} }
rc = __pci_enable_msix(dev, entries, nvec, affd); rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
if (rc == 0) if (rc == 0)
return nvec; return nvec;
@ -1127,7 +1163,7 @@ static int __pci_enable_msix_range(struct pci_dev *dev,
int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
int minvec, int maxvec) int minvec, int maxvec)
{ {
return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL); return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0);
} }
EXPORT_SYMBOL(pci_enable_msix_range); EXPORT_SYMBOL(pci_enable_msix_range);
@ -1167,7 +1203,7 @@ int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
if (flags & PCI_IRQ_MSIX) { if (flags & PCI_IRQ_MSIX) {
msix_vecs = __pci_enable_msix_range(dev, NULL, min_vecs, msix_vecs = __pci_enable_msix_range(dev, NULL, min_vecs,
max_vecs, affd); max_vecs, affd, flags);
if (msix_vecs > 0) if (msix_vecs > 0)
return msix_vecs; return msix_vecs;
} }

View File

@ -64,6 +64,10 @@ struct ti_sci_inta_msi_desc {
* @msg: The last set MSI message cached for reuse * @msg: The last set MSI message cached for reuse
* @affinity: Optional pointer to a cpu affinity mask for this descriptor * @affinity: Optional pointer to a cpu affinity mask for this descriptor
* *
* @write_msi_msg: Callback that may be called when the MSI message
* address or data changes
* @write_msi_msg_data: Data parameter for the callback.
*
* @masked: [PCI MSI/X] Mask bits * @masked: [PCI MSI/X] Mask bits
* @is_msix: [PCI MSI/X] True if MSI-X * @is_msix: [PCI MSI/X] True if MSI-X
* @multiple: [PCI MSI/X] log2 num of messages allocated * @multiple: [PCI MSI/X] log2 num of messages allocated
@ -90,6 +94,9 @@ struct msi_desc {
const void *iommu_cookie; const void *iommu_cookie;
#endif #endif
void (*write_msi_msg)(struct msi_desc *entry, void *data);
void *write_msi_msg_data;
union { union {
/* PCI MSI/X specific data */ /* PCI MSI/X specific data */
struct { struct {
@ -100,6 +107,7 @@ struct msi_desc {
u8 multi_cap : 3; u8 multi_cap : 3;
u8 maskbit : 1; u8 maskbit : 1;
u8 is_64 : 1; u8 is_64 : 1;
u8 is_virtual : 1;
u16 entry_nr; u16 entry_nr;
unsigned default_irq; unsigned default_irq;
} msi_attrib; } msi_attrib;

View File

@ -1362,6 +1362,15 @@ int pci_set_vga_state(struct pci_dev *pdev, bool decode,
#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
/*
* Virtual interrupts allow for more interrupts to be allocated
* than the device has interrupts for. These are not programmed
* into the device's MSI-X table and must be handled by some
* other driver means.
*/
#define PCI_IRQ_VIRTUAL (1 << 4)
#define PCI_IRQ_ALL_TYPES \ #define PCI_IRQ_ALL_TYPES \
(PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)