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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/i915: make intel_crtc_load_lut static
And move it so it doesn't need a forward declaration. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3282,6 +3282,84 @@ static void intel_disable_planes(struct drm_crtc *crtc)
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intel_plane_disable(&intel_plane->base);
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}
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static void hsw_enable_ips(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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if (!crtc->config.ips_enabled)
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return;
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/* We can only enable IPS after we enable a plane and wait for a vblank.
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* We guarantee that the plane is enabled by calling intel_enable_ips
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* only after intel_enable_plane. And intel_enable_plane already waits
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* for a vblank, so all we need to do here is to enable the IPS bit. */
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assert_plane_enabled(dev_priv, crtc->plane);
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I915_WRITE(IPS_CTL, IPS_ENABLE);
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}
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static void hsw_disable_ips(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (!crtc->config.ips_enabled)
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return;
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assert_plane_enabled(dev_priv, crtc->plane);
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I915_WRITE(IPS_CTL, 0);
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POSTING_READ(IPS_CTL);
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/* We need to wait for a vblank before we can disable the plane. */
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intel_wait_for_vblank(dev, crtc->pipe);
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}
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/** Loads the palette/gamma unit for the CRTC with the prepared values */
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static void intel_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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enum pipe pipe = intel_crtc->pipe;
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int palreg = PALETTE(pipe);
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int i;
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bool reenable_ips = false;
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/* The clocks have to be on to load the palette. */
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if (!crtc->enabled || !intel_crtc->active)
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return;
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if (!HAS_PCH_SPLIT(dev_priv->dev)) {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
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assert_dsi_pll_enabled(dev_priv);
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else
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assert_pll_enabled(dev_priv, pipe);
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}
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/* use legacy palette for Ironlake */
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if (HAS_PCH_SPLIT(dev))
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palreg = LGC_PALETTE(pipe);
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/* Workaround : Do not read or write the pipe palette/gamma data while
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* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
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*/
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if (intel_crtc->config.ips_enabled &&
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((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
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GAMMA_MODE_MODE_SPLIT)) {
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hsw_disable_ips(intel_crtc);
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reenable_ips = true;
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}
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for (i = 0; i < 256; i++) {
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I915_WRITE(palreg + 4 * i,
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(intel_crtc->lut_r[i] << 16) |
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(intel_crtc->lut_g[i] << 8) |
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intel_crtc->lut_b[i]);
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}
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if (reenable_ips)
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hsw_enable_ips(intel_crtc);
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}
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static void ironlake_crtc_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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@ -3360,37 +3438,6 @@ static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
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return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
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}
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static void hsw_enable_ips(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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if (!crtc->config.ips_enabled)
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return;
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/* We can only enable IPS after we enable a plane and wait for a vblank.
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* We guarantee that the plane is enabled by calling intel_enable_ips
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* only after intel_enable_plane. And intel_enable_plane already waits
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* for a vblank, so all we need to do here is to enable the IPS bit. */
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assert_plane_enabled(dev_priv, crtc->plane);
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I915_WRITE(IPS_CTL, IPS_ENABLE);
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}
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static void hsw_disable_ips(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (!crtc->config.ips_enabled)
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return;
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assert_plane_enabled(dev_priv, crtc->plane);
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I915_WRITE(IPS_CTL, 0);
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POSTING_READ(IPS_CTL);
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/* We need to wait for a vblank before we can disable the plane. */
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intel_wait_for_vblank(dev, crtc->pipe);
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}
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static void haswell_crtc_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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@ -6786,53 +6833,6 @@ void intel_write_eld(struct drm_encoder *encoder,
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dev_priv->display.write_eld(connector, crtc);
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}
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/** Loads the palette/gamma unit for the CRTC with the prepared values */
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void intel_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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enum pipe pipe = intel_crtc->pipe;
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int palreg = PALETTE(pipe);
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int i;
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bool reenable_ips = false;
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/* The clocks have to be on to load the palette. */
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if (!crtc->enabled || !intel_crtc->active)
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return;
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if (!HAS_PCH_SPLIT(dev_priv->dev)) {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
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assert_dsi_pll_enabled(dev_priv);
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else
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assert_pll_enabled(dev_priv, pipe);
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}
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/* use legacy palette for Ironlake */
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if (HAS_PCH_SPLIT(dev))
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palreg = LGC_PALETTE(pipe);
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/* Workaround : Do not read or write the pipe palette/gamma data while
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* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
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*/
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if (intel_crtc->config.ips_enabled &&
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((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
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GAMMA_MODE_MODE_SPLIT)) {
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hsw_disable_ips(intel_crtc);
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reenable_ips = true;
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}
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for (i = 0; i < 256; i++) {
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I915_WRITE(palreg + 4 * i,
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(intel_crtc->lut_r[i] << 16) |
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(intel_crtc->lut_g[i] << 8) |
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intel_crtc->lut_b[i]);
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}
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if (reenable_ips)
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hsw_enable_ips(intel_crtc);
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}
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static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
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{
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struct drm_device *dev = crtc->dev;
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@ -613,7 +613,6 @@ extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
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struct intel_ring_buffer *ring);
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extern void intel_mark_idle(struct drm_device *dev);
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extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
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extern void intel_crtc_load_lut(struct drm_crtc *crtc);
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extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
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extern void intel_encoder_destroy(struct drm_encoder *encoder);
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extern void intel_connector_dpms(struct drm_connector *, int mode);
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