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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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net: stmmac: Add DMA related callbacks for XGMAC2
Add the DMA related callbacks for the new IP block XGMAC2. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: David S. Miller <davem@davemloft.net> Cc: Joao Pinto <jpinto@synopsys.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jose Abreu
David S. Miller
parent
2142754f8b
commit
d6ddfacd95
@ -5,7 +5,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
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dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
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mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o \
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dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \
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stmmac_tc.o dwxgmac2_core.o $(stmmac-y)
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stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o $(stmmac-y)
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# Ordering matters. Generic driver must be last.
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obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o
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@ -138,4 +138,61 @@
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#define XGMAC_ABPSIS BIT(1)
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#define XGMAC_TXUNFIS BIT(0)
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/* DMA Registers */
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#define XGMAC_DMA_MODE 0x00003000
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#define XGMAC_SWR BIT(0)
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#define XGMAC_DMA_SYSBUS_MODE 0x00003004
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#define XGMAC_WR_OSR_LMT GENMASK(29, 24)
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#define XGMAC_WR_OSR_LMT_SHIFT 24
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#define XGMAC_RD_OSR_LMT GENMASK(21, 16)
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#define XGMAC_RD_OSR_LMT_SHIFT 16
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#define XGMAC_EN_LPI BIT(15)
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#define XGMAC_LPI_XIT_PKT BIT(14)
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#define XGMAC_AAL BIT(12)
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#define XGMAC_BLEN GENMASK(7, 1)
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#define XGMAC_BLEN256 BIT(7)
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#define XGMAC_BLEN128 BIT(6)
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#define XGMAC_BLEN64 BIT(5)
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#define XGMAC_BLEN32 BIT(4)
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#define XGMAC_BLEN16 BIT(3)
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#define XGMAC_BLEN8 BIT(2)
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#define XGMAC_BLEN4 BIT(1)
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#define XGMAC_UNDEF BIT(0)
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#define XGMAC_DMA_CH_CONTROL(x) (0x00003100 + (0x80 * (x)))
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#define XGMAC_PBLx8 BIT(16)
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#define XGMAC_DMA_CH_TX_CONTROL(x) (0x00003104 + (0x80 * (x)))
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#define XGMAC_TxPBL GENMASK(21, 16)
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#define XGMAC_TxPBL_SHIFT 16
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#define XGMAC_TSE BIT(12)
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#define XGMAC_OSP BIT(4)
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#define XGMAC_TXST BIT(0)
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#define XGMAC_DMA_CH_RX_CONTROL(x) (0x00003108 + (0x80 * (x)))
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#define XGMAC_RxPBL GENMASK(21, 16)
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#define XGMAC_RxPBL_SHIFT 16
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#define XGMAC_RXST BIT(0)
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#define XGMAC_DMA_CH_TxDESC_LADDR(x) (0x00003114 + (0x80 * (x)))
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#define XGMAC_DMA_CH_RxDESC_LADDR(x) (0x0000311c + (0x80 * (x)))
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#define XGMAC_DMA_CH_TxDESC_TAIL_LPTR(x) (0x00003124 + (0x80 * (x)))
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#define XGMAC_DMA_CH_RxDESC_TAIL_LPTR(x) (0x0000312c + (0x80 * (x)))
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#define XGMAC_DMA_CH_TxDESC_RING_LEN(x) (0x00003130 + (0x80 * (x)))
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#define XGMAC_DMA_CH_RxDESC_RING_LEN(x) (0x00003134 + (0x80 * (x)))
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#define XGMAC_DMA_CH_INT_EN(x) (0x00003138 + (0x80 * (x)))
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#define XGMAC_NIE BIT(15)
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#define XGMAC_AIE BIT(14)
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#define XGMAC_RBUE BIT(7)
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#define XGMAC_RIE BIT(6)
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#define XGMAC_TIE BIT(0)
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#define XGMAC_DMA_INT_DEFAULT_EN (XGMAC_NIE | XGMAC_AIE | XGMAC_RBUE | \
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XGMAC_RIE | XGMAC_TIE)
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#define XGMAC_DMA_CH_Rx_WATCHDOG(x) (0x0000313c + (0x80 * (x)))
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#define XGMAC_RWT GENMASK(7, 0)
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#define XGMAC_DMA_CH_STATUS(x) (0x00003160 + (0x80 * (x)))
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#define XGMAC_NIS BIT(15)
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#define XGMAC_AIS BIT(14)
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#define XGMAC_FBE BIT(12)
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#define XGMAC_RBU BIT(7)
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#define XGMAC_RI BIT(6)
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#define XGMAC_TPS BIT(1)
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#define XGMAC_TI BIT(0)
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#endif /* __STMMAC_DWXGMAC2_H__ */
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411
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
Normal file
411
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
Normal file
@ -0,0 +1,411 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
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* stmmac XGMAC support.
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*/
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#include <linux/iopoll.h>
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#include "stmmac.h"
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#include "dwxgmac2.h"
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static int dwxgmac2_dma_reset(void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr + XGMAC_DMA_MODE);
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/* DMA SW reset */
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writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE);
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return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value,
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!(value & XGMAC_SWR), 0, 100000);
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}
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static void dwxgmac2_dma_init(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg, int atds)
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{
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u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
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if (dma_cfg->aal)
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value |= XGMAC_AAL;
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writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
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}
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static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg, u32 chan)
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{
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u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
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if (dma_cfg->pblx8)
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value |= XGMAC_PBLx8;
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writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
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writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
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}
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static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_rx_phy, u32 chan)
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{
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u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
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u32 value;
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value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
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value &= ~XGMAC_RxPBL;
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value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
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writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
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writel(dma_rx_phy, ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
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}
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static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_tx_phy, u32 chan)
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{
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u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
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u32 value;
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value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
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value &= ~XGMAC_TxPBL;
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value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL;
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value |= XGMAC_OSP;
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writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
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writel(dma_tx_phy, ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
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}
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static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
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{
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u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
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int i;
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if (axi->axi_lpi_en)
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value |= XGMAC_EN_LPI;
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if (axi->axi_xit_frm)
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value |= XGMAC_LPI_XIT_PKT;
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value &= ~XGMAC_WR_OSR_LMT;
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value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) &
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XGMAC_WR_OSR_LMT;
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value &= ~XGMAC_RD_OSR_LMT;
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value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
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XGMAC_RD_OSR_LMT;
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value &= ~XGMAC_BLEN;
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for (i = 0; i < AXI_BLEN; i++) {
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if (axi->axi_blen[i])
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value &= ~XGMAC_UNDEF;
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switch (axi->axi_blen[i]) {
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case 256:
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value |= XGMAC_BLEN256;
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break;
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case 128:
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value |= XGMAC_BLEN128;
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break;
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case 64:
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value |= XGMAC_BLEN64;
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break;
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case 32:
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value |= XGMAC_BLEN32;
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break;
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case 16:
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value |= XGMAC_BLEN16;
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break;
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case 8:
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value |= XGMAC_BLEN8;
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break;
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case 4:
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value |= XGMAC_BLEN4;
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break;
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}
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}
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writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
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}
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static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
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u32 channel, int fifosz, u8 qmode)
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{
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u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
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unsigned int rqs = fifosz / 256 - 1;
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if (mode == SF_DMA_MODE) {
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value |= XGMAC_RSF;
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} else {
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value &= ~XGMAC_RSF;
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value &= ~XGMAC_RTC;
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if (mode <= 64)
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value |= 0x0 << XGMAC_RTC_SHIFT;
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else if (mode <= 96)
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value |= 0x2 << XGMAC_RTC_SHIFT;
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else
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value |= 0x3 << XGMAC_RTC_SHIFT;
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}
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value &= ~XGMAC_RQS;
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value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;
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writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
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/* Enable MTL RX overflow */
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value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));
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writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel));
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}
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static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode,
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u32 channel, int fifosz, u8 qmode)
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{
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u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
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unsigned int tqs = fifosz / 256 - 1;
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if (mode == SF_DMA_MODE) {
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value |= XGMAC_TSF;
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} else {
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value &= ~XGMAC_TSF;
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value &= ~XGMAC_TTC;
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if (mode <= 64)
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value |= 0x0 << XGMAC_TTC_SHIFT;
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else if (mode <= 96)
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value |= 0x2 << XGMAC_TTC_SHIFT;
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else if (mode <= 128)
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value |= 0x3 << XGMAC_TTC_SHIFT;
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else if (mode <= 192)
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value |= 0x4 << XGMAC_TTC_SHIFT;
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else if (mode <= 256)
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value |= 0x5 << XGMAC_TTC_SHIFT;
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else if (mode <= 384)
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value |= 0x6 << XGMAC_TTC_SHIFT;
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else
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value |= 0x7 << XGMAC_TTC_SHIFT;
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}
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value &= ~XGMAC_TXQEN;
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if (qmode != MTL_QUEUE_AVB)
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value |= 0x2 << XGMAC_TXQEN_SHIFT;
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else
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value |= 0x1 << XGMAC_TXQEN_SHIFT;
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value &= ~XGMAC_TQS;
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value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS;
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writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
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}
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static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan)
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{
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writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
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}
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static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan)
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{
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writel(0, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
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}
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static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan)
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{
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u32 value;
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value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
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value |= XGMAC_TXST;
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writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
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value = readl(ioaddr + XGMAC_TX_CONFIG);
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value |= XGMAC_CONFIG_TE;
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writel(value, ioaddr + XGMAC_TX_CONFIG);
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}
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static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan)
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{
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u32 value;
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value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
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value &= ~XGMAC_TXST;
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writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
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value = readl(ioaddr + XGMAC_TX_CONFIG);
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value &= ~XGMAC_CONFIG_TE;
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writel(value, ioaddr + XGMAC_TX_CONFIG);
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}
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static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan)
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{
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u32 value;
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value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
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value |= XGMAC_RXST;
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writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
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value = readl(ioaddr + XGMAC_RX_CONFIG);
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value |= XGMAC_CONFIG_RE;
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writel(value, ioaddr + XGMAC_RX_CONFIG);
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}
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static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan)
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{
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u32 value;
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value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
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value &= ~XGMAC_RXST;
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writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
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value = readl(ioaddr + XGMAC_RX_CONFIG);
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value &= ~XGMAC_CONFIG_RE;
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writel(value, ioaddr + XGMAC_RX_CONFIG);
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}
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static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
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struct stmmac_extra_stats *x, u32 chan)
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{
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u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));
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int ret = 0;
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/* ABNORMAL interrupts */
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if (unlikely(intr_status & XGMAC_AIS)) {
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if (unlikely(intr_status & XGMAC_TPS)) {
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x->tx_process_stopped_irq++;
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ret |= tx_hard_error;
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}
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if (unlikely(intr_status & XGMAC_FBE)) {
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x->fatal_bus_error_irq++;
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ret |= tx_hard_error;
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}
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}
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/* TX/RX NORMAL interrupts */
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if (likely(intr_status & XGMAC_NIS)) {
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x->normal_irq_n++;
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if (likely(intr_status & XGMAC_RI)) {
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u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
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if (likely(value & XGMAC_RIE)) {
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x->rx_normal_irq_n++;
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ret |= handle_rx;
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}
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}
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if (likely(intr_status & XGMAC_TI)) {
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x->tx_normal_irq_n++;
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ret |= handle_tx;
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}
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}
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/* Clear interrupts */
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writel(~0x0, ioaddr + XGMAC_DMA_CH_STATUS(chan));
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return ret;
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}
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static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
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struct dma_features *dma_cap)
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{
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u32 hw_cap;
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/* MAC HW feature 0 */
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hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);
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dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16;
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dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14;
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dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
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dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
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dma_cap->av &= (hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10;
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dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
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dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
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dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;
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/* MAC HW feature 1 */
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hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
|
||||
dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18;
|
||||
dma_cap->tx_fifo_size =
|
||||
128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6);
|
||||
dma_cap->rx_fifo_size =
|
||||
128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0);
|
||||
|
||||
/* MAC HW feature 2 */
|
||||
hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
|
||||
dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24;
|
||||
dma_cap->number_tx_channel =
|
||||
((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1;
|
||||
dma_cap->number_rx_channel =
|
||||
((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1;
|
||||
dma_cap->number_tx_queues =
|
||||
((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1;
|
||||
dma_cap->number_rx_queues =
|
||||
((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1;
|
||||
}
|
||||
|
||||
static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
for (i = 0; i < nchan; i++)
|
||||
writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(i));
|
||||
}
|
||||
|
||||
static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
|
||||
{
|
||||
writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));
|
||||
}
|
||||
|
||||
static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
|
||||
{
|
||||
writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan));
|
||||
}
|
||||
|
||||
static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
|
||||
{
|
||||
writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan));
|
||||
}
|
||||
|
||||
static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
|
||||
{
|
||||
writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan));
|
||||
}
|
||||
|
||||
static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
|
||||
{
|
||||
u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
|
||||
|
||||
if (en)
|
||||
value |= XGMAC_TSE;
|
||||
else
|
||||
value &= ~XGMAC_TSE;
|
||||
|
||||
writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
|
||||
}
|
||||
|
||||
static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
|
||||
value |= bfsize << 1;
|
||||
writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
|
||||
}
|
||||
|
||||
const struct stmmac_dma_ops dwxgmac210_dma_ops = {
|
||||
.reset = dwxgmac2_dma_reset,
|
||||
.init = dwxgmac2_dma_init,
|
||||
.init_chan = dwxgmac2_dma_init_chan,
|
||||
.init_rx_chan = dwxgmac2_dma_init_rx_chan,
|
||||
.init_tx_chan = dwxgmac2_dma_init_tx_chan,
|
||||
.axi = dwxgmac2_dma_axi,
|
||||
.dump_regs = NULL,
|
||||
.dma_rx_mode = dwxgmac2_dma_rx_mode,
|
||||
.dma_tx_mode = dwxgmac2_dma_tx_mode,
|
||||
.enable_dma_irq = dwxgmac2_enable_dma_irq,
|
||||
.disable_dma_irq = dwxgmac2_disable_dma_irq,
|
||||
.start_tx = dwxgmac2_dma_start_tx,
|
||||
.stop_tx = dwxgmac2_dma_stop_tx,
|
||||
.start_rx = dwxgmac2_dma_start_rx,
|
||||
.stop_rx = dwxgmac2_dma_stop_rx,
|
||||
.dma_interrupt = dwxgmac2_dma_interrupt,
|
||||
.get_hw_feature = dwxgmac2_get_hw_feature,
|
||||
.rx_watchdog = dwxgmac2_rx_watchdog,
|
||||
.set_rx_ring_len = dwxgmac2_set_rx_ring_len,
|
||||
.set_tx_ring_len = dwxgmac2_set_tx_ring_len,
|
||||
.set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
|
||||
.set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
|
||||
.enable_tso = dwxgmac2_enable_tso,
|
||||
.set_bfsize = dwxgmac2_set_bfsize,
|
||||
};
|
||||
@ -197,7 +197,7 @@ static const struct stmmac_hwif_entry {
|
||||
.mmc_off = 0,
|
||||
},
|
||||
.desc = NULL,
|
||||
.dma = NULL,
|
||||
.dma = &dwxgmac210_dma_ops,
|
||||
.mac = &dwxgmac210_ops,
|
||||
.hwtimestamp = NULL,
|
||||
.mode = NULL,
|
||||
|
||||
@ -480,6 +480,7 @@ extern const struct stmmac_dma_ops dwmac410_dma_ops;
|
||||
extern const struct stmmac_ops dwmac510_ops;
|
||||
extern const struct stmmac_tc_ops dwmac510_tc_ops;
|
||||
extern const struct stmmac_ops dwxgmac210_ops;
|
||||
extern const struct stmmac_dma_ops dwxgmac210_dma_ops;
|
||||
|
||||
#define GMAC_VERSION 0x00000020 /* GMAC CORE Version */
|
||||
#define GMAC4_VERSION 0x00000110 /* GMAC4+ CORE Version */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user